1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-clkc.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11 12/ { 13 compatible = "amlogic,meson-axg"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 /* 16 MiB reserved for Hardware ROM Firmware */ 25 hwrom_reserved: hwrom@0 { 26 reg = <0x0 0x0 0x0 0x1000000>; 27 no-map; 28 }; 29 30 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 31 secmon_reserved: secmon@5000000 { 32 reg = <0x0 0x05000000 0x0 0x300000>; 33 no-map; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <0x2>; 39 #size-cells = <0x0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53", "arm,armv8"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <0x0 0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x2>; 61 enable-method = "psci"; 62 next-level-cache = <&l2>; 63 }; 64 65 cpu3: cpu@3 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 reg = <0x0 0x3>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 }; 72 73 l2: l2-cache0 { 74 compatible = "cache"; 75 }; 76 }; 77 78 arm-pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 interrupts = <GIC_PPI 13 95 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 97 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 10 101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 102 }; 103 104 xtal: xtal-clk { 105 compatible = "fixed-clock"; 106 clock-frequency = <24000000>; 107 clock-output-names = "xtal"; 108 #clock-cells = <0>; 109 }; 110 111 ao_alt_xtal: ao_alt_xtal-clk { 112 compatible = "fixed-clock"; 113 clock-frequency = <32000000>; 114 clock-output-names = "ao_alt_xtal"; 115 #clock-cells = <0>; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges; 123 124 apb: apb@ffe00000 { 125 compatible = "simple-bus"; 126 reg = <0x0 0xffe00000 0x0 0x200000>; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 130 131 sd_emmc_b: sd@5000 { 132 compatible = "amlogic,meson-axg-mmc"; 133 reg = <0x0 0x5000 0x0 0x2000>; 134 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 135 status = "disabled"; 136 clocks = <&clkc CLKID_SD_EMMC_B>, 137 <&clkc CLKID_SD_EMMC_B_CLK0>, 138 <&clkc CLKID_FCLK_DIV2>; 139 clock-names = "core", "clkin0", "clkin1"; 140 }; 141 142 sd_emmc_c: mmc@7000 { 143 compatible = "amlogic,meson-axg-mmc"; 144 reg = <0x0 0x7000 0x0 0x2000>; 145 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 146 status = "disabled"; 147 clocks = <&clkc CLKID_SD_EMMC_C>, 148 <&clkc CLKID_SD_EMMC_C_CLK0>, 149 <&clkc CLKID_FCLK_DIV2>; 150 clock-names = "core", "clkin0", "clkin1"; 151 }; 152 }; 153 154 cbus: bus@ffd00000 { 155 compatible = "simple-bus"; 156 reg = <0x0 0xffd00000 0x0 0x25000>; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 160 161 gpio_intc: interrupt-controller@f080 { 162 compatible = "amlogic,meson-gpio-intc"; 163 reg = <0x0 0xf080 0x0 0x10>; 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 167 status = "disabled"; 168 }; 169 170 pwm_ab: pwm@1b000 { 171 compatible = "amlogic,meson-axg-ee-pwm"; 172 reg = <0x0 0x1b000 0x0 0x20>; 173 #pwm-cells = <3>; 174 status = "disabled"; 175 }; 176 177 pwm_cd: pwm@1a000 { 178 compatible = "amlogic,meson-axg-ee-pwm"; 179 reg = <0x0 0x1a000 0x0 0x20>; 180 #pwm-cells = <3>; 181 status = "disabled"; 182 }; 183 184 reset: reset-controller@1004 { 185 compatible = "amlogic,meson-axg-reset"; 186 reg = <0x0 0x01004 0x0 0x9c>; 187 #reset-cells = <1>; 188 }; 189 190 spicc0: spi@13000 { 191 compatible = "amlogic,meson-axg-spicc"; 192 reg = <0x0 0x13000 0x0 0x3c>; 193 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&clkc CLKID_SPICC0>; 195 clock-names = "core"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 status = "disabled"; 199 }; 200 201 spicc1: spi@15000 { 202 compatible = "amlogic,meson-axg-spicc"; 203 reg = <0x0 0x15000 0x0 0x3c>; 204 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&clkc CLKID_SPICC1>; 206 clock-names = "core"; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 status = "disabled"; 210 }; 211 212 i2c0: i2c@1f000 { 213 compatible = "amlogic,meson-axg-i2c"; 214 status = "disabled"; 215 reg = <0x0 0x1f000 0x0 0x20>; 216 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 217 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 clocks = <&clkc CLKID_I2C>; 221 clock-names = "clk_i2c"; 222 }; 223 224 i2c1: i2c@1e000 { 225 compatible = "amlogic,meson-axg-i2c"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <0x0 0x1e000 0x0 0x20>; 229 status = "disabled"; 230 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 232 clocks = <&clkc CLKID_I2C>; 233 clock-names = "clk_i2c"; 234 }; 235 236 i2c2: i2c@1d000 { 237 compatible = "amlogic,meson-axg-i2c"; 238 status = "disabled"; 239 reg = <0x0 0x1d000 0x0 0x20>; 240 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 clocks = <&clkc CLKID_I2C>; 245 clock-names = "clk_i2c"; 246 }; 247 248 i2c3: i2c@1c000 { 249 compatible = "amlogic,meson-axg-i2c"; 250 status = "disabled"; 251 reg = <0x0 0x1c000 0x0 0x20>; 252 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 clocks = <&clkc CLKID_I2C>; 257 clock-names = "clk_i2c"; 258 }; 259 260 uart_A: serial@24000 { 261 compatible = "amlogic,meson-gx-uart"; 262 reg = <0x0 0x24000 0x0 0x18>; 263 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 264 status = "disabled"; 265 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 266 clock-names = "xtal", "pclk", "baud"; 267 }; 268 269 uart_B: serial@23000 { 270 compatible = "amlogic,meson-gx-uart"; 271 reg = <0x0 0x23000 0x0 0x18>; 272 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 273 status = "disabled"; 274 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 275 clock-names = "xtal", "pclk", "baud"; 276 }; 277 }; 278 279 ethmac: ethernet@ff3f0000 { 280 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 281 reg = <0x0 0xff3f0000 0x0 0x10000 282 0x0 0xff634540 0x0 0x8>; 283 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 284 interrupt-names = "macirq"; 285 clocks = <&clkc CLKID_ETH>, 286 <&clkc CLKID_FCLK_DIV2>, 287 <&clkc CLKID_MPLL2>; 288 clock-names = "stmmaceth", "clkin0", "clkin1"; 289 status = "disabled"; 290 }; 291 292 gic: interrupt-controller@ffc01000 { 293 compatible = "arm,gic-400"; 294 reg = <0x0 0xffc01000 0 0x1000>, 295 <0x0 0xffc02000 0 0x2000>, 296 <0x0 0xffc04000 0 0x2000>, 297 <0x0 0xffc06000 0 0x2000>; 298 interrupt-controller; 299 interrupts = <GIC_PPI 9 300 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 301 #interrupt-cells = <3>; 302 #address-cells = <0>; 303 }; 304 305 hiubus: bus@ff63c000 { 306 compatible = "simple-bus"; 307 reg = <0x0 0xff63c000 0x0 0x1c00>; 308 #address-cells = <2>; 309 #size-cells = <2>; 310 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 311 312 sysctrl: system-controller@0 { 313 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd"; 314 reg = <0 0 0 0x400>; 315 316 clkc: clock-controller { 317 compatible = "amlogic,axg-clkc"; 318 #clock-cells = <1>; 319 }; 320 }; 321 }; 322 323 mailbox: mailbox@ff63dc00 { 324 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 325 reg = <0 0xff63dc00 0 0x400>; 326 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 329 #mbox-cells = <1>; 330 }; 331 332 periphs: periphs@ff634000 { 333 compatible = "simple-bus"; 334 reg = <0x0 0xff634000 0x0 0x2000>; 335 #address-cells = <2>; 336 #size-cells = <2>; 337 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 338 339 hwrng: rng { 340 compatible = "amlogic,meson-rng"; 341 reg = <0x0 0x18 0x0 0x4>; 342 clocks = <&clkc CLKID_RNG0>; 343 clock-names = "core"; 344 }; 345 346 pinctrl_periphs: pinctrl@480 { 347 compatible = "amlogic,meson-axg-periphs-pinctrl"; 348 #address-cells = <2>; 349 #size-cells = <2>; 350 ranges; 351 352 gpio: bank@480 { 353 reg = <0x0 0x00480 0x0 0x40>, 354 <0x0 0x004e8 0x0 0x14>, 355 <0x0 0x00520 0x0 0x14>, 356 <0x0 0x00430 0x0 0x3c>; 357 reg-names = "mux", "pull", "pull-enable", "gpio"; 358 gpio-controller; 359 #gpio-cells = <2>; 360 gpio-ranges = <&pinctrl_periphs 0 0 86>; 361 }; 362 363 emmc_pins: emmc { 364 mux { 365 groups = "emmc_nand_d0", 366 "emmc_nand_d1", 367 "emmc_nand_d2", 368 "emmc_nand_d3", 369 "emmc_nand_d4", 370 "emmc_nand_d5", 371 "emmc_nand_d6", 372 "emmc_nand_d7", 373 "emmc_clk", 374 "emmc_cmd", 375 "emmc_ds"; 376 function = "emmc"; 377 }; 378 }; 379 380 emmc_clk_gate_pins: emmc_clk_gate { 381 mux { 382 groups = "BOOT_8"; 383 function = "gpio_periphs"; 384 }; 385 cfg-pull-down { 386 pins = "BOOT_8"; 387 bias-pull-down; 388 }; 389 }; 390 391 sdio_pins: sdio { 392 mux { 393 groups = "sdio_d0", 394 "sdio_d1", 395 "sdio_d2", 396 "sdio_d3", 397 "sdio_cmd", 398 "sdio_clk"; 399 function = "sdio"; 400 }; 401 }; 402 403 sdio_clk_gate_pins: sdio_clk_gate { 404 mux { 405 groups = "GPIOX_4"; 406 function = "gpio_periphs"; 407 }; 408 cfg-pull-down { 409 pins = "GPIOX_4"; 410 bias-pull-down; 411 }; 412 }; 413 414 eth_rmii_x_pins: eth-x-rmii { 415 mux { 416 groups = "eth_mdio_x", 417 "eth_mdc_x", 418 "eth_rgmii_rx_clk_x", 419 "eth_rx_dv_x", 420 "eth_rxd0_x", 421 "eth_rxd1_x", 422 "eth_txen_x", 423 "eth_txd0_x", 424 "eth_txd1_x"; 425 function = "eth"; 426 }; 427 }; 428 429 eth_rmii_y_pins: eth-y-rmii { 430 mux { 431 groups = "eth_mdio_y", 432 "eth_mdc_y", 433 "eth_rgmii_rx_clk_y", 434 "eth_rx_dv_y", 435 "eth_rxd0_y", 436 "eth_rxd1_y", 437 "eth_txen_y", 438 "eth_txd0_y", 439 "eth_txd1_y"; 440 function = "eth"; 441 }; 442 }; 443 444 eth_rgmii_x_pins: eth-x-rgmii { 445 mux { 446 groups = "eth_mdio_x", 447 "eth_mdc_x", 448 "eth_rgmii_rx_clk_x", 449 "eth_rx_dv_x", 450 "eth_rxd0_x", 451 "eth_rxd1_x", 452 "eth_rxd2_rgmii", 453 "eth_rxd3_rgmii", 454 "eth_rgmii_tx_clk", 455 "eth_txen_x", 456 "eth_txd0_x", 457 "eth_txd1_x", 458 "eth_txd2_rgmii", 459 "eth_txd3_rgmii"; 460 function = "eth"; 461 }; 462 }; 463 464 eth_rgmii_y_pins: eth-y-rgmii { 465 mux { 466 groups = "eth_mdio_y", 467 "eth_mdc_y", 468 "eth_rgmii_rx_clk_y", 469 "eth_rx_dv_y", 470 "eth_rxd0_y", 471 "eth_rxd1_y", 472 "eth_rxd2_rgmii", 473 "eth_rxd3_rgmii", 474 "eth_rgmii_tx_clk", 475 "eth_txen_y", 476 "eth_txd0_y", 477 "eth_txd1_y", 478 "eth_txd2_rgmii", 479 "eth_txd3_rgmii"; 480 function = "eth"; 481 }; 482 }; 483 484 pwm_a_a_pins: pwm_a_a { 485 mux { 486 groups = "pwm_a_a"; 487 function = "pwm_a"; 488 }; 489 }; 490 491 pwm_a_x18_pins: pwm_a_x18 { 492 mux { 493 groups = "pwm_a_x18"; 494 function = "pwm_a"; 495 }; 496 }; 497 498 pwm_a_x20_pins: pwm_a_x20 { 499 mux { 500 groups = "pwm_a_x20"; 501 function = "pwm_a"; 502 }; 503 }; 504 505 pwm_a_z_pins: pwm_a_z { 506 mux { 507 groups = "pwm_a_z"; 508 function = "pwm_a"; 509 }; 510 }; 511 512 pwm_b_a_pins: pwm_b_a { 513 mux { 514 groups = "pwm_b_a"; 515 function = "pwm_b"; 516 }; 517 }; 518 519 pwm_b_x_pins: pwm_b_x { 520 mux { 521 groups = "pwm_b_x"; 522 function = "pwm_b"; 523 }; 524 }; 525 526 pwm_b_z_pins: pwm_b_z { 527 mux { 528 groups = "pwm_b_z"; 529 function = "pwm_b"; 530 }; 531 }; 532 533 pwm_c_a_pins: pwm_c_a { 534 mux { 535 groups = "pwm_c_a"; 536 function = "pwm_c"; 537 }; 538 }; 539 540 pwm_c_x10_pins: pwm_c_x10 { 541 mux { 542 groups = "pwm_c_x10"; 543 function = "pwm_c"; 544 }; 545 }; 546 547 pwm_c_x17_pins: pwm_c_x17 { 548 mux { 549 groups = "pwm_c_x17"; 550 function = "pwm_c"; 551 }; 552 }; 553 554 pwm_d_x11_pins: pwm_d_x11 { 555 mux { 556 groups = "pwm_d_x11"; 557 function = "pwm_d"; 558 }; 559 }; 560 561 pwm_d_x16_pins: pwm_d_x16 { 562 mux { 563 groups = "pwm_d_x16"; 564 function = "pwm_d"; 565 }; 566 }; 567 568 spi0_pins: spi0 { 569 mux { 570 groups = "spi0_miso", 571 "spi0_mosi", 572 "spi0_clk"; 573 function = "spi0"; 574 }; 575 }; 576 577 spi0_ss0_pins: spi0_ss0 { 578 mux { 579 groups = "spi0_ss0"; 580 function = "spi0"; 581 }; 582 }; 583 584 spi0_ss1_pins: spi0_ss1 { 585 mux { 586 groups = "spi0_ss1"; 587 function = "spi0"; 588 }; 589 }; 590 591 spi0_ss2_pins: spi0_ss2 { 592 mux { 593 groups = "spi0_ss2"; 594 function = "spi0"; 595 }; 596 }; 597 598 599 spi1_a_pins: spi1_a { 600 mux { 601 groups = "spi1_miso_a", 602 "spi1_mosi_a", 603 "spi1_clk_a"; 604 function = "spi1"; 605 }; 606 }; 607 608 spi1_ss0_a_pins: spi1_ss0_a { 609 mux { 610 groups = "spi1_ss0_a"; 611 function = "spi1"; 612 }; 613 }; 614 615 spi1_ss1_pins: spi1_ss1 { 616 mux { 617 groups = "spi1_ss1"; 618 function = "spi1"; 619 }; 620 }; 621 622 spi1_x_pins: spi1_x { 623 mux { 624 groups = "spi1_miso_x", 625 "spi1_mosi_x", 626 "spi1_clk_x"; 627 function = "spi1"; 628 }; 629 }; 630 631 spi1_ss0_x_pins: spi1_ss0_x { 632 mux { 633 groups = "spi1_ss0_x"; 634 function = "spi1"; 635 }; 636 }; 637 638 i2c0_pins: i2c0 { 639 mux { 640 groups = "i2c0_sck", 641 "i2c0_sda"; 642 function = "i2c0"; 643 }; 644 }; 645 646 i2c1_z_pins: i2c1_z { 647 mux { 648 groups = "i2c1_sck_z", 649 "i2c1_sda_z"; 650 function = "i2c1"; 651 }; 652 }; 653 654 i2c1_x_pins: i2c1_x { 655 mux { 656 groups = "i2c1_sck_x", 657 "i2c1_sda_x"; 658 function = "i2c1"; 659 }; 660 }; 661 662 i2c2_x_pins: i2c2_x { 663 mux { 664 groups = "i2c2_sck_x", 665 "i2c2_sda_x"; 666 function = "i2c2"; 667 }; 668 }; 669 670 i2c2_a_pins: i2c2_a { 671 mux { 672 groups = "i2c2_sck_a", 673 "i2c2_sda_a"; 674 function = "i2c2"; 675 }; 676 }; 677 678 i2c3_a6_pins: i2c3_a6 { 679 mux { 680 groups = "i2c3_sda_a6", 681 "i2c3_sck_a7"; 682 function = "i2c3"; 683 }; 684 }; 685 686 i2c3_a12_pins: i2c3_a12 { 687 mux { 688 groups = "i2c3_sda_a12", 689 "i2c3_sck_a13"; 690 function = "i2c3"; 691 }; 692 }; 693 694 i2c3_a19_pins: i2c3_a19 { 695 mux { 696 groups = "i2c3_sda_a19", 697 "i2c3_sck_a20"; 698 function = "i2c3"; 699 }; 700 }; 701 702 uart_a_pins: uart_a { 703 mux { 704 groups = "uart_tx_a", 705 "uart_rx_a"; 706 function = "uart_a"; 707 }; 708 }; 709 710 uart_a_cts_rts_pins: uart_a_cts_rts { 711 mux { 712 groups = "uart_cts_a", 713 "uart_rts_a"; 714 function = "uart_a"; 715 }; 716 }; 717 718 uart_b_x_pins: uart_b_x { 719 mux { 720 groups = "uart_tx_b_x", 721 "uart_rx_b_x"; 722 function = "uart_b"; 723 }; 724 }; 725 726 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 727 mux { 728 groups = "uart_cts_b_x", 729 "uart_rts_b_x"; 730 function = "uart_b"; 731 }; 732 }; 733 734 uart_b_z_pins: uart_b_z { 735 mux { 736 groups = "uart_tx_b_z", 737 "uart_rx_b_z"; 738 function = "uart_b"; 739 }; 740 }; 741 742 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 743 mux { 744 groups = "uart_cts_b_z", 745 "uart_rts_b_z"; 746 function = "uart_b"; 747 }; 748 }; 749 750 uart_ao_b_z_pins: uart_ao_b_z { 751 mux { 752 groups = "uart_ao_tx_b_z", 753 "uart_ao_rx_b_z"; 754 function = "uart_ao_b_z"; 755 }; 756 }; 757 758 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 759 mux { 760 groups = "uart_ao_cts_b_z", 761 "uart_ao_rts_b_z"; 762 function = "uart_ao_b_z"; 763 }; 764 }; 765 766 mclk_b_pins: mclk_b { 767 mux { 768 groups = "mclk_b"; 769 function = "mclk_b"; 770 }; 771 }; 772 773 mclk_c_pins: mclk_c { 774 mux { 775 groups = "mclk_c"; 776 function = "mclk_c"; 777 }; 778 }; 779 780 tdma_sclk_pins: tdma_sclk { 781 mux { 782 groups = "tdma_sclk"; 783 function = "tdma"; 784 }; 785 }; 786 787 tdma_sclk_slv_pins: tdma_sclk_slv { 788 mux { 789 groups = "tdma_sclk_slv"; 790 function = "tdma"; 791 }; 792 }; 793 794 tdma_fs_pins: tdma_fs { 795 mux { 796 groups = "tdma_fs"; 797 function = "tdma"; 798 }; 799 }; 800 801 tdma_fs_slv_pins: tdma_fs_slv { 802 mux { 803 groups = "tdma_fs_slv"; 804 function = "tdma"; 805 }; 806 }; 807 808 tdma_din0_pins: tdma_din0 { 809 mux { 810 groups = "tdma_din0"; 811 function = "tdma"; 812 }; 813 }; 814 815 tdma_dout0_x14_pins: tdma_dout0_x14 { 816 mux { 817 groups = "tdma_dout0_x14"; 818 function = "tdma"; 819 }; 820 }; 821 822 tdma_dout0_x15_pins: tdma_dout0_x15 { 823 mux { 824 groups = "tdma_dout0_x15"; 825 function = "tdma"; 826 }; 827 }; 828 829 tdma_dout1_pins: tdma_dout1 { 830 mux { 831 groups = "tdma_dout1"; 832 function = "tdma"; 833 }; 834 }; 835 836 tdma_din1_pins: tdma_din1 { 837 mux { 838 groups = "tdma_din1"; 839 function = "tdma"; 840 }; 841 }; 842 843 tdmb_sclk_pins: tdmb_sclk { 844 mux { 845 groups = "tdmb_sclk"; 846 function = "tdmb"; 847 }; 848 }; 849 850 tdmb_sclk_slv_pins: tdmb_sclk_slv { 851 mux { 852 groups = "tdmb_sclk_slv"; 853 function = "tdmb"; 854 }; 855 }; 856 857 tdmb_fs_pins: tdmb_fs { 858 mux { 859 groups = "tdmb_fs"; 860 function = "tdmb"; 861 }; 862 }; 863 864 tdmb_fs_slv_pins: tdmb_fs_slv { 865 mux { 866 groups = "tdmb_fs_slv"; 867 function = "tdmb"; 868 }; 869 }; 870 871 tdmb_din0_pins: tdmb_din0 { 872 mux { 873 groups = "tdmb_din0"; 874 function = "tdmb"; 875 }; 876 }; 877 878 tdmb_dout0_pins: tdmb_dout0 { 879 mux { 880 groups = "tdmb_dout0"; 881 function = "tdmb"; 882 }; 883 }; 884 885 tdmb_din1_pins: tdmb_din1 { 886 mux { 887 groups = "tdmb_din1"; 888 function = "tdmb"; 889 }; 890 }; 891 892 tdmb_dout1_pins: tdmb_dout1 { 893 mux { 894 groups = "tdmb_dout1"; 895 function = "tdmb"; 896 }; 897 }; 898 899 tdmb_din2_pins: tdmb_din2 { 900 mux { 901 groups = "tdmb_din2"; 902 function = "tdmb"; 903 }; 904 }; 905 906 tdmb_dout2_pins: tdmb_dout2 { 907 mux { 908 groups = "tdmb_dout2"; 909 function = "tdmb"; 910 }; 911 }; 912 913 tdmb_din3_pins: tdmb_din3 { 914 mux { 915 groups = "tdmb_din3"; 916 function = "tdmb"; 917 }; 918 }; 919 920 tdmb_dout3_pins: tdmb_dout3 { 921 mux { 922 groups = "tdmb_dout3"; 923 function = "tdmb"; 924 }; 925 }; 926 927 tdmc_sclk_pins: tdmc_sclk { 928 mux { 929 groups = "tdmc_sclk"; 930 function = "tdmc"; 931 }; 932 }; 933 934 tdmc_sclk_slv_pins: tdmc_sclk_slv { 935 mux { 936 groups = "tdmc_sclk_slv"; 937 function = "tdmc"; 938 }; 939 }; 940 941 tdmc_fs_pins: tdmc_fs { 942 mux { 943 groups = "tdmc_fs"; 944 function = "tdmc"; 945 }; 946 }; 947 948 tdmc_fs_slv_pins: tdmc_fs_slv { 949 mux { 950 groups = "tdmc_fs_slv"; 951 function = "tdmc"; 952 }; 953 }; 954 955 tdmc_din0_pins: tdmc_din0 { 956 mux { 957 groups = "tdmc_din0"; 958 function = "tdmc"; 959 }; 960 }; 961 962 tdmc_dout0_pins: tdmc_dout0 { 963 mux { 964 groups = "tdmc_dout0"; 965 function = "tdmc"; 966 }; 967 }; 968 969 tdmc_din1_pins: tdmc_din1 { 970 mux { 971 groups = "tdmc_din1"; 972 function = "tdmc"; 973 }; 974 }; 975 976 tdmc_dout1_pins: tdmc_dout1 { 977 mux { 978 groups = "tdmc_dout1"; 979 function = "tdmc"; 980 }; 981 }; 982 983 tdmc_din2_pins: tdmc_din2 { 984 mux { 985 groups = "tdmc_din2"; 986 function = "tdmc"; 987 }; 988 }; 989 990 tdmc_dout2_pins: tdmc_dout2 { 991 mux { 992 groups = "tdmc_dout2"; 993 function = "tdmc"; 994 }; 995 }; 996 997 tdmc_din3_pins: tdmc_din3 { 998 mux { 999 groups = "tdmc_din3"; 1000 function = "tdmc"; 1001 }; 1002 }; 1003 1004 tdmc_dout3_pins: tdmc_dout3 { 1005 mux { 1006 groups = "tdmc_dout3"; 1007 function = "tdmc"; 1008 }; 1009 }; 1010 }; 1011 }; 1012 1013 sram: sram@fffc0000 { 1014 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1015 reg = <0x0 0xfffc0000 0x0 0x20000>; 1016 #address-cells = <1>; 1017 #size-cells = <1>; 1018 ranges = <0 0x0 0xfffc0000 0x20000>; 1019 1020 cpu_scp_lpri: scp-shmem@0 { 1021 compatible = "amlogic,meson-axg-scp-shmem"; 1022 reg = <0x13000 0x400>; 1023 }; 1024 1025 cpu_scp_hpri: scp-shmem@200 { 1026 compatible = "amlogic,meson-axg-scp-shmem"; 1027 reg = <0x13400 0x400>; 1028 }; 1029 }; 1030 1031 aobus: bus@ff800000 { 1032 compatible = "simple-bus"; 1033 reg = <0x0 0xff800000 0x0 0x100000>; 1034 #address-cells = <2>; 1035 #size-cells = <2>; 1036 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1037 1038 pinctrl_aobus: pinctrl@14 { 1039 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1040 #address-cells = <2>; 1041 #size-cells = <2>; 1042 ranges; 1043 1044 gpio_ao: bank@14 { 1045 reg = <0x0 0x00014 0x0 0x8>, 1046 <0x0 0x0002c 0x0 0x4>, 1047 <0x0 0x00024 0x0 0x8>; 1048 reg-names = "mux", "pull", "gpio"; 1049 gpio-controller; 1050 #gpio-cells = <2>; 1051 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1052 }; 1053 1054 remote_input_ao_pins: remote_input_ao { 1055 mux { 1056 groups = "remote_input_ao"; 1057 function = "remote_input_ao"; 1058 }; 1059 }; 1060 1061 uart_ao_a_pins: uart_ao_a { 1062 mux { 1063 groups = "uart_ao_tx_a", 1064 "uart_ao_rx_a"; 1065 function = "uart_ao_a"; 1066 }; 1067 }; 1068 1069 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1070 mux { 1071 groups = "uart_ao_cts_a", 1072 "uart_ao_rts_a"; 1073 function = "uart_ao_a"; 1074 }; 1075 }; 1076 1077 uart_ao_b_pins: uart_ao_b { 1078 mux { 1079 groups = "uart_ao_tx_b", 1080 "uart_ao_rx_b"; 1081 function = "uart_ao_b"; 1082 }; 1083 }; 1084 1085 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1086 mux { 1087 groups = "uart_ao_cts_b", 1088 "uart_ao_rts_b"; 1089 function = "uart_ao_b"; 1090 }; 1091 }; 1092 }; 1093 1094 sec_AO: ao-secure@140 { 1095 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1096 reg = <0x0 0x140 0x0 0x140>; 1097 amlogic,has-chip-id; 1098 }; 1099 1100 pwm_AO_ab: pwm@7000 { 1101 compatible = "amlogic,meson-axg-ao-pwm"; 1102 reg = <0x0 0x07000 0x0 0x20>; 1103 #pwm-cells = <3>; 1104 status = "disabled"; 1105 }; 1106 1107 pwm_AO_cd: pwm@2000 { 1108 compatible = "amlogic,meson-axg-ao-pwm"; 1109 reg = <0x0 0x02000 0x0 0x20>; 1110 #pwm-cells = <3>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c_AO: i2c@5000 { 1115 compatible = "amlogic,meson-axg-i2c"; 1116 status = "disabled"; 1117 reg = <0x0 0x05000 0x0 0x20>; 1118 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 clocks = <&clkc CLKID_I2C>; 1122 clock-names = "clk_i2c"; 1123 }; 1124 1125 uart_AO: serial@3000 { 1126 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1127 reg = <0x0 0x3000 0x0 0x18>; 1128 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1129 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 1130 clock-names = "xtal", "pclk", "baud"; 1131 status = "disabled"; 1132 }; 1133 1134 uart_AO_B: serial@4000 { 1135 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1136 reg = <0x0 0x4000 0x0 0x18>; 1137 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1138 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 1139 clock-names = "xtal", "pclk", "baud"; 1140 status = "disabled"; 1141 }; 1142 1143 ir: ir@8000 { 1144 compatible = "amlogic,meson-gxbb-ir"; 1145 reg = <0x0 0x8000 0x0 0x20>; 1146 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1147 status = "disabled"; 1148 }; 1149 }; 1150 }; 1151}; 1152