1/* 2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "amlogic,meson-axg"; 13 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 /* 16 MiB reserved for Hardware ROM Firmware */ 24 hwrom_reserved: hwrom@0 { 25 reg = <0x0 0x0 0x0 0x1000000>; 26 no-map; 27 }; 28 29 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 30 secmon_reserved: secmon@5000000 { 31 reg = <0x0 0x05000000 0x0 0x300000>; 32 no-map; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <0x2>; 38 #size-cells = <0x0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53", "arm,armv8"; 51 reg = <0x0 0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&l2>; 54 }; 55 56 cpu2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 reg = <0x0 0x2>; 60 enable-method = "psci"; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 reg = <0x0 0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2>; 70 }; 71 72 l2: l2-cache0 { 73 compatible = "cache"; 74 }; 75 }; 76 77 arm-pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 101 }; 102 103 xtal: xtal-clk { 104 compatible = "fixed-clock"; 105 clock-frequency = <24000000>; 106 clock-output-names = "xtal"; 107 #clock-cells = <0>; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 cbus: bus@ffd00000 { 117 compatible = "simple-bus"; 118 reg = <0x0 0xffd00000 0x0 0x25000>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 122 123 pwm_ab: pwm@1b000 { 124 compatible = "amlogic,meson-axg-ee-pwm"; 125 reg = <0x0 0x1b000 0x0 0x20>; 126 #pwm-cells = <3>; 127 status = "disabled"; 128 }; 129 130 pwm_cd: pwm@1a000 { 131 compatible = "amlogic,meson-axg-ee-pwm"; 132 reg = <0x0 0x1a000 0x0 0x20>; 133 #pwm-cells = <3>; 134 status = "disabled"; 135 }; 136 137 uart_A: serial@24000 { 138 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 139 reg = <0x0 0x24000 0x0 0x14>; 140 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 141 status = "disabled"; 142 }; 143 144 uart_B: serial@23000 { 145 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 146 reg = <0x0 0x23000 0x0 0x14>; 147 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 148 status = "disabled"; 149 }; 150 }; 151 152 gic: interrupt-controller@ffc01000 { 153 compatible = "arm,gic-400"; 154 reg = <0x0 0xffc01000 0 0x1000>, 155 <0x0 0xffc02000 0 0x2000>, 156 <0x0 0xffc04000 0 0x2000>, 157 <0x0 0xffc06000 0 0x2000>; 158 interrupt-controller; 159 interrupts = <GIC_PPI 9 160 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 161 #interrupt-cells = <3>; 162 #address-cells = <0>; 163 }; 164 165 hiubus: bus@ff63c000 { 166 compatible = "simple-bus"; 167 reg = <0x0 0xff63c000 0x0 0x1c00>; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 171 172 clkc: clock-controller@0 { 173 compatible = "amlogic,axg-clkc"; 174 #clock-cells = <1>; 175 reg = <0x0 0x0 0x0 0x320>; 176 }; 177 }; 178 179 mailbox: mailbox@ff63dc00 { 180 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 181 reg = <0 0xff63dc00 0 0x400>; 182 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 183 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 185 #mbox-cells = <1>; 186 }; 187 188 periphs: periphs@ff634000 { 189 compatible = "simple-bus"; 190 reg = <0x0 0xff634000 0x0 0x2000>; 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 194 195 pinctrl_periphs: pinctrl@480 { 196 compatible = "amlogic,meson-axg-periphs-pinctrl"; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 gpio: bank@480 { 202 reg = <0x0 0x00480 0x0 0x40>, 203 <0x0 0x004e8 0x0 0x14>, 204 <0x0 0x00520 0x0 0x14>, 205 <0x0 0x00430 0x0 0x3c>; 206 reg-names = "mux", "pull", "pull-enable", "gpio"; 207 gpio-controller; 208 #gpio-cells = <2>; 209 gpio-ranges = <&pinctrl_periphs 0 0 86>; 210 }; 211 212 pwm_a_a_pins: pwm_a_a { 213 mux { 214 groups = "pwm_a_a"; 215 function = "pwm_a"; 216 }; 217 }; 218 219 pwm_a_x18_pins: pwm_a_x18 { 220 mux { 221 groups = "pwm_a_x18"; 222 function = "pwm_a"; 223 }; 224 }; 225 226 pwm_a_x20_pins: pwm_a_x20 { 227 mux { 228 groups = "pwm_a_x20"; 229 function = "pwm_a"; 230 }; 231 }; 232 233 pwm_a_z_pins: pwm_a_z { 234 mux { 235 groups = "pwm_a_z"; 236 function = "pwm_a"; 237 }; 238 }; 239 240 pwm_b_a_pins: pwm_b_a { 241 mux { 242 groups = "pwm_b_a"; 243 function = "pwm_b"; 244 }; 245 }; 246 247 pwm_b_x_pins: pwm_b_x { 248 mux { 249 groups = "pwm_b_x"; 250 function = "pwm_b"; 251 }; 252 }; 253 254 pwm_b_z_pins: pwm_b_z { 255 mux { 256 groups = "pwm_b_z"; 257 function = "pwm_b"; 258 }; 259 }; 260 261 pwm_c_a_pins: pwm_c_a { 262 mux { 263 groups = "pwm_c_a"; 264 function = "pwm_c"; 265 }; 266 }; 267 268 pwm_c_x10_pins: pwm_c_x10 { 269 mux { 270 groups = "pwm_c_x10"; 271 function = "pwm_c"; 272 }; 273 }; 274 275 pwm_c_x17_pins: pwm_c_x17 { 276 mux { 277 groups = "pwm_c_x17"; 278 function = "pwm_c"; 279 }; 280 }; 281 282 pwm_d_x11_pins: pwm_d_x11 { 283 mux { 284 groups = "pwm_d_x11"; 285 function = "pwm_d"; 286 }; 287 }; 288 289 pwm_d_x16_pins: pwm_d_x16 { 290 mux { 291 groups = "pwm_d_x16"; 292 function = "pwm_d"; 293 }; 294 }; 295 }; 296 }; 297 298 sram: sram@fffc0000 { 299 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 300 reg = <0x0 0xfffc0000 0x0 0x20000>; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0 0x0 0xfffc0000 0x20000>; 304 305 cpu_scp_lpri: scp-shmem@0 { 306 compatible = "amlogic,meson-axg-scp-shmem"; 307 reg = <0x13000 0x400>; 308 }; 309 310 cpu_scp_hpri: scp-shmem@200 { 311 compatible = "amlogic,meson-axg-scp-shmem"; 312 reg = <0x13400 0x400>; 313 }; 314 }; 315 316 aobus: bus@ff800000 { 317 compatible = "simple-bus"; 318 reg = <0x0 0xff800000 0x0 0x100000>; 319 #address-cells = <2>; 320 #size-cells = <2>; 321 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 322 323 pinctrl_aobus: pinctrl@14 { 324 compatible = "amlogic,meson-axg-aobus-pinctrl"; 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges; 328 329 gpio_ao: bank@14 { 330 reg = <0x0 0x00014 0x0 0x8>, 331 <0x0 0x0002c 0x0 0x4>, 332 <0x0 0x00024 0x0 0x8>; 333 reg-names = "mux", "pull", "gpio"; 334 gpio-controller; 335 #gpio-cells = <2>; 336 gpio-ranges = <&pinctrl_aobus 0 0 15>; 337 }; 338 }; 339 340 pwm_AO_ab: pwm@7000 { 341 compatible = "amlogic,meson-axg-ao-pwm"; 342 reg = <0x0 0x07000 0x0 0x20>; 343 #pwm-cells = <3>; 344 status = "disabled"; 345 }; 346 347 pwm_AO_cd: pwm@2000 { 348 compatible = "amlogic,axg-ao-pwm"; 349 reg = <0x0 0x02000 0x0 0x20>; 350 #pwm-cells = <3>; 351 status = "disabled"; 352 }; 353 354 uart_AO: serial@3000 { 355 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 356 reg = <0x0 0x3000 0x0 0x18>; 357 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 358 clocks = <&xtal>, <&xtal>, <&xtal>; 359 clock-names = "xtal", "pclk", "baud"; 360 status = "disabled"; 361 }; 362 363 uart_AO_B: serial@4000 { 364 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 365 reg = <0x0 0x4000 0x0 0x18>; 366 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 367 clocks = <&xtal>, <&xtal>, <&xtal>; 368 clock-names = "xtal", "pclk", "baud"; 369 status = "disabled"; 370 }; 371 }; 372 }; 373}; 374