1/* 2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "amlogic,meson-axg"; 13 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 /* 16 MiB reserved for Hardware ROM Firmware */ 24 hwrom_reserved: hwrom@0 { 25 reg = <0x0 0x0 0x0 0x1000000>; 26 no-map; 27 }; 28 29 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 30 secmon_reserved: secmon@5000000 { 31 reg = <0x0 0x05000000 0x0 0x300000>; 32 no-map; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <0x2>; 38 #size-cells = <0x0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53", "arm,armv8"; 51 reg = <0x0 0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&l2>; 54 }; 55 56 cpu2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 reg = <0x0 0x2>; 60 enable-method = "psci"; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 reg = <0x0 0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2>; 70 }; 71 72 l2: l2-cache0 { 73 compatible = "cache"; 74 }; 75 }; 76 77 arm-pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 101 }; 102 103 xtal: xtal-clk { 104 compatible = "fixed-clock"; 105 clock-frequency = <24000000>; 106 clock-output-names = "xtal"; 107 #clock-cells = <0>; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 cbus: bus@ffd00000 { 117 compatible = "simple-bus"; 118 reg = <0x0 0xffd00000 0x0 0x25000>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 122 123 pwm_ab: pwm@1b000 { 124 compatible = "amlogic,meson-axg-ee-pwm"; 125 reg = <0x0 0x1b000 0x0 0x20>; 126 #pwm-cells = <3>; 127 status = "disabled"; 128 }; 129 130 pwm_cd: pwm@1a000 { 131 compatible = "amlogic,meson-axg-ee-pwm"; 132 reg = <0x0 0x1a000 0x0 0x20>; 133 #pwm-cells = <3>; 134 status = "disabled"; 135 }; 136 137 reset: reset-controller@1004 { 138 compatible = "amlogic,meson-axg-reset"; 139 reg = <0x0 0x01004 0x0 0x9c>; 140 #reset-cells = <1>; 141 }; 142 143 uart_A: serial@24000 { 144 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 145 reg = <0x0 0x24000 0x0 0x14>; 146 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 147 status = "disabled"; 148 }; 149 150 uart_B: serial@23000 { 151 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 152 reg = <0x0 0x23000 0x0 0x14>; 153 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 154 status = "disabled"; 155 }; 156 }; 157 158 gic: interrupt-controller@ffc01000 { 159 compatible = "arm,gic-400"; 160 reg = <0x0 0xffc01000 0 0x1000>, 161 <0x0 0xffc02000 0 0x2000>, 162 <0x0 0xffc04000 0 0x2000>, 163 <0x0 0xffc06000 0 0x2000>; 164 interrupt-controller; 165 interrupts = <GIC_PPI 9 166 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 167 #interrupt-cells = <3>; 168 #address-cells = <0>; 169 }; 170 171 hiubus: bus@ff63c000 { 172 compatible = "simple-bus"; 173 reg = <0x0 0xff63c000 0x0 0x1c00>; 174 #address-cells = <2>; 175 #size-cells = <2>; 176 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 177 178 clkc: clock-controller@0 { 179 compatible = "amlogic,axg-clkc"; 180 #clock-cells = <1>; 181 reg = <0x0 0x0 0x0 0x320>; 182 }; 183 }; 184 185 mailbox: mailbox@ff63dc00 { 186 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 187 reg = <0 0xff63dc00 0 0x400>; 188 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 189 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 190 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 191 #mbox-cells = <1>; 192 }; 193 194 periphs: periphs@ff634000 { 195 compatible = "simple-bus"; 196 reg = <0x0 0xff634000 0x0 0x2000>; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 200 201 pinctrl_periphs: pinctrl@480 { 202 compatible = "amlogic,meson-axg-periphs-pinctrl"; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges; 206 207 gpio: bank@480 { 208 reg = <0x0 0x00480 0x0 0x40>, 209 <0x0 0x004e8 0x0 0x14>, 210 <0x0 0x00520 0x0 0x14>, 211 <0x0 0x00430 0x0 0x3c>; 212 reg-names = "mux", "pull", "pull-enable", "gpio"; 213 gpio-controller; 214 #gpio-cells = <2>; 215 gpio-ranges = <&pinctrl_periphs 0 0 86>; 216 }; 217 218 pwm_a_a_pins: pwm_a_a { 219 mux { 220 groups = "pwm_a_a"; 221 function = "pwm_a"; 222 }; 223 }; 224 225 pwm_a_x18_pins: pwm_a_x18 { 226 mux { 227 groups = "pwm_a_x18"; 228 function = "pwm_a"; 229 }; 230 }; 231 232 pwm_a_x20_pins: pwm_a_x20 { 233 mux { 234 groups = "pwm_a_x20"; 235 function = "pwm_a"; 236 }; 237 }; 238 239 pwm_a_z_pins: pwm_a_z { 240 mux { 241 groups = "pwm_a_z"; 242 function = "pwm_a"; 243 }; 244 }; 245 246 pwm_b_a_pins: pwm_b_a { 247 mux { 248 groups = "pwm_b_a"; 249 function = "pwm_b"; 250 }; 251 }; 252 253 pwm_b_x_pins: pwm_b_x { 254 mux { 255 groups = "pwm_b_x"; 256 function = "pwm_b"; 257 }; 258 }; 259 260 pwm_b_z_pins: pwm_b_z { 261 mux { 262 groups = "pwm_b_z"; 263 function = "pwm_b"; 264 }; 265 }; 266 267 pwm_c_a_pins: pwm_c_a { 268 mux { 269 groups = "pwm_c_a"; 270 function = "pwm_c"; 271 }; 272 }; 273 274 pwm_c_x10_pins: pwm_c_x10 { 275 mux { 276 groups = "pwm_c_x10"; 277 function = "pwm_c"; 278 }; 279 }; 280 281 pwm_c_x17_pins: pwm_c_x17 { 282 mux { 283 groups = "pwm_c_x17"; 284 function = "pwm_c"; 285 }; 286 }; 287 288 pwm_d_x11_pins: pwm_d_x11 { 289 mux { 290 groups = "pwm_d_x11"; 291 function = "pwm_d"; 292 }; 293 }; 294 295 pwm_d_x16_pins: pwm_d_x16 { 296 mux { 297 groups = "pwm_d_x16"; 298 function = "pwm_d"; 299 }; 300 }; 301 }; 302 }; 303 304 sram: sram@fffc0000 { 305 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 306 reg = <0x0 0xfffc0000 0x0 0x20000>; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 ranges = <0 0x0 0xfffc0000 0x20000>; 310 311 cpu_scp_lpri: scp-shmem@0 { 312 compatible = "amlogic,meson-axg-scp-shmem"; 313 reg = <0x13000 0x400>; 314 }; 315 316 cpu_scp_hpri: scp-shmem@200 { 317 compatible = "amlogic,meson-axg-scp-shmem"; 318 reg = <0x13400 0x400>; 319 }; 320 }; 321 322 aobus: bus@ff800000 { 323 compatible = "simple-bus"; 324 reg = <0x0 0xff800000 0x0 0x100000>; 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 328 329 pinctrl_aobus: pinctrl@14 { 330 compatible = "amlogic,meson-axg-aobus-pinctrl"; 331 #address-cells = <2>; 332 #size-cells = <2>; 333 ranges; 334 335 gpio_ao: bank@14 { 336 reg = <0x0 0x00014 0x0 0x8>, 337 <0x0 0x0002c 0x0 0x4>, 338 <0x0 0x00024 0x0 0x8>; 339 reg-names = "mux", "pull", "gpio"; 340 gpio-controller; 341 #gpio-cells = <2>; 342 gpio-ranges = <&pinctrl_aobus 0 0 15>; 343 }; 344 }; 345 346 pwm_AO_ab: pwm@7000 { 347 compatible = "amlogic,meson-axg-ao-pwm"; 348 reg = <0x0 0x07000 0x0 0x20>; 349 #pwm-cells = <3>; 350 status = "disabled"; 351 }; 352 353 pwm_AO_cd: pwm@2000 { 354 compatible = "amlogic,axg-ao-pwm"; 355 reg = <0x0 0x02000 0x0 0x20>; 356 #pwm-cells = <3>; 357 status = "disabled"; 358 }; 359 360 uart_AO: serial@3000 { 361 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 362 reg = <0x0 0x3000 0x0 0x18>; 363 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 364 clocks = <&xtal>, <&xtal>, <&xtal>; 365 clock-names = "xtal", "pclk", "baud"; 366 status = "disabled"; 367 }; 368 369 uart_AO_B: serial@4000 { 370 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 371 reg = <0x0 0x4000 0x0 0x18>; 372 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 373 clocks = <&xtal>, <&xtal>, <&xtal>; 374 clock-names = "xtal", "pclk", "baud"; 375 status = "disabled"; 376 }; 377 }; 378 }; 379}; 380