1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15#include <dt-bindings/power/meson-axg-power.h>
16
17/ {
18	compatible = "amlogic,meson-axg";
19
20	interrupt-parent = <&gic>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	tdmif_a: audio-controller-0 {
25		compatible = "amlogic,axg-tdm-iface";
26		#sound-dai-cells = <0>;
27		sound-name-prefix = "TDM_A";
28		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31		clock-names = "mclk", "sclk", "lrclk";
32		status = "disabled";
33	};
34
35	tdmif_b: audio-controller-1 {
36		compatible = "amlogic,axg-tdm-iface";
37		#sound-dai-cells = <0>;
38		sound-name-prefix = "TDM_B";
39		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42		clock-names = "mclk", "sclk", "lrclk";
43		status = "disabled";
44	};
45
46	tdmif_c: audio-controller-2 {
47		compatible = "amlogic,axg-tdm-iface";
48		#sound-dai-cells = <0>;
49		sound-name-prefix = "TDM_C";
50		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53		clock-names = "mclk", "sclk", "lrclk";
54		status = "disabled";
55	};
56
57	arm-pmu {
58		compatible = "arm,cortex-a53-pmu";
59		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64	};
65
66	cpus {
67		#address-cells = <0x2>;
68		#size-cells = <0x0>;
69
70		cpu0: cpu@0 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a53";
73			reg = <0x0 0x0>;
74			enable-method = "psci";
75			next-level-cache = <&l2>;
76			clocks = <&scpi_dvfs 0>;
77		};
78
79		cpu1: cpu@1 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a53";
82			reg = <0x0 0x1>;
83			enable-method = "psci";
84			next-level-cache = <&l2>;
85			clocks = <&scpi_dvfs 0>;
86		};
87
88		cpu2: cpu@2 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53";
91			reg = <0x0 0x2>;
92			enable-method = "psci";
93			next-level-cache = <&l2>;
94			clocks = <&scpi_dvfs 0>;
95		};
96
97		cpu3: cpu@3 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a53";
100			reg = <0x0 0x3>;
101			enable-method = "psci";
102			next-level-cache = <&l2>;
103			clocks = <&scpi_dvfs 0>;
104		};
105
106		l2: l2-cache0 {
107			compatible = "cache";
108		};
109	};
110
111	sm: secure-monitor {
112		compatible = "amlogic,meson-gxbb-sm";
113	};
114
115	efuse: efuse {
116		compatible = "amlogic,meson-gxbb-efuse";
117		clocks = <&clkc CLKID_EFUSE>;
118		#address-cells = <1>;
119		#size-cells = <1>;
120		read-only;
121		secure-monitor = <&sm>;
122	};
123
124	psci {
125		compatible = "arm,psci-1.0";
126		method = "smc";
127	};
128
129	reserved-memory {
130		#address-cells = <2>;
131		#size-cells = <2>;
132		ranges;
133
134		/* 16 MiB reserved for Hardware ROM Firmware */
135		hwrom_reserved: hwrom@0 {
136			reg = <0x0 0x0 0x0 0x1000000>;
137			no-map;
138		};
139
140		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
141		secmon_reserved: secmon@5000000 {
142			reg = <0x0 0x05000000 0x0 0x300000>;
143			no-map;
144		};
145	};
146
147	scpi {
148		compatible = "arm,scpi-pre-1.0";
149		mboxes = <&mailbox 1 &mailbox 2>;
150		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
151
152		scpi_clocks: clocks {
153			compatible = "arm,scpi-clocks";
154
155			scpi_dvfs: clock-controller {
156				compatible = "arm,scpi-dvfs-clocks";
157				#clock-cells = <1>;
158				clock-indices = <0>;
159				clock-output-names = "vcpu";
160			};
161		};
162
163		scpi_sensors: sensors {
164			compatible = "amlogic,meson-gxbb-scpi-sensors";
165			#thermal-sensor-cells = <1>;
166		};
167	};
168
169	soc {
170		compatible = "simple-bus";
171		#address-cells = <2>;
172		#size-cells = <2>;
173		ranges;
174
175		usb: usb@ffe09080 {
176			compatible = "amlogic,meson-axg-usb-ctrl";
177			reg = <0x0 0xffe09080 0x0 0x20>;
178			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
179			#address-cells = <2>;
180			#size-cells = <2>;
181			ranges;
182
183			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
184			clock-names = "usb_ctrl", "ddr";
185			resets = <&reset RESET_USB_OTG>;
186
187			dr_mode = "otg";
188
189			phys = <&usb2_phy1>;
190			phy-names = "usb2-phy1";
191
192			dwc2: usb@ff400000 {
193				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
194				reg = <0x0 0xff400000 0x0 0x40000>;
195				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
196				clocks = <&clkc CLKID_USB1>;
197				clock-names = "otg";
198				phys = <&usb2_phy1>;
199				dr_mode = "peripheral";
200				g-rx-fifo-size = <192>;
201				g-np-tx-fifo-size = <128>;
202				g-tx-fifo-size = <128 128 16 16 16>;
203			};
204
205			dwc3: usb@ff500000 {
206				compatible = "snps,dwc3";
207				reg = <0x0 0xff500000 0x0 0x100000>;
208				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
209				dr_mode = "host";
210				maximum-speed = "high-speed";
211				snps,dis_u2_susphy_quirk;
212			};
213		};
214
215		ethmac: ethernet@ff3f0000 {
216			compatible = "amlogic,meson-axg-dwmac",
217				     "snps,dwmac-3.70a",
218				     "snps,dwmac";
219			reg = <0x0 0xff3f0000 0x0 0x10000>,
220			      <0x0 0xff634540 0x0 0x8>;
221			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
222			interrupt-names = "macirq";
223			clocks = <&clkc CLKID_ETH>,
224				 <&clkc CLKID_FCLK_DIV2>,
225				 <&clkc CLKID_MPLL2>,
226				 <&clkc CLKID_FCLK_DIV2>;
227			clock-names = "stmmaceth", "clkin0", "clkin1",
228				      "timing-adjustment";
229			rx-fifo-depth = <4096>;
230			tx-fifo-depth = <2048>;
231			resets = <&reset RESET_ETHERNET>;
232			reset-names = "stmmaceth";
233			power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
234			status = "disabled";
235		};
236
237		pdm: audio-controller@ff632000 {
238			compatible = "amlogic,axg-pdm";
239			reg = <0x0 0xff632000 0x0 0x34>;
240			#sound-dai-cells = <0>;
241			sound-name-prefix = "PDM";
242			clocks = <&clkc_audio AUD_CLKID_PDM>,
243				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
244				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
245			clock-names = "pclk", "dclk", "sysclk";
246			status = "disabled";
247		};
248
249		periphs: bus@ff634000 {
250			compatible = "simple-bus";
251			reg = <0x0 0xff634000 0x0 0x2000>;
252			#address-cells = <2>;
253			#size-cells = <2>;
254			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
255
256			hwrng: rng@18 {
257				compatible = "amlogic,meson-rng";
258				reg = <0x0 0x18 0x0 0x4>;
259				clocks = <&clkc CLKID_RNG0>;
260				clock-names = "core";
261			};
262
263			pinctrl_periphs: pinctrl@480 {
264				compatible = "amlogic,meson-axg-periphs-pinctrl";
265				#address-cells = <2>;
266				#size-cells = <2>;
267				ranges;
268
269				gpio: bank@480 {
270					reg = <0x0 0x00480 0x0 0x40>,
271					      <0x0 0x004e8 0x0 0x14>,
272					      <0x0 0x00520 0x0 0x14>,
273					      <0x0 0x00430 0x0 0x3c>;
274					reg-names = "mux", "pull", "pull-enable", "gpio";
275					gpio-controller;
276					#gpio-cells = <2>;
277					gpio-ranges = <&pinctrl_periphs 0 0 86>;
278				};
279
280				i2c0_pins: i2c0 {
281					mux {
282						groups = "i2c0_sck",
283							 "i2c0_sda";
284						function = "i2c0";
285						bias-disable;
286					};
287				};
288
289				i2c1_x_pins: i2c1_x {
290					mux {
291						groups = "i2c1_sck_x",
292							 "i2c1_sda_x";
293						function = "i2c1";
294						bias-disable;
295					};
296				};
297
298				i2c1_z_pins: i2c1_z {
299					mux {
300						groups = "i2c1_sck_z",
301							 "i2c1_sda_z";
302						function = "i2c1";
303						bias-disable;
304					};
305				};
306
307				i2c2_a_pins: i2c2_a {
308					mux {
309						groups = "i2c2_sck_a",
310							 "i2c2_sda_a";
311						function = "i2c2";
312						bias-disable;
313					};
314				};
315
316				i2c2_x_pins: i2c2_x {
317					mux {
318						groups = "i2c2_sck_x",
319							 "i2c2_sda_x";
320						function = "i2c2";
321						bias-disable;
322					};
323				};
324
325				i2c3_a6_pins: i2c3_a6 {
326					mux {
327						groups = "i2c3_sda_a6",
328							 "i2c3_sck_a7";
329						function = "i2c3";
330						bias-disable;
331					};
332				};
333
334				i2c3_a12_pins: i2c3_a12 {
335					mux {
336						groups = "i2c3_sda_a12",
337							 "i2c3_sck_a13";
338						function = "i2c3";
339						bias-disable;
340					};
341				};
342
343				i2c3_a19_pins: i2c3_a19 {
344					mux {
345						groups = "i2c3_sda_a19",
346							 "i2c3_sck_a20";
347						function = "i2c3";
348						bias-disable;
349					};
350				};
351
352				emmc_pins: emmc {
353					mux-0 {
354						groups = "emmc_nand_d0",
355							 "emmc_nand_d1",
356							 "emmc_nand_d2",
357							 "emmc_nand_d3",
358							 "emmc_nand_d4",
359							 "emmc_nand_d5",
360							 "emmc_nand_d6",
361							 "emmc_nand_d7",
362							 "emmc_cmd";
363						function = "emmc";
364						bias-pull-up;
365					};
366
367					mux-1 {
368						groups = "emmc_clk";
369						function = "emmc";
370						bias-disable;
371					};
372				};
373
374				emmc_ds_pins: emmc_ds {
375					mux {
376						groups = "emmc_ds";
377						function = "emmc";
378						bias-pull-down;
379					};
380				};
381
382				emmc_clk_gate_pins: emmc_clk_gate {
383					mux {
384						groups = "BOOT_8";
385						function = "gpio_periphs";
386						bias-pull-down;
387					};
388				};
389
390				eth_rgmii_x_pins: eth-x-rgmii {
391					mux {
392						groups = "eth_mdio_x",
393							 "eth_mdc_x",
394							 "eth_rgmii_rx_clk_x",
395							 "eth_rx_dv_x",
396							 "eth_rxd0_x",
397							 "eth_rxd1_x",
398							 "eth_rxd2_rgmii",
399							 "eth_rxd3_rgmii",
400							 "eth_rgmii_tx_clk",
401							 "eth_txen_x",
402							 "eth_txd0_x",
403							 "eth_txd1_x",
404							 "eth_txd2_rgmii",
405							 "eth_txd3_rgmii";
406						function = "eth";
407						bias-disable;
408					};
409				};
410
411				eth_rgmii_y_pins: eth-y-rgmii {
412					mux {
413						groups = "eth_mdio_y",
414							 "eth_mdc_y",
415							 "eth_rgmii_rx_clk_y",
416							 "eth_rx_dv_y",
417							 "eth_rxd0_y",
418							 "eth_rxd1_y",
419							 "eth_rxd2_rgmii",
420							 "eth_rxd3_rgmii",
421							 "eth_rgmii_tx_clk",
422							 "eth_txen_y",
423							 "eth_txd0_y",
424							 "eth_txd1_y",
425							 "eth_txd2_rgmii",
426							 "eth_txd3_rgmii";
427						function = "eth";
428						bias-disable;
429					};
430				};
431
432				eth_rmii_x_pins: eth-x-rmii {
433					mux {
434						groups = "eth_mdio_x",
435							 "eth_mdc_x",
436							 "eth_rgmii_rx_clk_x",
437							 "eth_rx_dv_x",
438							 "eth_rxd0_x",
439							 "eth_rxd1_x",
440							 "eth_txen_x",
441							 "eth_txd0_x",
442							 "eth_txd1_x";
443						function = "eth";
444						bias-disable;
445					};
446				};
447
448				eth_rmii_y_pins: eth-y-rmii {
449					mux {
450						groups = "eth_mdio_y",
451							 "eth_mdc_y",
452							 "eth_rgmii_rx_clk_y",
453							 "eth_rx_dv_y",
454							 "eth_rxd0_y",
455							 "eth_rxd1_y",
456							 "eth_txen_y",
457							 "eth_txd0_y",
458							 "eth_txd1_y";
459						function = "eth";
460						bias-disable;
461					};
462				};
463
464				mclk_b_pins: mclk_b {
465					mux {
466						groups = "mclk_b";
467						function = "mclk_b";
468						bias-disable;
469					};
470				};
471
472				mclk_c_pins: mclk_c {
473					mux {
474						groups = "mclk_c";
475						function = "mclk_c";
476						bias-disable;
477					};
478				};
479
480				pdm_dclk_a14_pins: pdm_dclk_a14 {
481					mux {
482						groups = "pdm_dclk_a14";
483						function = "pdm";
484						bias-disable;
485					};
486				};
487
488				pdm_dclk_a19_pins: pdm_dclk_a19 {
489					mux {
490						groups = "pdm_dclk_a19";
491						function = "pdm";
492						bias-disable;
493					};
494				};
495
496				pdm_din0_pins: pdm_din0 {
497					mux {
498						groups = "pdm_din0";
499						function = "pdm";
500						bias-disable;
501					};
502				};
503
504				pdm_din1_pins: pdm_din1 {
505					mux {
506						groups = "pdm_din1";
507						function = "pdm";
508						bias-disable;
509					};
510				};
511
512				pdm_din2_pins: pdm_din2 {
513					mux {
514						groups = "pdm_din2";
515						function = "pdm";
516						bias-disable;
517					};
518				};
519
520				pdm_din3_pins: pdm_din3 {
521					mux {
522						groups = "pdm_din3";
523						function = "pdm";
524						bias-disable;
525					};
526				};
527
528				pwm_a_a_pins: pwm_a_a {
529					mux {
530						groups = "pwm_a_a";
531						function = "pwm_a";
532						bias-disable;
533					};
534				};
535
536				pwm_a_x18_pins: pwm_a_x18 {
537					mux {
538						groups = "pwm_a_x18";
539						function = "pwm_a";
540						bias-disable;
541					};
542				};
543
544				pwm_a_x20_pins: pwm_a_x20 {
545					mux {
546						groups = "pwm_a_x20";
547						function = "pwm_a";
548						bias-disable;
549					};
550				};
551
552				pwm_a_z_pins: pwm_a_z {
553					mux {
554						groups = "pwm_a_z";
555						function = "pwm_a";
556						bias-disable;
557					};
558				};
559
560				pwm_b_a_pins: pwm_b_a {
561					mux {
562						groups = "pwm_b_a";
563						function = "pwm_b";
564						bias-disable;
565					};
566				};
567
568				pwm_b_x_pins: pwm_b_x {
569					mux {
570						groups = "pwm_b_x";
571						function = "pwm_b";
572						bias-disable;
573					};
574				};
575
576				pwm_b_z_pins: pwm_b_z {
577					mux {
578						groups = "pwm_b_z";
579						function = "pwm_b";
580						bias-disable;
581					};
582				};
583
584				pwm_c_a_pins: pwm_c_a {
585					mux {
586						groups = "pwm_c_a";
587						function = "pwm_c";
588						bias-disable;
589					};
590				};
591
592				pwm_c_x10_pins: pwm_c_x10 {
593					mux {
594						groups = "pwm_c_x10";
595						function = "pwm_c";
596						bias-disable;
597					};
598				};
599
600				pwm_c_x17_pins: pwm_c_x17 {
601					mux {
602						groups = "pwm_c_x17";
603						function = "pwm_c";
604						bias-disable;
605					};
606				};
607
608				pwm_d_x11_pins: pwm_d_x11 {
609					mux {
610						groups = "pwm_d_x11";
611						function = "pwm_d";
612						bias-disable;
613					};
614				};
615
616				pwm_d_x16_pins: pwm_d_x16 {
617					mux {
618						groups = "pwm_d_x16";
619						function = "pwm_d";
620						bias-disable;
621					};
622				};
623
624				sdio_pins: sdio {
625					mux-0 {
626						groups = "sdio_d0",
627							 "sdio_d1",
628							 "sdio_d2",
629							 "sdio_d3",
630							 "sdio_cmd";
631						function = "sdio";
632						bias-pull-up;
633					};
634
635					mux-1 {
636						groups = "sdio_clk";
637						function = "sdio";
638						bias-disable;
639					};
640				};
641
642				sdio_clk_gate_pins: sdio_clk_gate {
643					mux {
644						groups = "GPIOX_4";
645						function = "gpio_periphs";
646						bias-pull-down;
647					};
648				};
649
650				spdif_in_z_pins: spdif_in_z {
651					mux {
652						groups = "spdif_in_z";
653						function = "spdif_in";
654						bias-disable;
655					};
656				};
657
658				spdif_in_a1_pins: spdif_in_a1 {
659					mux {
660						groups = "spdif_in_a1";
661						function = "spdif_in";
662						bias-disable;
663					};
664				};
665
666				spdif_in_a7_pins: spdif_in_a7 {
667					mux {
668						groups = "spdif_in_a7";
669						function = "spdif_in";
670						bias-disable;
671					};
672				};
673
674				spdif_in_a19_pins: spdif_in_a19 {
675					mux {
676						groups = "spdif_in_a19";
677						function = "spdif_in";
678						bias-disable;
679					};
680				};
681
682				spdif_in_a20_pins: spdif_in_a20 {
683					mux {
684						groups = "spdif_in_a20";
685						function = "spdif_in";
686						bias-disable;
687					};
688				};
689
690				spdif_out_a1_pins: spdif_out_a1 {
691					mux {
692						groups = "spdif_out_a1";
693						function = "spdif_out";
694						bias-disable;
695					};
696				};
697
698				spdif_out_a11_pins: spdif_out_a11 {
699					mux {
700						groups = "spdif_out_a11";
701						function = "spdif_out";
702						bias-disable;
703					};
704				};
705
706				spdif_out_a19_pins: spdif_out_a19 {
707					mux {
708						groups = "spdif_out_a19";
709						function = "spdif_out";
710						bias-disable;
711					};
712				};
713
714				spdif_out_a20_pins: spdif_out_a20 {
715					mux {
716						groups = "spdif_out_a20";
717						function = "spdif_out";
718						bias-disable;
719					};
720				};
721
722				spdif_out_z_pins: spdif_out_z {
723					mux {
724						groups = "spdif_out_z";
725						function = "spdif_out";
726						bias-disable;
727					};
728				};
729
730				spi0_pins: spi0 {
731					mux {
732						groups = "spi0_miso",
733							 "spi0_mosi",
734							 "spi0_clk";
735						function = "spi0";
736						bias-disable;
737					};
738				};
739
740				spi0_ss0_pins: spi0_ss0 {
741					mux {
742						groups = "spi0_ss0";
743						function = "spi0";
744						bias-disable;
745					};
746				};
747
748				spi0_ss1_pins: spi0_ss1 {
749					mux {
750						groups = "spi0_ss1";
751						function = "spi0";
752						bias-disable;
753					};
754				};
755
756				spi0_ss2_pins: spi0_ss2 {
757					mux {
758						groups = "spi0_ss2";
759						function = "spi0";
760						bias-disable;
761					};
762				};
763
764				spi1_a_pins: spi1_a {
765					mux {
766						groups = "spi1_miso_a",
767							 "spi1_mosi_a",
768							 "spi1_clk_a";
769						function = "spi1";
770						bias-disable;
771					};
772				};
773
774				spi1_ss0_a_pins: spi1_ss0_a {
775					mux {
776						groups = "spi1_ss0_a";
777						function = "spi1";
778						bias-disable;
779					};
780				};
781
782				spi1_ss1_pins: spi1_ss1 {
783					mux {
784						groups = "spi1_ss1";
785						function = "spi1";
786						bias-disable;
787					};
788				};
789
790				spi1_x_pins: spi1_x {
791					mux {
792						groups = "spi1_miso_x",
793							 "spi1_mosi_x",
794							 "spi1_clk_x";
795						function = "spi1";
796						bias-disable;
797					};
798				};
799
800				spi1_ss0_x_pins: spi1_ss0_x {
801					mux {
802						groups = "spi1_ss0_x";
803						function = "spi1";
804						bias-disable;
805					};
806				};
807
808				tdma_din0_pins: tdma_din0 {
809					mux {
810						groups = "tdma_din0";
811						function = "tdma";
812						bias-disable;
813					};
814				};
815
816				tdma_dout0_x14_pins: tdma_dout0_x14 {
817					mux {
818						groups = "tdma_dout0_x14";
819						function = "tdma";
820						bias-disable;
821					};
822				};
823
824				tdma_dout0_x15_pins: tdma_dout0_x15 {
825					mux {
826						groups = "tdma_dout0_x15";
827						function = "tdma";
828						bias-disable;
829					};
830				};
831
832				tdma_dout1_pins: tdma_dout1 {
833					mux {
834						groups = "tdma_dout1";
835						function = "tdma";
836						bias-disable;
837					};
838				};
839
840				tdma_din1_pins: tdma_din1 {
841					mux {
842						groups = "tdma_din1";
843						function = "tdma";
844						bias-disable;
845					};
846				};
847
848				tdma_fs_pins: tdma_fs {
849					mux {
850						groups = "tdma_fs";
851						function = "tdma";
852						bias-disable;
853					};
854				};
855
856				tdma_fs_slv_pins: tdma_fs_slv {
857					mux {
858						groups = "tdma_fs_slv";
859						function = "tdma";
860						bias-disable;
861					};
862				};
863
864				tdma_sclk_pins: tdma_sclk {
865					mux {
866						groups = "tdma_sclk";
867						function = "tdma";
868						bias-disable;
869					};
870				};
871
872				tdma_sclk_slv_pins: tdma_sclk_slv {
873					mux {
874						groups = "tdma_sclk_slv";
875						function = "tdma";
876						bias-disable;
877					};
878				};
879
880				tdmb_din0_pins: tdmb_din0 {
881					mux {
882						groups = "tdmb_din0";
883						function = "tdmb";
884						bias-disable;
885					};
886				};
887
888				tdmb_din1_pins: tdmb_din1 {
889					mux {
890						groups = "tdmb_din1";
891						function = "tdmb";
892						bias-disable;
893					};
894				};
895
896				tdmb_din2_pins: tdmb_din2 {
897					mux {
898						groups = "tdmb_din2";
899						function = "tdmb";
900						bias-disable;
901					};
902				};
903
904				tdmb_din3_pins: tdmb_din3 {
905					mux {
906						groups = "tdmb_din3";
907						function = "tdmb";
908						bias-disable;
909					};
910				};
911
912				tdmb_dout0_pins: tdmb_dout0 {
913					mux {
914						groups = "tdmb_dout0";
915						function = "tdmb";
916						bias-disable;
917					};
918				};
919
920				tdmb_dout1_pins: tdmb_dout1 {
921					mux {
922						groups = "tdmb_dout1";
923						function = "tdmb";
924						bias-disable;
925					};
926				};
927
928				tdmb_dout2_pins: tdmb_dout2 {
929					mux {
930						groups = "tdmb_dout2";
931						function = "tdmb";
932						bias-disable;
933					};
934				};
935
936				tdmb_dout3_pins: tdmb_dout3 {
937					mux {
938						groups = "tdmb_dout3";
939						function = "tdmb";
940						bias-disable;
941					};
942				};
943
944				tdmb_fs_pins: tdmb_fs {
945					mux {
946						groups = "tdmb_fs";
947						function = "tdmb";
948						bias-disable;
949					};
950				};
951
952				tdmb_fs_slv_pins: tdmb_fs_slv {
953					mux {
954						groups = "tdmb_fs_slv";
955						function = "tdmb";
956						bias-disable;
957					};
958				};
959
960				tdmb_sclk_pins: tdmb_sclk {
961					mux {
962						groups = "tdmb_sclk";
963						function = "tdmb";
964						bias-disable;
965					};
966				};
967
968				tdmb_sclk_slv_pins: tdmb_sclk_slv {
969					mux {
970						groups = "tdmb_sclk_slv";
971						function = "tdmb";
972						bias-disable;
973					};
974				};
975
976				tdmc_fs_pins: tdmc_fs {
977					mux {
978						groups = "tdmc_fs";
979						function = "tdmc";
980						bias-disable;
981					};
982				};
983
984				tdmc_fs_slv_pins: tdmc_fs_slv {
985					mux {
986						groups = "tdmc_fs_slv";
987						function = "tdmc";
988						bias-disable;
989					};
990				};
991
992				tdmc_sclk_pins: tdmc_sclk {
993					mux {
994						groups = "tdmc_sclk";
995						function = "tdmc";
996						bias-disable;
997					};
998				};
999
1000				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1001					mux {
1002						groups = "tdmc_sclk_slv";
1003						function = "tdmc";
1004						bias-disable;
1005					};
1006				};
1007
1008				tdmc_din0_pins: tdmc_din0 {
1009					mux {
1010						groups = "tdmc_din0";
1011						function = "tdmc";
1012						bias-disable;
1013					};
1014				};
1015
1016				tdmc_din1_pins: tdmc_din1 {
1017					mux {
1018						groups = "tdmc_din1";
1019						function = "tdmc";
1020						bias-disable;
1021					};
1022				};
1023
1024				tdmc_din2_pins: tdmc_din2 {
1025					mux {
1026						groups = "tdmc_din2";
1027						function = "tdmc";
1028						bias-disable;
1029					};
1030				};
1031
1032				tdmc_din3_pins: tdmc_din3 {
1033					mux {
1034						groups = "tdmc_din3";
1035						function = "tdmc";
1036						bias-disable;
1037					};
1038				};
1039
1040				tdmc_dout0_pins: tdmc_dout0 {
1041					mux {
1042						groups = "tdmc_dout0";
1043						function = "tdmc";
1044						bias-disable;
1045					};
1046				};
1047
1048				tdmc_dout1_pins: tdmc_dout1 {
1049					mux {
1050						groups = "tdmc_dout1";
1051						function = "tdmc";
1052						bias-disable;
1053					};
1054				};
1055
1056				tdmc_dout2_pins: tdmc_dout2 {
1057					mux {
1058						groups = "tdmc_dout2";
1059						function = "tdmc";
1060						bias-disable;
1061					};
1062				};
1063
1064				tdmc_dout3_pins: tdmc_dout3 {
1065					mux {
1066						groups = "tdmc_dout3";
1067						function = "tdmc";
1068						bias-disable;
1069					};
1070				};
1071
1072				uart_a_pins: uart_a {
1073					mux {
1074						groups = "uart_tx_a",
1075							 "uart_rx_a";
1076						function = "uart_a";
1077						bias-disable;
1078					};
1079				};
1080
1081				uart_a_cts_rts_pins: uart_a_cts_rts {
1082					mux {
1083						groups = "uart_cts_a",
1084							 "uart_rts_a";
1085						function = "uart_a";
1086						bias-disable;
1087					};
1088				};
1089
1090				uart_b_x_pins: uart_b_x {
1091					mux {
1092						groups = "uart_tx_b_x",
1093							 "uart_rx_b_x";
1094						function = "uart_b";
1095						bias-disable;
1096					};
1097				};
1098
1099				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1100					mux {
1101						groups = "uart_cts_b_x",
1102							 "uart_rts_b_x";
1103						function = "uart_b";
1104						bias-disable;
1105					};
1106				};
1107
1108				uart_b_z_pins: uart_b_z {
1109					mux {
1110						groups = "uart_tx_b_z",
1111							 "uart_rx_b_z";
1112						function = "uart_b";
1113						bias-disable;
1114					};
1115				};
1116
1117				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1118					mux {
1119						groups = "uart_cts_b_z",
1120							 "uart_rts_b_z";
1121						function = "uart_b";
1122						bias-disable;
1123					};
1124				};
1125
1126				uart_ao_b_z_pins: uart_ao_b_z {
1127					mux {
1128						groups = "uart_ao_tx_b_z",
1129							 "uart_ao_rx_b_z";
1130						function = "uart_ao_b_z";
1131						bias-disable;
1132					};
1133				};
1134
1135				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1136					mux {
1137						groups = "uart_ao_cts_b_z",
1138							 "uart_ao_rts_b_z";
1139						function = "uart_ao_b_z";
1140						bias-disable;
1141					};
1142				};
1143			};
1144		};
1145
1146		hiubus: bus@ff63c000 {
1147			compatible = "simple-bus";
1148			reg = <0x0 0xff63c000 0x0 0x1c00>;
1149			#address-cells = <2>;
1150			#size-cells = <2>;
1151			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1152
1153			sysctrl: system-controller@0 {
1154				compatible = "amlogic,meson-axg-hhi-sysctrl",
1155					     "simple-mfd", "syscon";
1156				reg = <0 0 0 0x400>;
1157
1158				clkc: clock-controller {
1159					compatible = "amlogic,axg-clkc";
1160					#clock-cells = <1>;
1161					clocks = <&xtal>;
1162					clock-names = "xtal";
1163				};
1164
1165				pwrc: power-controller {
1166					compatible = "amlogic,meson-axg-pwrc";
1167					#power-domain-cells = <1>;
1168					amlogic,ao-sysctrl = <&sysctrl_AO>;
1169					resets = <&reset RESET_VIU>,
1170						 <&reset RESET_VENC>,
1171						 <&reset RESET_VCBUS>,
1172						 <&reset RESET_VENCL>,
1173						 <&reset RESET_VID_LOCK>;
1174					reset-names = "viu", "venc", "vcbus",
1175						      "vencl", "vid_lock";
1176					clocks = <&clkc CLKID_VPU>,
1177						 <&clkc CLKID_VAPB>;
1178					clock-names = "vpu", "vapb";
1179					/*
1180					 * VPU clocking is provided by two identical clock paths
1181					 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1182					 * free mux to safely change frequency while running.
1183					 * Same for VAPB but with a final gate after the glitch free mux.
1184					 */
1185					assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1186							  <&clkc CLKID_VPU_0>,
1187							  <&clkc CLKID_VPU>, /* Glitch free mux */
1188							  <&clkc CLKID_VAPB_0_SEL>,
1189							  <&clkc CLKID_VAPB_0>,
1190							  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1191					assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1192								 <0>, /* Do Nothing */
1193								 <&clkc CLKID_VPU_0>,
1194								 <&clkc CLKID_FCLK_DIV4>,
1195								 <0>, /* Do Nothing */
1196								 <&clkc CLKID_VAPB_0>;
1197					assigned-clock-rates = <0>, /* Do Nothing */
1198							       <250000000>,
1199							       <0>, /* Do Nothing */
1200							       <0>, /* Do Nothing */
1201							       <250000000>,
1202							       <0>; /* Do Nothing */
1203				};
1204
1205				mipi_pcie_analog_dphy: phy {
1206					compatible = "amlogic,axg-mipi-pcie-analog-phy";
1207					#phy-cells = <0>;
1208					status = "disabled";
1209				};
1210			};
1211		};
1212
1213		mailbox: mailbox@ff63c404 {
1214			compatible = "amlogic,meson-gxbb-mhu";
1215			reg = <0 0xff63c404 0 0x4c>;
1216			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1217				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1218				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1219			#mbox-cells = <1>;
1220		};
1221
1222		mipi_dphy: phy@ff640000 {
1223			compatible = "amlogic,axg-mipi-dphy";
1224			reg = <0x0 0xff640000 0x0 0x100>;
1225			clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1226			clock-names = "pclk";
1227			resets = <&reset RESET_MIPI_PHY>;
1228			reset-names = "phy";
1229			phys = <&mipi_pcie_analog_dphy>;
1230			phy-names = "analog";
1231			#phy-cells = <0>;
1232			status = "disabled";
1233		};
1234
1235		audio: bus@ff642000 {
1236			compatible = "simple-bus";
1237			reg = <0x0 0xff642000 0x0 0x2000>;
1238			#address-cells = <2>;
1239			#size-cells = <2>;
1240			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1241
1242			clkc_audio: clock-controller@0 {
1243				compatible = "amlogic,axg-audio-clkc";
1244				reg = <0x0 0x0 0x0 0xb4>;
1245				#clock-cells = <1>;
1246
1247				clocks = <&clkc CLKID_AUDIO>,
1248					 <&clkc CLKID_MPLL0>,
1249					 <&clkc CLKID_MPLL1>,
1250					 <&clkc CLKID_MPLL2>,
1251					 <&clkc CLKID_MPLL3>,
1252					 <&clkc CLKID_HIFI_PLL>,
1253					 <&clkc CLKID_FCLK_DIV3>,
1254					 <&clkc CLKID_FCLK_DIV4>,
1255					 <&clkc CLKID_GP0_PLL>;
1256				clock-names = "pclk",
1257					      "mst_in0",
1258					      "mst_in1",
1259					      "mst_in2",
1260					      "mst_in3",
1261					      "mst_in4",
1262					      "mst_in5",
1263					      "mst_in6",
1264					      "mst_in7";
1265
1266				resets = <&reset RESET_AUDIO>;
1267			};
1268
1269			toddr_a: audio-controller@100 {
1270				compatible = "amlogic,axg-toddr";
1271				reg = <0x0 0x100 0x0 0x2c>;
1272				#sound-dai-cells = <0>;
1273				sound-name-prefix = "TODDR_A";
1274				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1275				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1276				resets = <&arb AXG_ARB_TODDR_A>;
1277				amlogic,fifo-depth = <512>;
1278				status = "disabled";
1279			};
1280
1281			toddr_b: audio-controller@140 {
1282				compatible = "amlogic,axg-toddr";
1283				reg = <0x0 0x140 0x0 0x2c>;
1284				#sound-dai-cells = <0>;
1285				sound-name-prefix = "TODDR_B";
1286				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1287				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1288				resets = <&arb AXG_ARB_TODDR_B>;
1289				amlogic,fifo-depth = <256>;
1290				status = "disabled";
1291			};
1292
1293			toddr_c: audio-controller@180 {
1294				compatible = "amlogic,axg-toddr";
1295				reg = <0x0 0x180 0x0 0x2c>;
1296				#sound-dai-cells = <0>;
1297				sound-name-prefix = "TODDR_C";
1298				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1299				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1300				resets = <&arb AXG_ARB_TODDR_C>;
1301				amlogic,fifo-depth = <256>;
1302				status = "disabled";
1303			};
1304
1305			frddr_a: audio-controller@1c0 {
1306				compatible = "amlogic,axg-frddr";
1307				reg = <0x0 0x1c0 0x0 0x2c>;
1308				#sound-dai-cells = <0>;
1309				sound-name-prefix = "FRDDR_A";
1310				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1311				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1312				resets = <&arb AXG_ARB_FRDDR_A>;
1313				amlogic,fifo-depth = <512>;
1314				status = "disabled";
1315			};
1316
1317			frddr_b: audio-controller@200 {
1318				compatible = "amlogic,axg-frddr";
1319				reg = <0x0 0x200 0x0 0x2c>;
1320				#sound-dai-cells = <0>;
1321				sound-name-prefix = "FRDDR_B";
1322				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1323				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1324				resets = <&arb AXG_ARB_FRDDR_B>;
1325				amlogic,fifo-depth = <256>;
1326				status = "disabled";
1327			};
1328
1329			frddr_c: audio-controller@240 {
1330				compatible = "amlogic,axg-frddr";
1331				reg = <0x0 0x240 0x0 0x2c>;
1332				#sound-dai-cells = <0>;
1333				sound-name-prefix = "FRDDR_C";
1334				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1335				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1336				resets = <&arb AXG_ARB_FRDDR_C>;
1337				amlogic,fifo-depth = <256>;
1338				status = "disabled";
1339			};
1340
1341			arb: reset-controller@280 {
1342				compatible = "amlogic,meson-axg-audio-arb";
1343				reg = <0x0 0x280 0x0 0x4>;
1344				#reset-cells = <1>;
1345				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1346			};
1347
1348			tdmin_a: audio-controller@300 {
1349				compatible = "amlogic,axg-tdmin";
1350				reg = <0x0 0x300 0x0 0x40>;
1351				sound-name-prefix = "TDMIN_A";
1352				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1353					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1354					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1355					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1356					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1357				clock-names = "pclk", "sclk", "sclk_sel",
1358					      "lrclk", "lrclk_sel";
1359				status = "disabled";
1360			};
1361
1362			tdmin_b: audio-controller@340 {
1363				compatible = "amlogic,axg-tdmin";
1364				reg = <0x0 0x340 0x0 0x40>;
1365				sound-name-prefix = "TDMIN_B";
1366				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1367					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1368					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1369					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1370					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1371				clock-names = "pclk", "sclk", "sclk_sel",
1372					      "lrclk", "lrclk_sel";
1373				status = "disabled";
1374			};
1375
1376			tdmin_c: audio-controller@380 {
1377				compatible = "amlogic,axg-tdmin";
1378				reg = <0x0 0x380 0x0 0x40>;
1379				sound-name-prefix = "TDMIN_C";
1380				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1381					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1382					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1383					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1384					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1385				clock-names = "pclk", "sclk", "sclk_sel",
1386					      "lrclk", "lrclk_sel";
1387				status = "disabled";
1388			};
1389
1390			tdmin_lb: audio-controller@3c0 {
1391				compatible = "amlogic,axg-tdmin";
1392				reg = <0x0 0x3c0 0x0 0x40>;
1393				sound-name-prefix = "TDMIN_LB";
1394				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1395					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1396					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1397					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1398					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1399				clock-names = "pclk", "sclk", "sclk_sel",
1400					      "lrclk", "lrclk_sel";
1401				status = "disabled";
1402			};
1403
1404			spdifin: audio-controller@400 {
1405				compatible = "amlogic,axg-spdifin";
1406				reg = <0x0 0x400 0x0 0x30>;
1407				#sound-dai-cells = <0>;
1408				sound-name-prefix = "SPDIFIN";
1409				interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1410				clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1411					 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1412				clock-names = "pclk", "refclk";
1413				status = "disabled";
1414			};
1415
1416			spdifout: audio-controller@480 {
1417				compatible = "amlogic,axg-spdifout";
1418				reg = <0x0 0x480 0x0 0x50>;
1419				#sound-dai-cells = <0>;
1420				sound-name-prefix = "SPDIFOUT";
1421				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1422					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1423				clock-names = "pclk", "mclk";
1424				status = "disabled";
1425			};
1426
1427			tdmout_a: audio-controller@500 {
1428				compatible = "amlogic,axg-tdmout";
1429				reg = <0x0 0x500 0x0 0x40>;
1430				sound-name-prefix = "TDMOUT_A";
1431				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1432					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1433					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1434					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1435					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1436				clock-names = "pclk", "sclk", "sclk_sel",
1437					      "lrclk", "lrclk_sel";
1438				status = "disabled";
1439			};
1440
1441			tdmout_b: audio-controller@540 {
1442				compatible = "amlogic,axg-tdmout";
1443				reg = <0x0 0x540 0x0 0x40>;
1444				sound-name-prefix = "TDMOUT_B";
1445				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1446					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1447					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1448					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1449					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1450				clock-names = "pclk", "sclk", "sclk_sel",
1451					      "lrclk", "lrclk_sel";
1452				status = "disabled";
1453			};
1454
1455			tdmout_c: audio-controller@580 {
1456				compatible = "amlogic,axg-tdmout";
1457				reg = <0x0 0x580 0x0 0x40>;
1458				sound-name-prefix = "TDMOUT_C";
1459				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1460					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1461					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1462					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1463					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1464				clock-names = "pclk", "sclk", "sclk_sel",
1465					      "lrclk", "lrclk_sel";
1466				status = "disabled";
1467			};
1468		};
1469
1470		aobus: bus@ff800000 {
1471			compatible = "simple-bus";
1472			reg = <0x0 0xff800000 0x0 0x100000>;
1473			#address-cells = <2>;
1474			#size-cells = <2>;
1475			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1476
1477			sysctrl_AO: sys-ctrl@0 {
1478				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1479				reg =  <0x0 0x0 0x0 0x100>;
1480
1481				clkc_AO: clock-controller {
1482					compatible = "amlogic,meson-axg-aoclkc";
1483					#clock-cells = <1>;
1484					#reset-cells = <1>;
1485					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1486					clock-names = "xtal", "mpeg-clk";
1487				};
1488			};
1489
1490			pinctrl_aobus: pinctrl@14 {
1491				compatible = "amlogic,meson-axg-aobus-pinctrl";
1492				#address-cells = <2>;
1493				#size-cells = <2>;
1494				ranges;
1495
1496				gpio_ao: bank@14 {
1497					reg = <0x0 0x00014 0x0 0x8>,
1498					      <0x0 0x0002c 0x0 0x4>,
1499					      <0x0 0x00024 0x0 0x8>;
1500					reg-names = "mux", "pull", "gpio";
1501					gpio-controller;
1502					#gpio-cells = <2>;
1503					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1504				};
1505
1506				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1507					mux {
1508						groups = "i2c_ao_sck_4";
1509						function = "i2c_ao";
1510						bias-disable;
1511					};
1512				};
1513
1514				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1515					mux {
1516						groups = "i2c_ao_sck_8";
1517						function = "i2c_ao";
1518						bias-disable;
1519					};
1520				};
1521
1522				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1523					mux {
1524						groups = "i2c_ao_sck_10";
1525						function = "i2c_ao";
1526						bias-disable;
1527					};
1528				};
1529
1530				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1531					mux {
1532						groups = "i2c_ao_sda_5";
1533						function = "i2c_ao";
1534						bias-disable;
1535					};
1536				};
1537
1538				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1539					mux {
1540						groups = "i2c_ao_sda_9";
1541						function = "i2c_ao";
1542						bias-disable;
1543					};
1544				};
1545
1546				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1547					mux {
1548						groups = "i2c_ao_sda_11";
1549						function = "i2c_ao";
1550						bias-disable;
1551					};
1552				};
1553
1554				remote_input_ao_pins: remote_input_ao {
1555					mux {
1556						groups = "remote_input_ao";
1557						function = "remote_input_ao";
1558						bias-disable;
1559					};
1560				};
1561
1562				uart_ao_a_pins: uart_ao_a {
1563					mux {
1564						groups = "uart_ao_tx_a",
1565							 "uart_ao_rx_a";
1566						function = "uart_ao_a";
1567						bias-disable;
1568					};
1569				};
1570
1571				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1572					mux {
1573						groups = "uart_ao_cts_a",
1574							 "uart_ao_rts_a";
1575						function = "uart_ao_a";
1576						bias-disable;
1577					};
1578				};
1579
1580				uart_ao_b_pins: uart_ao_b {
1581					mux {
1582						groups = "uart_ao_tx_b",
1583							 "uart_ao_rx_b";
1584						function = "uart_ao_b";
1585						bias-disable;
1586					};
1587				};
1588
1589				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1590					mux {
1591						groups = "uart_ao_cts_b",
1592							 "uart_ao_rts_b";
1593						function = "uart_ao_b";
1594						bias-disable;
1595					};
1596				};
1597			};
1598
1599			sec_AO: ao-secure@140 {
1600				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1601				reg = <0x0 0x140 0x0 0x140>;
1602				amlogic,has-chip-id;
1603			};
1604
1605			pwm_AO_cd: pwm@2000 {
1606				compatible = "amlogic,meson-axg-ao-pwm";
1607				reg = <0x0 0x02000  0x0 0x20>;
1608				#pwm-cells = <3>;
1609				status = "disabled";
1610			};
1611
1612			uart_AO: serial@3000 {
1613				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1614				reg = <0x0 0x3000 0x0 0x18>;
1615				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1616				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1617				clock-names = "xtal", "pclk", "baud";
1618				status = "disabled";
1619			};
1620
1621			uart_AO_B: serial@4000 {
1622				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1623				reg = <0x0 0x4000 0x0 0x18>;
1624				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1625				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1626				clock-names = "xtal", "pclk", "baud";
1627				status = "disabled";
1628			};
1629
1630			i2c_AO: i2c@5000 {
1631				compatible = "amlogic,meson-axg-i2c";
1632				reg = <0x0 0x05000 0x0 0x20>;
1633				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1634				clocks = <&clkc CLKID_AO_I2C>;
1635				#address-cells = <1>;
1636				#size-cells = <0>;
1637				status = "disabled";
1638			};
1639
1640			pwm_AO_ab: pwm@7000 {
1641				compatible = "amlogic,meson-axg-ao-pwm";
1642				reg = <0x0 0x07000 0x0 0x20>;
1643				#pwm-cells = <3>;
1644				status = "disabled";
1645			};
1646
1647			ir: ir@8000 {
1648				compatible = "amlogic,meson-gxbb-ir";
1649				reg = <0x0 0x8000 0x0 0x20>;
1650				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1651				status = "disabled";
1652			};
1653
1654			saradc: adc@9000 {
1655				compatible = "amlogic,meson-axg-saradc",
1656					"amlogic,meson-saradc";
1657				reg = <0x0 0x9000 0x0 0x38>;
1658				#io-channel-cells = <1>;
1659				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1660				clocks = <&xtal>,
1661					 <&clkc_AO CLKID_AO_SAR_ADC>,
1662					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1663					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1664				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1665				status = "disabled";
1666			};
1667		};
1668
1669		gic: interrupt-controller@ffc01000 {
1670			compatible = "arm,gic-400";
1671			reg = <0x0 0xffc01000 0 0x1000>,
1672			      <0x0 0xffc02000 0 0x2000>,
1673			      <0x0 0xffc04000 0 0x2000>,
1674			      <0x0 0xffc06000 0 0x2000>;
1675			interrupt-controller;
1676			interrupts = <GIC_PPI 9
1677				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1678			#interrupt-cells = <3>;
1679			#address-cells = <0>;
1680		};
1681
1682		cbus: bus@ffd00000 {
1683			compatible = "simple-bus";
1684			reg = <0x0 0xffd00000 0x0 0x25000>;
1685			#address-cells = <2>;
1686			#size-cells = <2>;
1687			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1688
1689			reset: reset-controller@1004 {
1690				compatible = "amlogic,meson-axg-reset";
1691				reg = <0x0 0x01004 0x0 0x9c>;
1692				#reset-cells = <1>;
1693			};
1694
1695			gpio_intc: interrupt-controller@f080 {
1696				compatible = "amlogic,meson-axg-gpio-intc",
1697					     "amlogic,meson-gpio-intc";
1698				reg = <0x0 0xf080 0x0 0x10>;
1699				interrupt-controller;
1700				#interrupt-cells = <2>;
1701				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1702			};
1703
1704			watchdog@f0d0 {
1705				compatible = "amlogic,meson-gxbb-wdt";
1706				reg = <0x0 0xf0d0 0x0 0x10>;
1707				clocks = <&xtal>;
1708			};
1709
1710			pwm_ab: pwm@1b000 {
1711				compatible = "amlogic,meson-axg-ee-pwm";
1712				reg = <0x0 0x1b000 0x0 0x20>;
1713				#pwm-cells = <3>;
1714				status = "disabled";
1715			};
1716
1717			pwm_cd: pwm@1a000 {
1718				compatible = "amlogic,meson-axg-ee-pwm";
1719				reg = <0x0 0x1a000 0x0 0x20>;
1720				#pwm-cells = <3>;
1721				status = "disabled";
1722			};
1723
1724			spicc0: spi@13000 {
1725				compatible = "amlogic,meson-axg-spicc";
1726				reg = <0x0 0x13000 0x0 0x3c>;
1727				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1728				clocks = <&clkc CLKID_SPICC0>;
1729				clock-names = "core";
1730				#address-cells = <1>;
1731				#size-cells = <0>;
1732				status = "disabled";
1733			};
1734
1735			spicc1: spi@15000 {
1736				compatible = "amlogic,meson-axg-spicc";
1737				reg = <0x0 0x15000 0x0 0x3c>;
1738				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1739				clocks = <&clkc CLKID_SPICC1>;
1740				clock-names = "core";
1741				#address-cells = <1>;
1742				#size-cells = <0>;
1743				status = "disabled";
1744			};
1745
1746			clk_msr: clock-measure@18000 {
1747				compatible = "amlogic,meson-axg-clk-measure";
1748				reg = <0x0 0x18000 0x0 0x10>;
1749			};
1750
1751			i2c3: i2c@1c000 {
1752				compatible = "amlogic,meson-axg-i2c";
1753				reg = <0x0 0x1c000 0x0 0x20>;
1754				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1755				clocks = <&clkc CLKID_I2C>;
1756				#address-cells = <1>;
1757				#size-cells = <0>;
1758				status = "disabled";
1759			};
1760
1761			i2c2: i2c@1d000 {
1762				compatible = "amlogic,meson-axg-i2c";
1763				reg = <0x0 0x1d000 0x0 0x20>;
1764				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1765				clocks = <&clkc CLKID_I2C>;
1766				#address-cells = <1>;
1767				#size-cells = <0>;
1768				status = "disabled";
1769			};
1770
1771			i2c1: i2c@1e000 {
1772				compatible = "amlogic,meson-axg-i2c";
1773				reg = <0x0 0x1e000 0x0 0x20>;
1774				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1775				clocks = <&clkc CLKID_I2C>;
1776				#address-cells = <1>;
1777				#size-cells = <0>;
1778				status = "disabled";
1779			};
1780
1781			i2c0: i2c@1f000 {
1782				compatible = "amlogic,meson-axg-i2c";
1783				reg = <0x0 0x1f000 0x0 0x20>;
1784				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1785				clocks = <&clkc CLKID_I2C>;
1786				#address-cells = <1>;
1787				#size-cells = <0>;
1788				status = "disabled";
1789			};
1790
1791			uart_B: serial@23000 {
1792				compatible = "amlogic,meson-gx-uart";
1793				reg = <0x0 0x23000 0x0 0x18>;
1794				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1795				status = "disabled";
1796				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1797				clock-names = "xtal", "pclk", "baud";
1798			};
1799
1800			uart_A: serial@24000 {
1801				compatible = "amlogic,meson-gx-uart";
1802				reg = <0x0 0x24000 0x0 0x18>;
1803				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1804				status = "disabled";
1805				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1806				clock-names = "xtal", "pclk", "baud";
1807			};
1808		};
1809
1810		apb: bus@ffe00000 {
1811			compatible = "simple-bus";
1812			reg = <0x0 0xffe00000 0x0 0x200000>;
1813			#address-cells = <2>;
1814			#size-cells = <2>;
1815			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1816
1817			sd_emmc_b: sd@5000 {
1818				compatible = "amlogic,meson-axg-mmc";
1819				reg = <0x0 0x5000 0x0 0x800>;
1820				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1821				status = "disabled";
1822				clocks = <&clkc CLKID_SD_EMMC_B>,
1823					<&clkc CLKID_SD_EMMC_B_CLK0>,
1824					<&clkc CLKID_FCLK_DIV2>;
1825				clock-names = "core", "clkin0", "clkin1";
1826				resets = <&reset RESET_SD_EMMC_B>;
1827			};
1828
1829			sd_emmc_c: mmc@7000 {
1830				compatible = "amlogic,meson-axg-mmc";
1831				reg = <0x0 0x7000 0x0 0x800>;
1832				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1833				status = "disabled";
1834				clocks = <&clkc CLKID_SD_EMMC_C>,
1835					<&clkc CLKID_SD_EMMC_C_CLK0>,
1836					<&clkc CLKID_FCLK_DIV2>;
1837				clock-names = "core", "clkin0", "clkin1";
1838				resets = <&reset RESET_SD_EMMC_C>;
1839			};
1840
1841			usb2_phy1: phy@9020 {
1842				compatible = "amlogic,meson-gxl-usb2-phy";
1843				#phy-cells = <0>;
1844				reg = <0x0 0x9020 0x0 0x20>;
1845				clocks = <&clkc CLKID_USB>;
1846				clock-names = "phy";
1847				resets = <&reset RESET_USB_OTG>;
1848				reset-names = "phy";
1849			};
1850		};
1851
1852		sram: sram@fffc0000 {
1853			compatible = "mmio-sram";
1854			reg = <0x0 0xfffc0000 0x0 0x20000>;
1855			#address-cells = <1>;
1856			#size-cells = <1>;
1857			ranges = <0 0x0 0xfffc0000 0x20000>;
1858
1859			cpu_scp_lpri: scp-sram@13000 {
1860				compatible = "amlogic,meson-axg-scp-shmem";
1861				reg = <0x13000 0x400>;
1862			};
1863
1864			cpu_scp_hpri: scp-sram@13400 {
1865				compatible = "amlogic,meson-axg-scp-shmem";
1866				reg = <0x13400 0x400>;
1867			};
1868		};
1869	};
1870
1871	timer {
1872		compatible = "arm,armv8-timer";
1873		interrupts = <GIC_PPI 13
1874			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1875			     <GIC_PPI 14
1876			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1877			     <GIC_PPI 11
1878			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1879			     <GIC_PPI 10
1880			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1881	};
1882
1883	xtal: xtal-clk {
1884		compatible = "fixed-clock";
1885		clock-frequency = <24000000>;
1886		clock-output-names = "xtal";
1887		#clock-cells = <0>;
1888	};
1889};
1890