1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 ao_alt_xtal: ao_alt_xtal-clk { 57 compatible = "fixed-clock"; 58 clock-frequency = <32000000>; 59 clock-output-names = "ao_alt_xtal"; 60 #clock-cells = <0>; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 cpus { 73 #address-cells = <0x2>; 74 #size-cells = <0x0>; 75 76 cpu0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 reg = <0x0 0x0>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 clocks = <&scpi_dvfs 0>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 reg = <0x0 0x1>; 89 enable-method = "psci"; 90 next-level-cache = <&l2>; 91 clocks = <&scpi_dvfs 0>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53", "arm,armv8"; 97 reg = <0x0 0x2>; 98 enable-method = "psci"; 99 next-level-cache = <&l2>; 100 clocks = <&scpi_dvfs 0>; 101 }; 102 103 cpu3: cpu@3 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53", "arm,armv8"; 106 reg = <0x0 0x3>; 107 enable-method = "psci"; 108 next-level-cache = <&l2>; 109 clocks = <&scpi_dvfs 0>; 110 }; 111 112 l2: l2-cache0 { 113 compatible = "cache"; 114 }; 115 }; 116 117 sm: secure-monitor { 118 compatible = "amlogic,meson-gxbb-sm"; 119 }; 120 121 psci { 122 compatible = "arm,psci-1.0"; 123 method = "smc"; 124 }; 125 126 reserved-memory { 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 131 /* 16 MiB reserved for Hardware ROM Firmware */ 132 hwrom_reserved: hwrom@0 { 133 reg = <0x0 0x0 0x0 0x1000000>; 134 no-map; 135 }; 136 137 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 138 secmon_reserved: secmon@5000000 { 139 reg = <0x0 0x05000000 0x0 0x300000>; 140 no-map; 141 }; 142 }; 143 144 scpi { 145 compatible = "arm,scpi-pre-1.0"; 146 mboxes = <&mailbox 1 &mailbox 2>; 147 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 148 149 scpi_clocks: clocks { 150 compatible = "arm,scpi-clocks"; 151 152 scpi_dvfs: clock-controller { 153 compatible = "arm,scpi-dvfs-clocks"; 154 #clock-cells = <1>; 155 clock-indices = <0>; 156 clock-output-names = "vcpu"; 157 }; 158 }; 159 160 scpi_sensors: sensors { 161 compatible = "amlogic,meson-gxbb-scpi-sensors"; 162 #thermal-sensor-cells = <1>; 163 }; 164 }; 165 166 soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 ethmac: ethernet@ff3f0000 { 173 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 174 reg = <0x0 0xff3f0000 0x0 0x10000 175 0x0 0xff634540 0x0 0x8>; 176 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 177 interrupt-names = "macirq"; 178 clocks = <&clkc CLKID_ETH>, 179 <&clkc CLKID_FCLK_DIV2>, 180 <&clkc CLKID_MPLL2>; 181 clock-names = "stmmaceth", "clkin0", "clkin1"; 182 status = "disabled"; 183 }; 184 185 pdm: audio-controller@ff632000 { 186 compatible = "amlogic,axg-pdm"; 187 reg = <0x0 0xff632000 0x0 0x34>; 188 #sound-dai-cells = <0>; 189 sound-name-prefix = "PDM"; 190 clocks = <&clkc_audio AUD_CLKID_PDM>, 191 <&clkc_audio AUD_CLKID_PDM_DCLK>, 192 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 193 clock-names = "pclk", "dclk", "sysclk"; 194 status = "disabled"; 195 }; 196 197 periphs: bus@ff634000 { 198 compatible = "simple-bus"; 199 reg = <0x0 0xff634000 0x0 0x2000>; 200 #address-cells = <2>; 201 #size-cells = <2>; 202 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 203 204 hwrng: rng@18 { 205 compatible = "amlogic,meson-rng"; 206 reg = <0x0 0x18 0x0 0x4>; 207 clocks = <&clkc CLKID_RNG0>; 208 clock-names = "core"; 209 }; 210 211 pinctrl_periphs: pinctrl@480 { 212 compatible = "amlogic,meson-axg-periphs-pinctrl"; 213 #address-cells = <2>; 214 #size-cells = <2>; 215 ranges; 216 217 gpio: bank@480 { 218 reg = <0x0 0x00480 0x0 0x40>, 219 <0x0 0x004e8 0x0 0x14>, 220 <0x0 0x00520 0x0 0x14>, 221 <0x0 0x00430 0x0 0x3c>; 222 reg-names = "mux", "pull", "pull-enable", "gpio"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 gpio-ranges = <&pinctrl_periphs 0 0 86>; 226 }; 227 228 i2c0_pins: i2c0 { 229 mux { 230 groups = "i2c0_sck", 231 "i2c0_sda"; 232 function = "i2c0"; 233 }; 234 }; 235 236 i2c1_x_pins: i2c1_x { 237 mux { 238 groups = "i2c1_sck_x", 239 "i2c1_sda_x"; 240 function = "i2c1"; 241 }; 242 }; 243 244 i2c1_z_pins: i2c1_z { 245 mux { 246 groups = "i2c1_sck_z", 247 "i2c1_sda_z"; 248 function = "i2c1"; 249 }; 250 }; 251 252 i2c2_a_pins: i2c2_a { 253 mux { 254 groups = "i2c2_sck_a", 255 "i2c2_sda_a"; 256 function = "i2c2"; 257 }; 258 }; 259 260 i2c2_x_pins: i2c2_x { 261 mux { 262 groups = "i2c2_sck_x", 263 "i2c2_sda_x"; 264 function = "i2c2"; 265 }; 266 }; 267 268 i2c3_a6_pins: i2c3_a6 { 269 mux { 270 groups = "i2c3_sda_a6", 271 "i2c3_sck_a7"; 272 function = "i2c3"; 273 }; 274 }; 275 276 i2c3_a12_pins: i2c3_a12 { 277 mux { 278 groups = "i2c3_sda_a12", 279 "i2c3_sck_a13"; 280 function = "i2c3"; 281 }; 282 }; 283 284 i2c3_a19_pins: i2c3_a19 { 285 mux { 286 groups = "i2c3_sda_a19", 287 "i2c3_sck_a20"; 288 function = "i2c3"; 289 }; 290 }; 291 292 emmc_pins: emmc { 293 mux { 294 groups = "emmc_nand_d0", 295 "emmc_nand_d1", 296 "emmc_nand_d2", 297 "emmc_nand_d3", 298 "emmc_nand_d4", 299 "emmc_nand_d5", 300 "emmc_nand_d6", 301 "emmc_nand_d7", 302 "emmc_clk", 303 "emmc_cmd", 304 "emmc_ds"; 305 function = "emmc"; 306 }; 307 }; 308 309 emmc_clk_gate_pins: emmc_clk_gate { 310 mux { 311 groups = "BOOT_8"; 312 function = "gpio_periphs"; 313 }; 314 cfg-pull-down { 315 pins = "BOOT_8"; 316 bias-pull-down; 317 }; 318 }; 319 320 eth_rgmii_x_pins: eth-x-rgmii { 321 mux { 322 groups = "eth_mdio_x", 323 "eth_mdc_x", 324 "eth_rgmii_rx_clk_x", 325 "eth_rx_dv_x", 326 "eth_rxd0_x", 327 "eth_rxd1_x", 328 "eth_rxd2_rgmii", 329 "eth_rxd3_rgmii", 330 "eth_rgmii_tx_clk", 331 "eth_txen_x", 332 "eth_txd0_x", 333 "eth_txd1_x", 334 "eth_txd2_rgmii", 335 "eth_txd3_rgmii"; 336 function = "eth"; 337 }; 338 }; 339 340 eth_rgmii_y_pins: eth-y-rgmii { 341 mux { 342 groups = "eth_mdio_y", 343 "eth_mdc_y", 344 "eth_rgmii_rx_clk_y", 345 "eth_rx_dv_y", 346 "eth_rxd0_y", 347 "eth_rxd1_y", 348 "eth_rxd2_rgmii", 349 "eth_rxd3_rgmii", 350 "eth_rgmii_tx_clk", 351 "eth_txen_y", 352 "eth_txd0_y", 353 "eth_txd1_y", 354 "eth_txd2_rgmii", 355 "eth_txd3_rgmii"; 356 function = "eth"; 357 }; 358 }; 359 360 eth_rmii_x_pins: eth-x-rmii { 361 mux { 362 groups = "eth_mdio_x", 363 "eth_mdc_x", 364 "eth_rgmii_rx_clk_x", 365 "eth_rx_dv_x", 366 "eth_rxd0_x", 367 "eth_rxd1_x", 368 "eth_txen_x", 369 "eth_txd0_x", 370 "eth_txd1_x"; 371 function = "eth"; 372 }; 373 }; 374 375 eth_rmii_y_pins: eth-y-rmii { 376 mux { 377 groups = "eth_mdio_y", 378 "eth_mdc_y", 379 "eth_rgmii_rx_clk_y", 380 "eth_rx_dv_y", 381 "eth_rxd0_y", 382 "eth_rxd1_y", 383 "eth_txen_y", 384 "eth_txd0_y", 385 "eth_txd1_y"; 386 function = "eth"; 387 }; 388 }; 389 390 mclk_b_pins: mclk_b { 391 mux { 392 groups = "mclk_b"; 393 function = "mclk_b"; 394 }; 395 }; 396 397 mclk_c_pins: mclk_c { 398 mux { 399 groups = "mclk_c"; 400 function = "mclk_c"; 401 }; 402 }; 403 404 pdm_dclk_a14_pins: pdm_dclk_a14 { 405 mux { 406 groups = "pdm_dclk_a14"; 407 function = "pdm"; 408 }; 409 }; 410 411 pdm_dclk_a19_pins: pdm_dclk_a19 { 412 mux { 413 groups = "pdm_dclk_a19"; 414 function = "pdm"; 415 }; 416 }; 417 418 pdm_din0_pins: pdm_din0 { 419 mux { 420 groups = "pdm_din0"; 421 function = "pdm"; 422 }; 423 }; 424 425 pdm_din1_pins: pdm_din1 { 426 mux { 427 groups = "pdm_din1"; 428 function = "pdm"; 429 }; 430 }; 431 432 pdm_din2_pins: pdm_din2 { 433 mux { 434 groups = "pdm_din2"; 435 function = "pdm"; 436 }; 437 }; 438 439 pdm_din3_pins: pdm_din3 { 440 mux { 441 groups = "pdm_din3"; 442 function = "pdm"; 443 }; 444 }; 445 446 pwm_a_a_pins: pwm_a_a { 447 mux { 448 groups = "pwm_a_a"; 449 function = "pwm_a"; 450 }; 451 }; 452 453 pwm_a_x18_pins: pwm_a_x18 { 454 mux { 455 groups = "pwm_a_x18"; 456 function = "pwm_a"; 457 }; 458 }; 459 460 pwm_a_x20_pins: pwm_a_x20 { 461 mux { 462 groups = "pwm_a_x20"; 463 function = "pwm_a"; 464 }; 465 }; 466 467 pwm_a_z_pins: pwm_a_z { 468 mux { 469 groups = "pwm_a_z"; 470 function = "pwm_a"; 471 }; 472 }; 473 474 pwm_b_a_pins: pwm_b_a { 475 mux { 476 groups = "pwm_b_a"; 477 function = "pwm_b"; 478 }; 479 }; 480 481 pwm_b_x_pins: pwm_b_x { 482 mux { 483 groups = "pwm_b_x"; 484 function = "pwm_b"; 485 }; 486 }; 487 488 pwm_b_z_pins: pwm_b_z { 489 mux { 490 groups = "pwm_b_z"; 491 function = "pwm_b"; 492 }; 493 }; 494 495 pwm_c_a_pins: pwm_c_a { 496 mux { 497 groups = "pwm_c_a"; 498 function = "pwm_c"; 499 }; 500 }; 501 502 pwm_c_x10_pins: pwm_c_x10 { 503 mux { 504 groups = "pwm_c_x10"; 505 function = "pwm_c"; 506 }; 507 }; 508 509 pwm_c_x17_pins: pwm_c_x17 { 510 mux { 511 groups = "pwm_c_x17"; 512 function = "pwm_c"; 513 }; 514 }; 515 516 pwm_d_x11_pins: pwm_d_x11 { 517 mux { 518 groups = "pwm_d_x11"; 519 function = "pwm_d"; 520 }; 521 }; 522 523 pwm_d_x16_pins: pwm_d_x16 { 524 mux { 525 groups = "pwm_d_x16"; 526 function = "pwm_d"; 527 }; 528 }; 529 530 sdio_pins: sdio { 531 mux { 532 groups = "sdio_d0", 533 "sdio_d1", 534 "sdio_d2", 535 "sdio_d3", 536 "sdio_cmd", 537 "sdio_clk"; 538 function = "sdio"; 539 }; 540 }; 541 542 sdio_clk_gate_pins: sdio_clk_gate { 543 mux { 544 groups = "GPIOX_4"; 545 function = "gpio_periphs"; 546 }; 547 cfg-pull-down { 548 pins = "GPIOX_4"; 549 bias-pull-down; 550 }; 551 }; 552 553 spdif_in_z_pins: spdif_in_z { 554 mux { 555 groups = "spdif_in_z"; 556 function = "spdif_in"; 557 }; 558 }; 559 560 spdif_in_a1_pins: spdif_in_a1 { 561 mux { 562 groups = "spdif_in_a1"; 563 function = "spdif_in"; 564 }; 565 }; 566 567 spdif_in_a7_pins: spdif_in_a7 { 568 mux { 569 groups = "spdif_in_a7"; 570 function = "spdif_in"; 571 }; 572 }; 573 574 spdif_in_a19_pins: spdif_in_a19 { 575 mux { 576 groups = "spdif_in_a19"; 577 function = "spdif_in"; 578 }; 579 }; 580 581 spdif_in_a20_pins: spdif_in_a20 { 582 mux { 583 groups = "spdif_in_a20"; 584 function = "spdif_in"; 585 }; 586 }; 587 588 spdif_out_a1_pins: spdif_out_a1 { 589 mux { 590 groups = "spdif_out_a1"; 591 function = "spdif_out"; 592 }; 593 }; 594 595 spdif_out_a11_pins: spdif_out_a11 { 596 mux { 597 groups = "spdif_out_a11"; 598 function = "spdif_out"; 599 }; 600 }; 601 602 spdif_out_a19_pins: spdif_out_a19 { 603 mux { 604 groups = "spdif_out_a19"; 605 function = "spdif_out"; 606 }; 607 }; 608 609 spdif_out_a20_pins: spdif_out_a20 { 610 mux { 611 groups = "spdif_out_a20"; 612 function = "spdif_out"; 613 }; 614 }; 615 616 spdif_out_z_pins: spdif_out_z { 617 mux { 618 groups = "spdif_out_z"; 619 function = "spdif_out"; 620 }; 621 }; 622 623 spi0_pins: spi0 { 624 mux { 625 groups = "spi0_miso", 626 "spi0_mosi", 627 "spi0_clk"; 628 function = "spi0"; 629 }; 630 }; 631 632 spi0_ss0_pins: spi0_ss0 { 633 mux { 634 groups = "spi0_ss0"; 635 function = "spi0"; 636 }; 637 }; 638 639 spi0_ss1_pins: spi0_ss1 { 640 mux { 641 groups = "spi0_ss1"; 642 function = "spi0"; 643 }; 644 }; 645 646 spi0_ss2_pins: spi0_ss2 { 647 mux { 648 groups = "spi0_ss2"; 649 function = "spi0"; 650 }; 651 }; 652 653 spi1_a_pins: spi1_a { 654 mux { 655 groups = "spi1_miso_a", 656 "spi1_mosi_a", 657 "spi1_clk_a"; 658 function = "spi1"; 659 }; 660 }; 661 662 spi1_ss0_a_pins: spi1_ss0_a { 663 mux { 664 groups = "spi1_ss0_a"; 665 function = "spi1"; 666 }; 667 }; 668 669 spi1_ss1_pins: spi1_ss1 { 670 mux { 671 groups = "spi1_ss1"; 672 function = "spi1"; 673 }; 674 }; 675 676 spi1_x_pins: spi1_x { 677 mux { 678 groups = "spi1_miso_x", 679 "spi1_mosi_x", 680 "spi1_clk_x"; 681 function = "spi1"; 682 }; 683 }; 684 685 spi1_ss0_x_pins: spi1_ss0_x { 686 mux { 687 groups = "spi1_ss0_x"; 688 function = "spi1"; 689 }; 690 }; 691 692 tdma_din0_pins: tdma_din0 { 693 mux { 694 groups = "tdma_din0"; 695 function = "tdma"; 696 }; 697 }; 698 699 tdma_dout0_x14_pins: tdma_dout0_x14 { 700 mux { 701 groups = "tdma_dout0_x14"; 702 function = "tdma"; 703 }; 704 }; 705 706 tdma_dout0_x15_pins: tdma_dout0_x15 { 707 mux { 708 groups = "tdma_dout0_x15"; 709 function = "tdma"; 710 }; 711 }; 712 713 tdma_dout1_pins: tdma_dout1 { 714 mux { 715 groups = "tdma_dout1"; 716 function = "tdma"; 717 }; 718 }; 719 720 tdma_din1_pins: tdma_din1 { 721 mux { 722 groups = "tdma_din1"; 723 function = "tdma"; 724 }; 725 }; 726 727 tdma_fs_pins: tdma_fs { 728 mux { 729 groups = "tdma_fs"; 730 function = "tdma"; 731 }; 732 }; 733 734 tdma_fs_slv_pins: tdma_fs_slv { 735 mux { 736 groups = "tdma_fs_slv"; 737 function = "tdma"; 738 }; 739 }; 740 741 tdma_sclk_pins: tdma_sclk { 742 mux { 743 groups = "tdma_sclk"; 744 function = "tdma"; 745 }; 746 }; 747 748 tdma_sclk_slv_pins: tdma_sclk_slv { 749 mux { 750 groups = "tdma_sclk_slv"; 751 function = "tdma"; 752 }; 753 }; 754 755 tdmb_din0_pins: tdmb_din0 { 756 mux { 757 groups = "tdmb_din0"; 758 function = "tdmb"; 759 }; 760 }; 761 762 tdmb_din1_pins: tdmb_din1 { 763 mux { 764 groups = "tdmb_din1"; 765 function = "tdmb"; 766 }; 767 }; 768 769 tdmb_din2_pins: tdmb_din2 { 770 mux { 771 groups = "tdmb_din2"; 772 function = "tdmb"; 773 }; 774 }; 775 776 tdmb_din3_pins: tdmb_din3 { 777 mux { 778 groups = "tdmb_din3"; 779 function = "tdmb"; 780 }; 781 }; 782 783 tdmb_dout0_pins: tdmb_dout0 { 784 mux { 785 groups = "tdmb_dout0"; 786 function = "tdmb"; 787 }; 788 }; 789 790 tdmb_dout1_pins: tdmb_dout1 { 791 mux { 792 groups = "tdmb_dout1"; 793 function = "tdmb"; 794 }; 795 }; 796 797 tdmb_dout2_pins: tdmb_dout2 { 798 mux { 799 groups = "tdmb_dout2"; 800 function = "tdmb"; 801 }; 802 }; 803 804 tdmb_dout3_pins: tdmb_dout3 { 805 mux { 806 groups = "tdmb_dout3"; 807 function = "tdmb"; 808 }; 809 }; 810 811 tdmb_fs_pins: tdmb_fs { 812 mux { 813 groups = "tdmb_fs"; 814 function = "tdmb"; 815 }; 816 }; 817 818 tdmb_fs_slv_pins: tdmb_fs_slv { 819 mux { 820 groups = "tdmb_fs_slv"; 821 function = "tdmb"; 822 }; 823 }; 824 825 tdmb_sclk_pins: tdmb_sclk { 826 mux { 827 groups = "tdmb_sclk"; 828 function = "tdmb"; 829 }; 830 }; 831 832 tdmb_sclk_slv_pins: tdmb_sclk_slv { 833 mux { 834 groups = "tdmb_sclk_slv"; 835 function = "tdmb"; 836 }; 837 }; 838 839 tdmc_fs_pins: tdmc_fs { 840 mux { 841 groups = "tdmc_fs"; 842 function = "tdmc"; 843 }; 844 }; 845 846 tdmc_fs_slv_pins: tdmc_fs_slv { 847 mux { 848 groups = "tdmc_fs_slv"; 849 function = "tdmc"; 850 }; 851 }; 852 853 tdmc_sclk_pins: tdmc_sclk { 854 mux { 855 groups = "tdmc_sclk"; 856 function = "tdmc"; 857 }; 858 }; 859 860 tdmc_sclk_slv_pins: tdmc_sclk_slv { 861 mux { 862 groups = "tdmc_sclk_slv"; 863 function = "tdmc"; 864 }; 865 }; 866 867 tdmc_din0_pins: tdmc_din0 { 868 mux { 869 groups = "tdmc_din0"; 870 function = "tdmc"; 871 }; 872 }; 873 874 tdmc_din1_pins: tdmc_din1 { 875 mux { 876 groups = "tdmc_din1"; 877 function = "tdmc"; 878 }; 879 }; 880 881 tdmc_din2_pins: tdmc_din2 { 882 mux { 883 groups = "tdmc_din2"; 884 function = "tdmc"; 885 }; 886 }; 887 888 tdmc_din3_pins: tdmc_din3 { 889 mux { 890 groups = "tdmc_din3"; 891 function = "tdmc"; 892 }; 893 }; 894 895 tdmc_dout0_pins: tdmc_dout0 { 896 mux { 897 groups = "tdmc_dout0"; 898 function = "tdmc"; 899 }; 900 }; 901 902 tdmc_dout1_pins: tdmc_dout1 { 903 mux { 904 groups = "tdmc_dout1"; 905 function = "tdmc"; 906 }; 907 }; 908 909 tdmc_dout2_pins: tdmc_dout2 { 910 mux { 911 groups = "tdmc_dout2"; 912 function = "tdmc"; 913 }; 914 }; 915 916 tdmc_dout3_pins: tdmc_dout3 { 917 mux { 918 groups = "tdmc_dout3"; 919 function = "tdmc"; 920 }; 921 }; 922 923 uart_a_pins: uart_a { 924 mux { 925 groups = "uart_tx_a", 926 "uart_rx_a"; 927 function = "uart_a"; 928 }; 929 }; 930 931 uart_a_cts_rts_pins: uart_a_cts_rts { 932 mux { 933 groups = "uart_cts_a", 934 "uart_rts_a"; 935 function = "uart_a"; 936 }; 937 }; 938 939 uart_b_x_pins: uart_b_x { 940 mux { 941 groups = "uart_tx_b_x", 942 "uart_rx_b_x"; 943 function = "uart_b"; 944 }; 945 }; 946 947 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 948 mux { 949 groups = "uart_cts_b_x", 950 "uart_rts_b_x"; 951 function = "uart_b"; 952 }; 953 }; 954 955 uart_b_z_pins: uart_b_z { 956 mux { 957 groups = "uart_tx_b_z", 958 "uart_rx_b_z"; 959 function = "uart_b"; 960 }; 961 }; 962 963 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 964 mux { 965 groups = "uart_cts_b_z", 966 "uart_rts_b_z"; 967 function = "uart_b"; 968 }; 969 }; 970 971 uart_ao_b_z_pins: uart_ao_b_z { 972 mux { 973 groups = "uart_ao_tx_b_z", 974 "uart_ao_rx_b_z"; 975 function = "uart_ao_b_z"; 976 }; 977 }; 978 979 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 980 mux { 981 groups = "uart_ao_cts_b_z", 982 "uart_ao_rts_b_z"; 983 function = "uart_ao_b_z"; 984 }; 985 }; 986 }; 987 }; 988 989 hiubus: bus@ff63c000 { 990 compatible = "simple-bus"; 991 reg = <0x0 0xff63c000 0x0 0x1c00>; 992 #address-cells = <2>; 993 #size-cells = <2>; 994 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 995 996 sysctrl: system-controller@0 { 997 compatible = "amlogic,meson-axg-hhi-sysctrl", 998 "simple-mfd", "syscon"; 999 reg = <0 0 0 0x400>; 1000 1001 clkc: clock-controller { 1002 compatible = "amlogic,axg-clkc"; 1003 #clock-cells = <1>; 1004 }; 1005 }; 1006 }; 1007 1008 mailbox: mailbox@ff63c404 { 1009 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 1010 reg = <0 0xff63c404 0 0x4c>; 1011 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1012 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1013 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1014 #mbox-cells = <1>; 1015 }; 1016 1017 audio: bus@ff642000 { 1018 compatible = "simple-bus"; 1019 reg = <0x0 0xff642000 0x0 0x2000>; 1020 #address-cells = <2>; 1021 #size-cells = <2>; 1022 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1023 1024 clkc_audio: clock-controller@0 { 1025 compatible = "amlogic,axg-audio-clkc"; 1026 reg = <0x0 0x0 0x0 0xb4>; 1027 #clock-cells = <1>; 1028 1029 clocks = <&clkc CLKID_AUDIO>, 1030 <&clkc CLKID_MPLL0>, 1031 <&clkc CLKID_MPLL1>, 1032 <&clkc CLKID_MPLL2>, 1033 <&clkc CLKID_MPLL3>, 1034 <&clkc CLKID_HIFI_PLL>, 1035 <&clkc CLKID_FCLK_DIV3>, 1036 <&clkc CLKID_FCLK_DIV4>, 1037 <&clkc CLKID_GP0_PLL>; 1038 clock-names = "pclk", 1039 "mst_in0", 1040 "mst_in1", 1041 "mst_in2", 1042 "mst_in3", 1043 "mst_in4", 1044 "mst_in5", 1045 "mst_in6", 1046 "mst_in7"; 1047 1048 resets = <&reset RESET_AUDIO>; 1049 }; 1050 1051 toddr_a: audio-controller@100 { 1052 compatible = "amlogic,axg-toddr"; 1053 reg = <0x0 0x100 0x0 0x1c>; 1054 #sound-dai-cells = <0>; 1055 sound-name-prefix = "TODDR_A"; 1056 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1057 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1058 resets = <&arb AXG_ARB_TODDR_A>; 1059 status = "disabled"; 1060 }; 1061 1062 toddr_b: audio-controller@140 { 1063 compatible = "amlogic,axg-toddr"; 1064 reg = <0x0 0x140 0x0 0x1c>; 1065 #sound-dai-cells = <0>; 1066 sound-name-prefix = "TODDR_B"; 1067 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1068 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1069 resets = <&arb AXG_ARB_TODDR_B>; 1070 status = "disabled"; 1071 }; 1072 1073 toddr_c: audio-controller@180 { 1074 compatible = "amlogic,axg-toddr"; 1075 reg = <0x0 0x180 0x0 0x1c>; 1076 #sound-dai-cells = <0>; 1077 sound-name-prefix = "TODDR_C"; 1078 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1079 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1080 resets = <&arb AXG_ARB_TODDR_C>; 1081 status = "disabled"; 1082 }; 1083 1084 frddr_a: audio-controller@1c0 { 1085 compatible = "amlogic,axg-frddr"; 1086 reg = <0x0 0x1c0 0x0 0x1c>; 1087 #sound-dai-cells = <0>; 1088 sound-name-prefix = "FRDDR_A"; 1089 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1090 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1091 resets = <&arb AXG_ARB_FRDDR_A>; 1092 status = "disabled"; 1093 }; 1094 1095 frddr_b: audio-controller@200 { 1096 compatible = "amlogic,axg-frddr"; 1097 reg = <0x0 0x200 0x0 0x1c>; 1098 #sound-dai-cells = <0>; 1099 sound-name-prefix = "FRDDR_B"; 1100 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1101 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1102 resets = <&arb AXG_ARB_FRDDR_B>; 1103 status = "disabled"; 1104 }; 1105 1106 frddr_c: audio-controller@240 { 1107 compatible = "amlogic,axg-frddr"; 1108 reg = <0x0 0x240 0x0 0x1c>; 1109 #sound-dai-cells = <0>; 1110 sound-name-prefix = "FRDDR_C"; 1111 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1112 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1113 resets = <&arb AXG_ARB_FRDDR_C>; 1114 status = "disabled"; 1115 }; 1116 1117 arb: reset-controller@280 { 1118 compatible = "amlogic,meson-axg-audio-arb"; 1119 reg = <0x0 0x280 0x0 0x4>; 1120 #reset-cells = <1>; 1121 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1122 }; 1123 1124 tdmin_a: audio-controller@300 { 1125 compatible = "amlogic,axg-tdmin"; 1126 reg = <0x0 0x300 0x0 0x40>; 1127 sound-name-prefix = "TDMIN_A"; 1128 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1129 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1130 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1131 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1132 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1133 clock-names = "pclk", "sclk", "sclk_sel", 1134 "lrclk", "lrclk_sel"; 1135 status = "disabled"; 1136 }; 1137 1138 tdmin_b: audio-controller@340 { 1139 compatible = "amlogic,axg-tdmin"; 1140 reg = <0x0 0x340 0x0 0x40>; 1141 sound-name-prefix = "TDMIN_B"; 1142 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1143 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1144 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1145 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1146 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1147 clock-names = "pclk", "sclk", "sclk_sel", 1148 "lrclk", "lrclk_sel"; 1149 status = "disabled"; 1150 }; 1151 1152 tdmin_c: audio-controller@380 { 1153 compatible = "amlogic,axg-tdmin"; 1154 reg = <0x0 0x380 0x0 0x40>; 1155 sound-name-prefix = "TDMIN_C"; 1156 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1157 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1158 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1159 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1160 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1161 clock-names = "pclk", "sclk", "sclk_sel", 1162 "lrclk", "lrclk_sel"; 1163 status = "disabled"; 1164 }; 1165 1166 tdmin_lb: audio-controller@3c0 { 1167 compatible = "amlogic,axg-tdmin"; 1168 reg = <0x0 0x3c0 0x0 0x40>; 1169 sound-name-prefix = "TDMIN_LB"; 1170 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1171 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1172 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1173 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1174 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1175 clock-names = "pclk", "sclk", "sclk_sel", 1176 "lrclk", "lrclk_sel"; 1177 status = "disabled"; 1178 }; 1179 1180 spdifout: audio-controller@480 { 1181 compatible = "amlogic,axg-spdifout"; 1182 reg = <0x0 0x480 0x0 0x50>; 1183 #sound-dai-cells = <0>; 1184 sound-name-prefix = "SPDIFOUT"; 1185 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1186 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1187 clock-names = "pclk", "mclk"; 1188 status = "disabled"; 1189 }; 1190 1191 tdmout_a: audio-controller@500 { 1192 compatible = "amlogic,axg-tdmout"; 1193 reg = <0x0 0x500 0x0 0x40>; 1194 sound-name-prefix = "TDMOUT_A"; 1195 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1196 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1197 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1198 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1199 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1200 clock-names = "pclk", "sclk", "sclk_sel", 1201 "lrclk", "lrclk_sel"; 1202 status = "disabled"; 1203 }; 1204 1205 tdmout_b: audio-controller@540 { 1206 compatible = "amlogic,axg-tdmout"; 1207 reg = <0x0 0x540 0x0 0x40>; 1208 sound-name-prefix = "TDMOUT_B"; 1209 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1210 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1211 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1212 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1213 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1214 clock-names = "pclk", "sclk", "sclk_sel", 1215 "lrclk", "lrclk_sel"; 1216 status = "disabled"; 1217 }; 1218 1219 tdmout_c: audio-controller@580 { 1220 compatible = "amlogic,axg-tdmout"; 1221 reg = <0x0 0x580 0x0 0x40>; 1222 sound-name-prefix = "TDMOUT_C"; 1223 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1224 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1225 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1226 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1227 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1228 clock-names = "pclk", "sclk", "sclk_sel", 1229 "lrclk", "lrclk_sel"; 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 aobus: bus@ff800000 { 1235 compatible = "simple-bus"; 1236 reg = <0x0 0xff800000 0x0 0x100000>; 1237 #address-cells = <2>; 1238 #size-cells = <2>; 1239 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1240 1241 sysctrl_AO: sys-ctrl@0 { 1242 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1243 reg = <0x0 0x0 0x0 0x100>; 1244 1245 clkc_AO: clock-controller { 1246 compatible = "amlogic,meson-axg-aoclkc"; 1247 #clock-cells = <1>; 1248 #reset-cells = <1>; 1249 }; 1250 }; 1251 1252 pinctrl_aobus: pinctrl@14 { 1253 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1254 #address-cells = <2>; 1255 #size-cells = <2>; 1256 ranges; 1257 1258 gpio_ao: bank@14 { 1259 reg = <0x0 0x00014 0x0 0x8>, 1260 <0x0 0x0002c 0x0 0x4>, 1261 <0x0 0x00024 0x0 0x8>; 1262 reg-names = "mux", "pull", "gpio"; 1263 gpio-controller; 1264 #gpio-cells = <2>; 1265 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1266 }; 1267 1268 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1269 mux { 1270 groups = "i2c_ao_sck_4"; 1271 function = "i2c_ao"; 1272 }; 1273 }; 1274 1275 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1276 mux { 1277 groups = "i2c_ao_sck_8"; 1278 function = "i2c_ao"; 1279 }; 1280 }; 1281 1282 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1283 mux { 1284 groups = "i2c_ao_sck_10"; 1285 function = "i2c_ao"; 1286 }; 1287 }; 1288 1289 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1290 mux { 1291 groups = "i2c_ao_sda_5"; 1292 function = "i2c_ao"; 1293 }; 1294 }; 1295 1296 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1297 mux { 1298 groups = "i2c_ao_sda_9"; 1299 function = "i2c_ao"; 1300 }; 1301 }; 1302 1303 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1304 mux { 1305 groups = "i2c_ao_sda_11"; 1306 function = "i2c_ao"; 1307 }; 1308 }; 1309 1310 remote_input_ao_pins: remote_input_ao { 1311 mux { 1312 groups = "remote_input_ao"; 1313 function = "remote_input_ao"; 1314 }; 1315 }; 1316 1317 uart_ao_a_pins: uart_ao_a { 1318 mux { 1319 groups = "uart_ao_tx_a", 1320 "uart_ao_rx_a"; 1321 function = "uart_ao_a"; 1322 }; 1323 }; 1324 1325 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1326 mux { 1327 groups = "uart_ao_cts_a", 1328 "uart_ao_rts_a"; 1329 function = "uart_ao_a"; 1330 }; 1331 }; 1332 1333 uart_ao_b_pins: uart_ao_b { 1334 mux { 1335 groups = "uart_ao_tx_b", 1336 "uart_ao_rx_b"; 1337 function = "uart_ao_b"; 1338 }; 1339 }; 1340 1341 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1342 mux { 1343 groups = "uart_ao_cts_b", 1344 "uart_ao_rts_b"; 1345 function = "uart_ao_b"; 1346 }; 1347 }; 1348 }; 1349 1350 sec_AO: ao-secure@140 { 1351 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1352 reg = <0x0 0x140 0x0 0x140>; 1353 amlogic,has-chip-id; 1354 }; 1355 1356 pwm_AO_cd: pwm@2000 { 1357 compatible = "amlogic,meson-axg-ao-pwm"; 1358 reg = <0x0 0x02000 0x0 0x20>; 1359 #pwm-cells = <3>; 1360 status = "disabled"; 1361 }; 1362 1363 uart_AO: serial@3000 { 1364 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1365 reg = <0x0 0x3000 0x0 0x18>; 1366 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1367 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1368 clock-names = "xtal", "pclk", "baud"; 1369 status = "disabled"; 1370 }; 1371 1372 uart_AO_B: serial@4000 { 1373 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1374 reg = <0x0 0x4000 0x0 0x18>; 1375 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1376 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1377 clock-names = "xtal", "pclk", "baud"; 1378 status = "disabled"; 1379 }; 1380 1381 i2c_AO: i2c@5000 { 1382 compatible = "amlogic,meson-axg-i2c"; 1383 reg = <0x0 0x05000 0x0 0x20>; 1384 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1385 clocks = <&clkc CLKID_AO_I2C>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 pwm_AO_ab: pwm@7000 { 1392 compatible = "amlogic,meson-axg-ao-pwm"; 1393 reg = <0x0 0x07000 0x0 0x20>; 1394 #pwm-cells = <3>; 1395 status = "disabled"; 1396 }; 1397 1398 ir: ir@8000 { 1399 compatible = "amlogic,meson-gxbb-ir"; 1400 reg = <0x0 0x8000 0x0 0x20>; 1401 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1402 status = "disabled"; 1403 }; 1404 1405 saradc: adc@9000 { 1406 compatible = "amlogic,meson-axg-saradc", 1407 "amlogic,meson-saradc"; 1408 reg = <0x0 0x9000 0x0 0x38>; 1409 #io-channel-cells = <1>; 1410 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1411 clocks = <&xtal>, 1412 <&clkc_AO CLKID_AO_SAR_ADC>, 1413 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1414 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1415 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1416 status = "disabled"; 1417 }; 1418 }; 1419 1420 gic: interrupt-controller@ffc01000 { 1421 compatible = "arm,gic-400"; 1422 reg = <0x0 0xffc01000 0 0x1000>, 1423 <0x0 0xffc02000 0 0x2000>, 1424 <0x0 0xffc04000 0 0x2000>, 1425 <0x0 0xffc06000 0 0x2000>; 1426 interrupt-controller; 1427 interrupts = <GIC_PPI 9 1428 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1429 #interrupt-cells = <3>; 1430 #address-cells = <0>; 1431 }; 1432 1433 cbus: bus@ffd00000 { 1434 compatible = "simple-bus"; 1435 reg = <0x0 0xffd00000 0x0 0x25000>; 1436 #address-cells = <2>; 1437 #size-cells = <2>; 1438 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1439 1440 reset: reset-controller@1004 { 1441 compatible = "amlogic,meson-axg-reset"; 1442 reg = <0x0 0x01004 0x0 0x9c>; 1443 #reset-cells = <1>; 1444 }; 1445 1446 gpio_intc: interrupt-controller@f080 { 1447 compatible = "amlogic,meson-gpio-intc"; 1448 reg = <0x0 0xf080 0x0 0x10>; 1449 interrupt-controller; 1450 #interrupt-cells = <2>; 1451 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1452 status = "disabled"; 1453 }; 1454 1455 pwm_ab: pwm@1b000 { 1456 compatible = "amlogic,meson-axg-ee-pwm"; 1457 reg = <0x0 0x1b000 0x0 0x20>; 1458 #pwm-cells = <3>; 1459 status = "disabled"; 1460 }; 1461 1462 pwm_cd: pwm@1a000 { 1463 compatible = "amlogic,meson-axg-ee-pwm"; 1464 reg = <0x0 0x1a000 0x0 0x20>; 1465 #pwm-cells = <3>; 1466 status = "disabled"; 1467 }; 1468 1469 spicc0: spi@13000 { 1470 compatible = "amlogic,meson-axg-spicc"; 1471 reg = <0x0 0x13000 0x0 0x3c>; 1472 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1473 clocks = <&clkc CLKID_SPICC0>; 1474 clock-names = "core"; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 status = "disabled"; 1478 }; 1479 1480 spicc1: spi@15000 { 1481 compatible = "amlogic,meson-axg-spicc"; 1482 reg = <0x0 0x15000 0x0 0x3c>; 1483 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1484 clocks = <&clkc CLKID_SPICC1>; 1485 clock-names = "core"; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 }; 1490 1491 i2c3: i2c@1c000 { 1492 compatible = "amlogic,meson-axg-i2c"; 1493 reg = <0x0 0x1c000 0x0 0x20>; 1494 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1495 clocks = <&clkc CLKID_I2C>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 i2c2: i2c@1d000 { 1502 compatible = "amlogic,meson-axg-i2c"; 1503 reg = <0x0 0x1d000 0x0 0x20>; 1504 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1505 clocks = <&clkc CLKID_I2C>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 status = "disabled"; 1509 }; 1510 1511 i2c1: i2c@1e000 { 1512 compatible = "amlogic,meson-axg-i2c"; 1513 reg = <0x0 0x1e000 0x0 0x20>; 1514 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1515 clocks = <&clkc CLKID_I2C>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 status = "disabled"; 1519 }; 1520 1521 i2c0: i2c@1f000 { 1522 compatible = "amlogic,meson-axg-i2c"; 1523 reg = <0x0 0x1f000 0x0 0x20>; 1524 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1525 clocks = <&clkc CLKID_I2C>; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 status = "disabled"; 1529 }; 1530 1531 uart_B: serial@23000 { 1532 compatible = "amlogic,meson-gx-uart"; 1533 reg = <0x0 0x23000 0x0 0x18>; 1534 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1535 status = "disabled"; 1536 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1537 clock-names = "xtal", "pclk", "baud"; 1538 }; 1539 1540 uart_A: serial@24000 { 1541 compatible = "amlogic,meson-gx-uart"; 1542 reg = <0x0 0x24000 0x0 0x18>; 1543 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1544 status = "disabled"; 1545 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1546 clock-names = "xtal", "pclk", "baud"; 1547 }; 1548 }; 1549 1550 apb: bus@ffe00000 { 1551 compatible = "simple-bus"; 1552 reg = <0x0 0xffe00000 0x0 0x200000>; 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1556 1557 sd_emmc_b: sd@5000 { 1558 compatible = "amlogic,meson-axg-mmc"; 1559 reg = <0x0 0x5000 0x0 0x800>; 1560 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1561 status = "disabled"; 1562 clocks = <&clkc CLKID_SD_EMMC_B>, 1563 <&clkc CLKID_SD_EMMC_B_CLK0>, 1564 <&clkc CLKID_FCLK_DIV2>; 1565 clock-names = "core", "clkin0", "clkin1"; 1566 resets = <&reset RESET_SD_EMMC_B>; 1567 }; 1568 1569 sd_emmc_c: mmc@7000 { 1570 compatible = "amlogic,meson-axg-mmc"; 1571 reg = <0x0 0x7000 0x0 0x800>; 1572 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1573 status = "disabled"; 1574 clocks = <&clkc CLKID_SD_EMMC_C>, 1575 <&clkc CLKID_SD_EMMC_C_CLK0>, 1576 <&clkc CLKID_FCLK_DIV2>; 1577 clock-names = "core", "clkin0", "clkin1"; 1578 resets = <&reset RESET_SD_EMMC_C>; 1579 }; 1580 }; 1581 1582 sram: sram@fffc0000 { 1583 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1584 reg = <0x0 0xfffc0000 0x0 0x20000>; 1585 #address-cells = <1>; 1586 #size-cells = <1>; 1587 ranges = <0 0x0 0xfffc0000 0x20000>; 1588 1589 cpu_scp_lpri: scp-shmem@13000 { 1590 compatible = "amlogic,meson-axg-scp-shmem"; 1591 reg = <0x13000 0x400>; 1592 }; 1593 1594 cpu_scp_hpri: scp-shmem@13400 { 1595 compatible = "amlogic,meson-axg-scp-shmem"; 1596 reg = <0x13400 0x400>; 1597 }; 1598 }; 1599 }; 1600 1601 timer { 1602 compatible = "arm,armv8-timer"; 1603 interrupts = <GIC_PPI 13 1604 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1605 <GIC_PPI 14 1606 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1607 <GIC_PPI 11 1608 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1609 <GIC_PPI 10 1610 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1611 }; 1612 1613 xtal: xtal-clk { 1614 compatible = "fixed-clock"; 1615 clock-frequency = <24000000>; 1616 clock-output-names = "xtal"; 1617 #clock-cells = <0>; 1618 }; 1619}; 1620