1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-clkc.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		apb: apb@ffe00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffe00000 0x0 0x200000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
123
124			sd_emmc_b: sd@5000 {
125				compatible = "amlogic,meson-axg-mmc";
126				reg = <0x0 0x5000 0x0 0x2000>;
127				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
128				status = "disabled";
129				clocks = <&clkc CLKID_SD_EMMC_B>,
130					<&clkc CLKID_SD_EMMC_B_CLK0>,
131					<&clkc CLKID_FCLK_DIV2>;
132				clock-names = "core", "clkin0", "clkin1";
133			};
134
135			sd_emmc_c: mmc@7000 {
136				compatible = "amlogic,meson-axg-mmc";
137				reg = <0x0 0x7000 0x0 0x2000>;
138				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
139				status = "disabled";
140				clocks = <&clkc CLKID_SD_EMMC_C>,
141					<&clkc CLKID_SD_EMMC_C_CLK0>,
142					<&clkc CLKID_FCLK_DIV2>;
143				clock-names = "core", "clkin0", "clkin1";
144			};
145		};
146
147		cbus: bus@ffd00000 {
148			compatible = "simple-bus";
149			reg = <0x0 0xffd00000 0x0 0x25000>;
150			#address-cells = <2>;
151			#size-cells = <2>;
152			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
153
154			pwm_ab: pwm@1b000 {
155				compatible = "amlogic,meson-axg-ee-pwm";
156				reg = <0x0 0x1b000 0x0 0x20>;
157				#pwm-cells = <3>;
158				status = "disabled";
159			};
160
161			pwm_cd: pwm@1a000 {
162				compatible = "amlogic,meson-axg-ee-pwm";
163				reg = <0x0 0x1a000 0x0 0x20>;
164				#pwm-cells = <3>;
165				status = "disabled";
166			};
167
168			reset: reset-controller@1004 {
169				compatible = "amlogic,meson-axg-reset";
170				reg = <0x0 0x01004 0x0 0x9c>;
171				#reset-cells = <1>;
172			};
173
174			spicc0: spi@13000 {
175				compatible = "amlogic,meson-axg-spicc";
176				reg = <0x0 0x13000 0x0 0x3c>;
177				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
178				clocks = <&clkc CLKID_SPICC0>;
179				clock-names = "core";
180				#address-cells = <1>;
181				#size-cells = <0>;
182				status = "disabled";
183			};
184
185			spicc1: spi@15000 {
186				compatible = "amlogic,meson-axg-spicc";
187				reg = <0x0 0x15000 0x0 0x3c>;
188				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
189				clocks = <&clkc CLKID_SPICC1>;
190				clock-names = "core";
191				#address-cells = <1>;
192				#size-cells = <0>;
193				status = "disabled";
194			};
195
196			i2c0: i2c@1f000 {
197				compatible = "amlogic,meson-axg-i2c";
198				status = "disabled";
199				reg = <0x0 0x1f000 0x0 0x20>;
200				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
201					<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
202				#address-cells = <1>;
203				#size-cells = <0>;
204				clocks = <&clkc CLKID_I2C>;
205				clock-names = "clk_i2c";
206			};
207
208			i2c1: i2c@1e000 {
209				compatible = "amlogic,meson-axg-i2c";
210				#address-cells = <1>;
211				#size-cells = <0>;
212				reg = <0x0 0x1e000 0x0 0x20>;
213				status = "disabled";
214				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
215					<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
216				clocks = <&clkc CLKID_I2C>;
217				clock-names = "clk_i2c";
218			};
219
220			i2c2: i2c@1d000 {
221				compatible = "amlogic,meson-axg-i2c";
222				status = "disabled";
223				reg = <0x0 0x1d000 0x0 0x20>;
224				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
225					<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
226				#address-cells = <1>;
227				#size-cells = <0>;
228				clocks = <&clkc CLKID_I2C>;
229				clock-names = "clk_i2c";
230			};
231
232			i2c3: i2c@1c000 {
233				compatible = "amlogic,meson-axg-i2c";
234				status = "disabled";
235				reg = <0x0 0x1c000 0x0 0x20>;
236				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
237					<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
238				#address-cells = <1>;
239				#size-cells = <0>;
240				clocks = <&clkc CLKID_I2C>;
241				clock-names = "clk_i2c";
242			};
243
244			uart_A: serial@24000 {
245				compatible = "amlogic,meson-gx-uart";
246				reg = <0x0 0x24000 0x0 0x18>;
247				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
248				status = "disabled";
249				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
250				clock-names = "xtal", "pclk", "baud";
251			};
252
253			uart_B: serial@23000 {
254				compatible = "amlogic,meson-gx-uart";
255				reg = <0x0 0x23000 0x0 0x18>;
256				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
257				status = "disabled";
258				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
259				clock-names = "xtal", "pclk", "baud";
260			};
261		};
262
263		ethmac: ethernet@ff3f0000 {
264			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
265			reg = <0x0 0xff3f0000 0x0 0x10000
266				0x0 0xff634540 0x0 0x8>;
267			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
268			interrupt-names = "macirq";
269			clocks = <&clkc CLKID_ETH>,
270				 <&clkc CLKID_FCLK_DIV2>,
271				 <&clkc CLKID_MPLL2>;
272			clock-names = "stmmaceth", "clkin0", "clkin1";
273			status = "disabled";
274		};
275
276		gic: interrupt-controller@ffc01000 {
277			compatible = "arm,gic-400";
278			reg = <0x0 0xffc01000 0 0x1000>,
279			      <0x0 0xffc02000 0 0x2000>,
280			      <0x0 0xffc04000 0 0x2000>,
281			      <0x0 0xffc06000 0 0x2000>;
282			interrupt-controller;
283			interrupts = <GIC_PPI 9
284				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
285			#interrupt-cells = <3>;
286			#address-cells = <0>;
287		};
288
289		hiubus: bus@ff63c000 {
290			compatible = "simple-bus";
291			reg = <0x0 0xff63c000 0x0 0x1c00>;
292			#address-cells = <2>;
293			#size-cells = <2>;
294			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
295
296			sysctrl: system-controller@0 {
297				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
298				reg = <0 0 0 0x400>;
299
300				clkc: clock-controller {
301					compatible = "amlogic,axg-clkc";
302					#clock-cells = <1>;
303				};
304			};
305		};
306
307		mailbox: mailbox@ff63dc00 {
308			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
309			reg = <0 0xff63dc00 0 0x400>;
310			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
311				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
312				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
313			#mbox-cells = <1>;
314		};
315
316		periphs: periphs@ff634000 {
317			compatible = "simple-bus";
318			reg = <0x0 0xff634000 0x0 0x2000>;
319			#address-cells = <2>;
320			#size-cells = <2>;
321			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
322
323			hwrng: rng {
324				compatible = "amlogic,meson-rng";
325				reg = <0x0 0x18 0x0 0x4>;
326				clocks = <&clkc CLKID_RNG0>;
327				clock-names = "core";
328			};
329
330			pinctrl_periphs: pinctrl@480 {
331				compatible = "amlogic,meson-axg-periphs-pinctrl";
332				#address-cells = <2>;
333				#size-cells = <2>;
334				ranges;
335
336				gpio: bank@480 {
337					reg = <0x0 0x00480 0x0 0x40>,
338						<0x0 0x004e8 0x0 0x14>,
339						<0x0 0x00520 0x0 0x14>,
340						<0x0 0x00430 0x0 0x3c>;
341					reg-names = "mux", "pull", "pull-enable", "gpio";
342					gpio-controller;
343					#gpio-cells = <2>;
344					gpio-ranges = <&pinctrl_periphs 0 0 86>;
345				};
346
347				emmc_pins: emmc {
348					mux {
349						groups = "emmc_nand_d0",
350							"emmc_nand_d1",
351							"emmc_nand_d2",
352							"emmc_nand_d3",
353							"emmc_nand_d4",
354							"emmc_nand_d5",
355							"emmc_nand_d6",
356							"emmc_nand_d7",
357							"emmc_clk",
358							"emmc_cmd",
359							"emmc_ds";
360						function = "emmc";
361					};
362				};
363
364				emmc_clk_gate_pins: emmc_clk_gate {
365					mux {
366						groups = "BOOT_8";
367						function = "gpio_periphs";
368					};
369					cfg-pull-down {
370						pins = "BOOT_8";
371						bias-pull-down;
372					};
373				};
374
375				sdio_pins: sdio {
376					mux {
377						groups = "sdio_d0",
378							"sdio_d1",
379							"sdio_d2",
380							"sdio_d3",
381							"sdio_cmd",
382							"sdio_clk";
383						function = "sdio";
384					};
385				};
386
387				sdio_clk_gate_pins: sdio_clk_gate {
388					mux {
389						groups = "GPIOX_4";
390						function = "gpio_periphs";
391					};
392					cfg-pull-down {
393						pins = "GPIOX_4";
394						bias-pull-down;
395					};
396				};
397
398				eth_rmii_x_pins: eth-x-rmii {
399					mux {
400						groups = "eth_mdio_x",
401						       "eth_mdc_x",
402						       "eth_rgmii_rx_clk_x",
403						       "eth_rx_dv_x",
404						       "eth_rxd0_x",
405						       "eth_rxd1_x",
406						       "eth_txen_x",
407						       "eth_txd0_x",
408						       "eth_txd1_x";
409						function = "eth";
410					};
411				};
412
413				eth_rmii_y_pins: eth-y-rmii {
414					mux {
415						groups = "eth_mdio_y",
416						       "eth_mdc_y",
417						       "eth_rgmii_rx_clk_y",
418						       "eth_rx_dv_y",
419						       "eth_rxd0_y",
420						       "eth_rxd1_y",
421						       "eth_txen_y",
422						       "eth_txd0_y",
423						       "eth_txd1_y";
424						function = "eth";
425					};
426				};
427
428				eth_rgmii_x_pins: eth-x-rgmii {
429					mux {
430						groups = "eth_mdio_x",
431						       "eth_mdc_x",
432						       "eth_rgmii_rx_clk_x",
433						       "eth_rx_dv_x",
434						       "eth_rxd0_x",
435						       "eth_rxd1_x",
436						       "eth_rxd2_rgmii",
437						       "eth_rxd3_rgmii",
438						       "eth_rgmii_tx_clk",
439						       "eth_txen_x",
440						       "eth_txd0_x",
441						       "eth_txd1_x",
442						       "eth_txd2_rgmii",
443						       "eth_txd3_rgmii";
444						function = "eth";
445					};
446				};
447
448				eth_rgmii_y_pins: eth-y-rgmii {
449					mux {
450						groups = "eth_mdio_y",
451						       "eth_mdc_y",
452						       "eth_rgmii_rx_clk_y",
453						       "eth_rx_dv_y",
454						       "eth_rxd0_y",
455						       "eth_rxd1_y",
456						       "eth_rxd2_rgmii",
457						       "eth_rxd3_rgmii",
458						       "eth_rgmii_tx_clk",
459						       "eth_txen_y",
460						       "eth_txd0_y",
461						       "eth_txd1_y",
462						       "eth_txd2_rgmii",
463						       "eth_txd3_rgmii";
464						function = "eth";
465					};
466				};
467
468				pwm_a_a_pins: pwm_a_a {
469					mux {
470						groups = "pwm_a_a";
471						function = "pwm_a";
472					};
473				};
474
475				pwm_a_x18_pins: pwm_a_x18 {
476					mux {
477						groups = "pwm_a_x18";
478						function = "pwm_a";
479					};
480				};
481
482				pwm_a_x20_pins: pwm_a_x20 {
483					mux {
484						groups = "pwm_a_x20";
485						function = "pwm_a";
486					};
487				};
488
489				pwm_a_z_pins: pwm_a_z {
490					mux {
491						groups = "pwm_a_z";
492						function = "pwm_a";
493					};
494				};
495
496				pwm_b_a_pins: pwm_b_a {
497					mux {
498						groups = "pwm_b_a";
499						function = "pwm_b";
500					};
501				};
502
503				pwm_b_x_pins: pwm_b_x {
504					mux {
505						groups = "pwm_b_x";
506						function = "pwm_b";
507					};
508				};
509
510				pwm_b_z_pins: pwm_b_z {
511					mux {
512						groups = "pwm_b_z";
513						function = "pwm_b";
514					};
515				};
516
517				pwm_c_a_pins: pwm_c_a {
518					mux {
519						groups = "pwm_c_a";
520						function = "pwm_c";
521					};
522				};
523
524				pwm_c_x10_pins: pwm_c_x10 {
525					mux {
526						groups = "pwm_c_x10";
527						function = "pwm_c";
528					};
529				};
530
531				pwm_c_x17_pins: pwm_c_x17 {
532					mux {
533						groups = "pwm_c_x17";
534						function = "pwm_c";
535					};
536				};
537
538				pwm_d_x11_pins: pwm_d_x11 {
539					mux {
540						groups = "pwm_d_x11";
541						function = "pwm_d";
542					};
543				};
544
545				pwm_d_x16_pins: pwm_d_x16 {
546					mux {
547						groups = "pwm_d_x16";
548						function = "pwm_d";
549					};
550				};
551
552				spi0_pins: spi0 {
553					mux {
554						groups = "spi0_miso",
555							"spi0_mosi",
556							"spi0_clk";
557						function = "spi0";
558					};
559				};
560
561				spi0_ss0_pins: spi0_ss0 {
562					mux {
563						groups = "spi0_ss0";
564						function = "spi0";
565					};
566				};
567
568				spi0_ss1_pins: spi0_ss1 {
569					mux {
570						groups = "spi0_ss1";
571						function = "spi0";
572					};
573				};
574
575				spi0_ss2_pins: spi0_ss2 {
576					mux {
577						groups = "spi0_ss2";
578						function = "spi0";
579					};
580				};
581
582
583				spi1_a_pins: spi1_a {
584					mux {
585						groups = "spi1_miso_a",
586							"spi1_mosi_a",
587							"spi1_clk_a";
588						function = "spi1";
589					};
590				};
591
592				spi1_ss0_a_pins: spi1_ss0_a {
593					mux {
594						groups = "spi1_ss0_a";
595						function = "spi1";
596					};
597				};
598
599				spi1_ss1_pins: spi1_ss1 {
600					mux {
601						groups = "spi1_ss1";
602						function = "spi1";
603					};
604				};
605
606				spi1_x_pins: spi1_x {
607					mux {
608						groups = "spi1_miso_x",
609							"spi1_mosi_x",
610							"spi1_clk_x";
611						function = "spi1";
612					};
613				};
614
615				spi1_ss0_x_pins: spi1_ss0_x {
616					mux {
617						groups = "spi1_ss0_x";
618						function = "spi1";
619					};
620				};
621
622				i2c0_pins: i2c0 {
623					mux {
624						groups = "i2c0_sck",
625							"i2c0_sda";
626						function = "i2c0";
627					};
628				};
629
630				i2c1_z_pins: i2c1_z {
631					mux {
632						groups = "i2c1_sck_z",
633							"i2c1_sda_z";
634						function = "i2c1";
635					};
636				};
637
638				i2c1_x_pins: i2c1_x {
639					mux {
640						groups = "i2c1_sck_x",
641							"i2c1_sda_x";
642						function = "i2c1";
643					};
644				};
645
646				i2c2_x_pins: i2c2_x {
647					mux {
648						groups = "i2c2_sck_x",
649							"i2c2_sda_x";
650						function = "i2c2";
651					};
652				};
653
654				i2c2_a_pins: i2c2_a {
655					mux {
656						groups = "i2c2_sck_a",
657							"i2c2_sda_a";
658						function = "i2c2";
659					};
660				};
661
662				i2c3_a6_pins: i2c3_a6 {
663					mux {
664						groups = "i2c3_sda_a6",
665							"i2c3_sck_a7";
666						function = "i2c3";
667					};
668				};
669
670				i2c3_a12_pins: i2c3_a12 {
671					mux {
672						groups = "i2c3_sda_a12",
673							"i2c3_sck_a13";
674						function = "i2c3";
675					};
676				};
677
678				i2c3_a19_pins: i2c3_a19 {
679					mux {
680						groups = "i2c3_sda_a19",
681							"i2c3_sck_a20";
682						function = "i2c3";
683					};
684				};
685
686				uart_a_pins: uart_a {
687					mux {
688						groups = "uart_tx_a",
689							"uart_rx_a";
690						function = "uart_a";
691					};
692				};
693
694				uart_a_cts_rts_pins: uart_a_cts_rts {
695					mux {
696						groups = "uart_cts_a",
697							"uart_rts_a";
698						function = "uart_a";
699					};
700				};
701
702				uart_b_x_pins: uart_b_x {
703					mux {
704						groups = "uart_tx_b_x",
705							"uart_rx_b_x";
706						function = "uart_b";
707					};
708				};
709
710				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
711					mux {
712						groups = "uart_cts_b_x",
713							"uart_rts_b_x";
714						function = "uart_b";
715					};
716				};
717
718				uart_b_z_pins: uart_b_z {
719					mux {
720						groups = "uart_tx_b_z",
721							"uart_rx_b_z";
722						function = "uart_b";
723					};
724				};
725
726				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
727					mux {
728						groups = "uart_cts_b_z",
729							"uart_rts_b_z";
730						function = "uart_b";
731					};
732				};
733
734				uart_ao_b_z_pins: uart_ao_b_z {
735					mux {
736						groups = "uart_ao_tx_b_z",
737							"uart_ao_rx_b_z";
738						function = "uart_ao_b_z";
739					};
740				};
741
742				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
743					mux {
744						groups = "uart_ao_cts_b_z",
745							"uart_ao_rts_b_z";
746						function = "uart_ao_b_z";
747					};
748				};
749			};
750		};
751
752		sram: sram@fffc0000 {
753			compatible = "amlogic,meson-axg-sram", "mmio-sram";
754			reg = <0x0 0xfffc0000 0x0 0x20000>;
755			#address-cells = <1>;
756			#size-cells = <1>;
757			ranges = <0 0x0 0xfffc0000 0x20000>;
758
759			cpu_scp_lpri: scp-shmem@0 {
760				compatible = "amlogic,meson-axg-scp-shmem";
761				reg = <0x13000 0x400>;
762			};
763
764			cpu_scp_hpri: scp-shmem@200 {
765				compatible = "amlogic,meson-axg-scp-shmem";
766				reg = <0x13400 0x400>;
767			};
768		};
769
770		aobus: bus@ff800000 {
771			compatible = "simple-bus";
772			reg = <0x0 0xff800000 0x0 0x100000>;
773			#address-cells = <2>;
774			#size-cells = <2>;
775			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
776
777			pinctrl_aobus: pinctrl@14 {
778				compatible = "amlogic,meson-axg-aobus-pinctrl";
779				#address-cells = <2>;
780				#size-cells = <2>;
781				ranges;
782
783				gpio_ao: bank@14 {
784					reg = <0x0 0x00014 0x0 0x8>,
785						<0x0 0x0002c 0x0 0x4>,
786						<0x0 0x00024 0x0 0x8>;
787					reg-names = "mux", "pull", "gpio";
788					gpio-controller;
789					#gpio-cells = <2>;
790					gpio-ranges = <&pinctrl_aobus 0 0 15>;
791				};
792
793				remote_input_ao_pins: remote_input_ao {
794					mux {
795						groups = "remote_input_ao";
796						function = "remote_input_ao";
797					};
798				};
799
800				uart_ao_a_pins: uart_ao_a {
801					mux {
802						groups = "uart_ao_tx_a",
803							"uart_ao_rx_a";
804						function = "uart_ao_a";
805					};
806				};
807
808				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
809					mux {
810						groups = "uart_ao_cts_a",
811							"uart_ao_rts_a";
812						function = "uart_ao_a";
813					};
814				};
815
816				uart_ao_b_pins: uart_ao_b {
817					mux {
818						groups = "uart_ao_tx_b",
819							"uart_ao_rx_b";
820						function = "uart_ao_b";
821					};
822				};
823
824				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
825					mux {
826						groups = "uart_ao_cts_b",
827							"uart_ao_rts_b";
828						function = "uart_ao_b";
829					};
830				};
831			};
832
833			sec_AO: ao-secure@140 {
834				compatible = "amlogic,meson-gx-ao-secure", "syscon";
835				reg = <0x0 0x140 0x0 0x140>;
836				amlogic,has-chip-id;
837			};
838
839			pwm_AO_ab: pwm@7000 {
840				compatible = "amlogic,meson-axg-ao-pwm";
841				reg = <0x0 0x07000 0x0 0x20>;
842				#pwm-cells = <3>;
843				status = "disabled";
844			};
845
846			pwm_AO_cd: pwm@2000 {
847				compatible = "amlogic,meson-axg-ao-pwm";
848				reg = <0x0 0x02000  0x0 0x20>;
849				#pwm-cells = <3>;
850				status = "disabled";
851			};
852
853			i2c_AO: i2c@5000 {
854				compatible = "amlogic,meson-axg-i2c";
855				status = "disabled";
856				reg = <0x0 0x05000 0x0 0x20>;
857				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
858				#address-cells = <1>;
859				#size-cells = <0>;
860				clocks = <&clkc CLKID_I2C>;
861				clock-names = "clk_i2c";
862			};
863
864			uart_AO: serial@3000 {
865				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
866				reg = <0x0 0x3000 0x0 0x18>;
867				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
868				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
869				clock-names = "xtal", "pclk", "baud";
870				status = "disabled";
871			};
872
873			uart_AO_B: serial@4000 {
874				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
875				reg = <0x0 0x4000 0x0 0x18>;
876				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
877				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
878				clock-names = "xtal", "pclk", "baud";
879				status = "disabled";
880			};
881
882			ir: ir@8000 {
883				compatible = "amlogic,meson-gxbb-ir";
884				reg = <0x0 0x8000 0x0 0x20>;
885				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
886				status = "disabled";
887			};
888		};
889	};
890};
891