1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 63 }; 64 65 cpus { 66 #address-cells = <0x2>; 67 #size-cells = <0x0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x1>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&l2>; 102 clocks = <&scpi_dvfs 0>; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 }; 108 }; 109 110 sm: secure-monitor { 111 compatible = "amlogic,meson-gxbb-sm"; 112 }; 113 114 efuse: efuse { 115 compatible = "amlogic,meson-gxbb-efuse"; 116 clocks = <&clkc CLKID_EFUSE>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 read-only; 120 secure-monitor = <&sm>; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 reserved-memory { 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 /* 16 MiB reserved for Hardware ROM Firmware */ 134 hwrom_reserved: hwrom@0 { 135 reg = <0x0 0x0 0x0 0x1000000>; 136 no-map; 137 }; 138 139 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 140 secmon_reserved: secmon@5000000 { 141 reg = <0x0 0x05000000 0x0 0x300000>; 142 no-map; 143 }; 144 }; 145 146 scpi { 147 compatible = "arm,scpi-pre-1.0"; 148 mboxes = <&mailbox 1 &mailbox 2>; 149 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 150 151 scpi_clocks: clocks { 152 compatible = "arm,scpi-clocks"; 153 154 scpi_dvfs: clock-controller { 155 compatible = "arm,scpi-dvfs-clocks"; 156 #clock-cells = <1>; 157 clock-indices = <0>; 158 clock-output-names = "vcpu"; 159 }; 160 }; 161 162 scpi_sensors: sensors { 163 compatible = "amlogic,meson-gxbb-scpi-sensors"; 164 #thermal-sensor-cells = <1>; 165 }; 166 }; 167 168 soc { 169 compatible = "simple-bus"; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 usb: usb@ffe09080 { 175 compatible = "amlogic,meson-axg-usb-ctrl"; 176 reg = <0x0 0xffe09080 0x0 0x20>; 177 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges; 181 182 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; 183 clock-names = "usb_ctrl", "ddr"; 184 resets = <&reset RESET_USB_OTG>; 185 186 dr_mode = "otg"; 187 188 phys = <&usb2_phy1>; 189 phy-names = "usb2-phy1"; 190 191 dwc2: usb@ff400000 { 192 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 193 reg = <0x0 0xff400000 0x0 0x40000>; 194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&clkc CLKID_USB1>; 196 clock-names = "otg"; 197 phys = <&usb2_phy1>; 198 dr_mode = "peripheral"; 199 g-rx-fifo-size = <192>; 200 g-np-tx-fifo-size = <128>; 201 g-tx-fifo-size = <128 128 16 16 16>; 202 }; 203 204 dwc3: usb@ff500000 { 205 compatible = "snps,dwc3"; 206 reg = <0x0 0xff500000 0x0 0x100000>; 207 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 208 dr_mode = "host"; 209 maximum-speed = "high-speed"; 210 snps,dis_u2_susphy_quirk; 211 }; 212 }; 213 214 ethmac: ethernet@ff3f0000 { 215 compatible = "amlogic,meson-axg-dwmac", 216 "snps,dwmac-3.70a", 217 "snps,dwmac"; 218 reg = <0x0 0xff3f0000 0x0 0x10000>, 219 <0x0 0xff634540 0x0 0x8>; 220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-names = "macirq"; 222 clocks = <&clkc CLKID_ETH>, 223 <&clkc CLKID_FCLK_DIV2>, 224 <&clkc CLKID_MPLL2>, 225 <&clkc CLKID_FCLK_DIV2>; 226 clock-names = "stmmaceth", "clkin0", "clkin1", 227 "timing-adjustment"; 228 rx-fifo-depth = <4096>; 229 tx-fifo-depth = <2048>; 230 status = "disabled"; 231 }; 232 233 pdm: audio-controller@ff632000 { 234 compatible = "amlogic,axg-pdm"; 235 reg = <0x0 0xff632000 0x0 0x34>; 236 #sound-dai-cells = <0>; 237 sound-name-prefix = "PDM"; 238 clocks = <&clkc_audio AUD_CLKID_PDM>, 239 <&clkc_audio AUD_CLKID_PDM_DCLK>, 240 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 241 clock-names = "pclk", "dclk", "sysclk"; 242 status = "disabled"; 243 }; 244 245 periphs: bus@ff634000 { 246 compatible = "simple-bus"; 247 reg = <0x0 0xff634000 0x0 0x2000>; 248 #address-cells = <2>; 249 #size-cells = <2>; 250 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 251 252 hwrng: rng@18 { 253 compatible = "amlogic,meson-rng"; 254 reg = <0x0 0x18 0x0 0x4>; 255 clocks = <&clkc CLKID_RNG0>; 256 clock-names = "core"; 257 }; 258 259 pinctrl_periphs: pinctrl@480 { 260 compatible = "amlogic,meson-axg-periphs-pinctrl"; 261 #address-cells = <2>; 262 #size-cells = <2>; 263 ranges; 264 265 gpio: bank@480 { 266 reg = <0x0 0x00480 0x0 0x40>, 267 <0x0 0x004e8 0x0 0x14>, 268 <0x0 0x00520 0x0 0x14>, 269 <0x0 0x00430 0x0 0x3c>; 270 reg-names = "mux", "pull", "pull-enable", "gpio"; 271 gpio-controller; 272 #gpio-cells = <2>; 273 gpio-ranges = <&pinctrl_periphs 0 0 86>; 274 }; 275 276 i2c0_pins: i2c0 { 277 mux { 278 groups = "i2c0_sck", 279 "i2c0_sda"; 280 function = "i2c0"; 281 bias-disable; 282 }; 283 }; 284 285 i2c1_x_pins: i2c1_x { 286 mux { 287 groups = "i2c1_sck_x", 288 "i2c1_sda_x"; 289 function = "i2c1"; 290 bias-disable; 291 }; 292 }; 293 294 i2c1_z_pins: i2c1_z { 295 mux { 296 groups = "i2c1_sck_z", 297 "i2c1_sda_z"; 298 function = "i2c1"; 299 bias-disable; 300 }; 301 }; 302 303 i2c2_a_pins: i2c2_a { 304 mux { 305 groups = "i2c2_sck_a", 306 "i2c2_sda_a"; 307 function = "i2c2"; 308 bias-disable; 309 }; 310 }; 311 312 i2c2_x_pins: i2c2_x { 313 mux { 314 groups = "i2c2_sck_x", 315 "i2c2_sda_x"; 316 function = "i2c2"; 317 bias-disable; 318 }; 319 }; 320 321 i2c3_a6_pins: i2c3_a6 { 322 mux { 323 groups = "i2c3_sda_a6", 324 "i2c3_sck_a7"; 325 function = "i2c3"; 326 bias-disable; 327 }; 328 }; 329 330 i2c3_a12_pins: i2c3_a12 { 331 mux { 332 groups = "i2c3_sda_a12", 333 "i2c3_sck_a13"; 334 function = "i2c3"; 335 bias-disable; 336 }; 337 }; 338 339 i2c3_a19_pins: i2c3_a19 { 340 mux { 341 groups = "i2c3_sda_a19", 342 "i2c3_sck_a20"; 343 function = "i2c3"; 344 bias-disable; 345 }; 346 }; 347 348 emmc_pins: emmc { 349 mux-0 { 350 groups = "emmc_nand_d0", 351 "emmc_nand_d1", 352 "emmc_nand_d2", 353 "emmc_nand_d3", 354 "emmc_nand_d4", 355 "emmc_nand_d5", 356 "emmc_nand_d6", 357 "emmc_nand_d7", 358 "emmc_cmd"; 359 function = "emmc"; 360 bias-pull-up; 361 }; 362 363 mux-1 { 364 groups = "emmc_clk"; 365 function = "emmc"; 366 bias-disable; 367 }; 368 }; 369 370 emmc_ds_pins: emmc_ds { 371 mux { 372 groups = "emmc_ds"; 373 function = "emmc"; 374 bias-pull-down; 375 }; 376 }; 377 378 emmc_clk_gate_pins: emmc_clk_gate { 379 mux { 380 groups = "BOOT_8"; 381 function = "gpio_periphs"; 382 bias-pull-down; 383 }; 384 }; 385 386 eth_rgmii_x_pins: eth-x-rgmii { 387 mux { 388 groups = "eth_mdio_x", 389 "eth_mdc_x", 390 "eth_rgmii_rx_clk_x", 391 "eth_rx_dv_x", 392 "eth_rxd0_x", 393 "eth_rxd1_x", 394 "eth_rxd2_rgmii", 395 "eth_rxd3_rgmii", 396 "eth_rgmii_tx_clk", 397 "eth_txen_x", 398 "eth_txd0_x", 399 "eth_txd1_x", 400 "eth_txd2_rgmii", 401 "eth_txd3_rgmii"; 402 function = "eth"; 403 bias-disable; 404 }; 405 }; 406 407 eth_rgmii_y_pins: eth-y-rgmii { 408 mux { 409 groups = "eth_mdio_y", 410 "eth_mdc_y", 411 "eth_rgmii_rx_clk_y", 412 "eth_rx_dv_y", 413 "eth_rxd0_y", 414 "eth_rxd1_y", 415 "eth_rxd2_rgmii", 416 "eth_rxd3_rgmii", 417 "eth_rgmii_tx_clk", 418 "eth_txen_y", 419 "eth_txd0_y", 420 "eth_txd1_y", 421 "eth_txd2_rgmii", 422 "eth_txd3_rgmii"; 423 function = "eth"; 424 bias-disable; 425 }; 426 }; 427 428 eth_rmii_x_pins: eth-x-rmii { 429 mux { 430 groups = "eth_mdio_x", 431 "eth_mdc_x", 432 "eth_rgmii_rx_clk_x", 433 "eth_rx_dv_x", 434 "eth_rxd0_x", 435 "eth_rxd1_x", 436 "eth_txen_x", 437 "eth_txd0_x", 438 "eth_txd1_x"; 439 function = "eth"; 440 bias-disable; 441 }; 442 }; 443 444 eth_rmii_y_pins: eth-y-rmii { 445 mux { 446 groups = "eth_mdio_y", 447 "eth_mdc_y", 448 "eth_rgmii_rx_clk_y", 449 "eth_rx_dv_y", 450 "eth_rxd0_y", 451 "eth_rxd1_y", 452 "eth_txen_y", 453 "eth_txd0_y", 454 "eth_txd1_y"; 455 function = "eth"; 456 bias-disable; 457 }; 458 }; 459 460 mclk_b_pins: mclk_b { 461 mux { 462 groups = "mclk_b"; 463 function = "mclk_b"; 464 bias-disable; 465 }; 466 }; 467 468 mclk_c_pins: mclk_c { 469 mux { 470 groups = "mclk_c"; 471 function = "mclk_c"; 472 bias-disable; 473 }; 474 }; 475 476 pdm_dclk_a14_pins: pdm_dclk_a14 { 477 mux { 478 groups = "pdm_dclk_a14"; 479 function = "pdm"; 480 bias-disable; 481 }; 482 }; 483 484 pdm_dclk_a19_pins: pdm_dclk_a19 { 485 mux { 486 groups = "pdm_dclk_a19"; 487 function = "pdm"; 488 bias-disable; 489 }; 490 }; 491 492 pdm_din0_pins: pdm_din0 { 493 mux { 494 groups = "pdm_din0"; 495 function = "pdm"; 496 bias-disable; 497 }; 498 }; 499 500 pdm_din1_pins: pdm_din1 { 501 mux { 502 groups = "pdm_din1"; 503 function = "pdm"; 504 bias-disable; 505 }; 506 }; 507 508 pdm_din2_pins: pdm_din2 { 509 mux { 510 groups = "pdm_din2"; 511 function = "pdm"; 512 bias-disable; 513 }; 514 }; 515 516 pdm_din3_pins: pdm_din3 { 517 mux { 518 groups = "pdm_din3"; 519 function = "pdm"; 520 bias-disable; 521 }; 522 }; 523 524 pwm_a_a_pins: pwm_a_a { 525 mux { 526 groups = "pwm_a_a"; 527 function = "pwm_a"; 528 bias-disable; 529 }; 530 }; 531 532 pwm_a_x18_pins: pwm_a_x18 { 533 mux { 534 groups = "pwm_a_x18"; 535 function = "pwm_a"; 536 bias-disable; 537 }; 538 }; 539 540 pwm_a_x20_pins: pwm_a_x20 { 541 mux { 542 groups = "pwm_a_x20"; 543 function = "pwm_a"; 544 bias-disable; 545 }; 546 }; 547 548 pwm_a_z_pins: pwm_a_z { 549 mux { 550 groups = "pwm_a_z"; 551 function = "pwm_a"; 552 bias-disable; 553 }; 554 }; 555 556 pwm_b_a_pins: pwm_b_a { 557 mux { 558 groups = "pwm_b_a"; 559 function = "pwm_b"; 560 bias-disable; 561 }; 562 }; 563 564 pwm_b_x_pins: pwm_b_x { 565 mux { 566 groups = "pwm_b_x"; 567 function = "pwm_b"; 568 bias-disable; 569 }; 570 }; 571 572 pwm_b_z_pins: pwm_b_z { 573 mux { 574 groups = "pwm_b_z"; 575 function = "pwm_b"; 576 bias-disable; 577 }; 578 }; 579 580 pwm_c_a_pins: pwm_c_a { 581 mux { 582 groups = "pwm_c_a"; 583 function = "pwm_c"; 584 bias-disable; 585 }; 586 }; 587 588 pwm_c_x10_pins: pwm_c_x10 { 589 mux { 590 groups = "pwm_c_x10"; 591 function = "pwm_c"; 592 bias-disable; 593 }; 594 }; 595 596 pwm_c_x17_pins: pwm_c_x17 { 597 mux { 598 groups = "pwm_c_x17"; 599 function = "pwm_c"; 600 bias-disable; 601 }; 602 }; 603 604 pwm_d_x11_pins: pwm_d_x11 { 605 mux { 606 groups = "pwm_d_x11"; 607 function = "pwm_d"; 608 bias-disable; 609 }; 610 }; 611 612 pwm_d_x16_pins: pwm_d_x16 { 613 mux { 614 groups = "pwm_d_x16"; 615 function = "pwm_d"; 616 bias-disable; 617 }; 618 }; 619 620 sdio_pins: sdio { 621 mux-0 { 622 groups = "sdio_d0", 623 "sdio_d1", 624 "sdio_d2", 625 "sdio_d3", 626 "sdio_cmd"; 627 function = "sdio"; 628 bias-pull-up; 629 }; 630 631 mux-1 { 632 groups = "sdio_clk"; 633 function = "sdio"; 634 bias-disable; 635 }; 636 }; 637 638 sdio_clk_gate_pins: sdio_clk_gate { 639 mux { 640 groups = "GPIOX_4"; 641 function = "gpio_periphs"; 642 bias-pull-down; 643 }; 644 }; 645 646 spdif_in_z_pins: spdif_in_z { 647 mux { 648 groups = "spdif_in_z"; 649 function = "spdif_in"; 650 bias-disable; 651 }; 652 }; 653 654 spdif_in_a1_pins: spdif_in_a1 { 655 mux { 656 groups = "spdif_in_a1"; 657 function = "spdif_in"; 658 bias-disable; 659 }; 660 }; 661 662 spdif_in_a7_pins: spdif_in_a7 { 663 mux { 664 groups = "spdif_in_a7"; 665 function = "spdif_in"; 666 bias-disable; 667 }; 668 }; 669 670 spdif_in_a19_pins: spdif_in_a19 { 671 mux { 672 groups = "spdif_in_a19"; 673 function = "spdif_in"; 674 bias-disable; 675 }; 676 }; 677 678 spdif_in_a20_pins: spdif_in_a20 { 679 mux { 680 groups = "spdif_in_a20"; 681 function = "spdif_in"; 682 bias-disable; 683 }; 684 }; 685 686 spdif_out_a1_pins: spdif_out_a1 { 687 mux { 688 groups = "spdif_out_a1"; 689 function = "spdif_out"; 690 bias-disable; 691 }; 692 }; 693 694 spdif_out_a11_pins: spdif_out_a11 { 695 mux { 696 groups = "spdif_out_a11"; 697 function = "spdif_out"; 698 bias-disable; 699 }; 700 }; 701 702 spdif_out_a19_pins: spdif_out_a19 { 703 mux { 704 groups = "spdif_out_a19"; 705 function = "spdif_out"; 706 bias-disable; 707 }; 708 }; 709 710 spdif_out_a20_pins: spdif_out_a20 { 711 mux { 712 groups = "spdif_out_a20"; 713 function = "spdif_out"; 714 bias-disable; 715 }; 716 }; 717 718 spdif_out_z_pins: spdif_out_z { 719 mux { 720 groups = "spdif_out_z"; 721 function = "spdif_out"; 722 bias-disable; 723 }; 724 }; 725 726 spi0_pins: spi0 { 727 mux { 728 groups = "spi0_miso", 729 "spi0_mosi", 730 "spi0_clk"; 731 function = "spi0"; 732 bias-disable; 733 }; 734 }; 735 736 spi0_ss0_pins: spi0_ss0 { 737 mux { 738 groups = "spi0_ss0"; 739 function = "spi0"; 740 bias-disable; 741 }; 742 }; 743 744 spi0_ss1_pins: spi0_ss1 { 745 mux { 746 groups = "spi0_ss1"; 747 function = "spi0"; 748 bias-disable; 749 }; 750 }; 751 752 spi0_ss2_pins: spi0_ss2 { 753 mux { 754 groups = "spi0_ss2"; 755 function = "spi0"; 756 bias-disable; 757 }; 758 }; 759 760 spi1_a_pins: spi1_a { 761 mux { 762 groups = "spi1_miso_a", 763 "spi1_mosi_a", 764 "spi1_clk_a"; 765 function = "spi1"; 766 bias-disable; 767 }; 768 }; 769 770 spi1_ss0_a_pins: spi1_ss0_a { 771 mux { 772 groups = "spi1_ss0_a"; 773 function = "spi1"; 774 bias-disable; 775 }; 776 }; 777 778 spi1_ss1_pins: spi1_ss1 { 779 mux { 780 groups = "spi1_ss1"; 781 function = "spi1"; 782 bias-disable; 783 }; 784 }; 785 786 spi1_x_pins: spi1_x { 787 mux { 788 groups = "spi1_miso_x", 789 "spi1_mosi_x", 790 "spi1_clk_x"; 791 function = "spi1"; 792 bias-disable; 793 }; 794 }; 795 796 spi1_ss0_x_pins: spi1_ss0_x { 797 mux { 798 groups = "spi1_ss0_x"; 799 function = "spi1"; 800 bias-disable; 801 }; 802 }; 803 804 tdma_din0_pins: tdma_din0 { 805 mux { 806 groups = "tdma_din0"; 807 function = "tdma"; 808 bias-disable; 809 }; 810 }; 811 812 tdma_dout0_x14_pins: tdma_dout0_x14 { 813 mux { 814 groups = "tdma_dout0_x14"; 815 function = "tdma"; 816 bias-disable; 817 }; 818 }; 819 820 tdma_dout0_x15_pins: tdma_dout0_x15 { 821 mux { 822 groups = "tdma_dout0_x15"; 823 function = "tdma"; 824 bias-disable; 825 }; 826 }; 827 828 tdma_dout1_pins: tdma_dout1 { 829 mux { 830 groups = "tdma_dout1"; 831 function = "tdma"; 832 bias-disable; 833 }; 834 }; 835 836 tdma_din1_pins: tdma_din1 { 837 mux { 838 groups = "tdma_din1"; 839 function = "tdma"; 840 bias-disable; 841 }; 842 }; 843 844 tdma_fs_pins: tdma_fs { 845 mux { 846 groups = "tdma_fs"; 847 function = "tdma"; 848 bias-disable; 849 }; 850 }; 851 852 tdma_fs_slv_pins: tdma_fs_slv { 853 mux { 854 groups = "tdma_fs_slv"; 855 function = "tdma"; 856 bias-disable; 857 }; 858 }; 859 860 tdma_sclk_pins: tdma_sclk { 861 mux { 862 groups = "tdma_sclk"; 863 function = "tdma"; 864 bias-disable; 865 }; 866 }; 867 868 tdma_sclk_slv_pins: tdma_sclk_slv { 869 mux { 870 groups = "tdma_sclk_slv"; 871 function = "tdma"; 872 bias-disable; 873 }; 874 }; 875 876 tdmb_din0_pins: tdmb_din0 { 877 mux { 878 groups = "tdmb_din0"; 879 function = "tdmb"; 880 bias-disable; 881 }; 882 }; 883 884 tdmb_din1_pins: tdmb_din1 { 885 mux { 886 groups = "tdmb_din1"; 887 function = "tdmb"; 888 bias-disable; 889 }; 890 }; 891 892 tdmb_din2_pins: tdmb_din2 { 893 mux { 894 groups = "tdmb_din2"; 895 function = "tdmb"; 896 bias-disable; 897 }; 898 }; 899 900 tdmb_din3_pins: tdmb_din3 { 901 mux { 902 groups = "tdmb_din3"; 903 function = "tdmb"; 904 bias-disable; 905 }; 906 }; 907 908 tdmb_dout0_pins: tdmb_dout0 { 909 mux { 910 groups = "tdmb_dout0"; 911 function = "tdmb"; 912 bias-disable; 913 }; 914 }; 915 916 tdmb_dout1_pins: tdmb_dout1 { 917 mux { 918 groups = "tdmb_dout1"; 919 function = "tdmb"; 920 bias-disable; 921 }; 922 }; 923 924 tdmb_dout2_pins: tdmb_dout2 { 925 mux { 926 groups = "tdmb_dout2"; 927 function = "tdmb"; 928 bias-disable; 929 }; 930 }; 931 932 tdmb_dout3_pins: tdmb_dout3 { 933 mux { 934 groups = "tdmb_dout3"; 935 function = "tdmb"; 936 bias-disable; 937 }; 938 }; 939 940 tdmb_fs_pins: tdmb_fs { 941 mux { 942 groups = "tdmb_fs"; 943 function = "tdmb"; 944 bias-disable; 945 }; 946 }; 947 948 tdmb_fs_slv_pins: tdmb_fs_slv { 949 mux { 950 groups = "tdmb_fs_slv"; 951 function = "tdmb"; 952 bias-disable; 953 }; 954 }; 955 956 tdmb_sclk_pins: tdmb_sclk { 957 mux { 958 groups = "tdmb_sclk"; 959 function = "tdmb"; 960 bias-disable; 961 }; 962 }; 963 964 tdmb_sclk_slv_pins: tdmb_sclk_slv { 965 mux { 966 groups = "tdmb_sclk_slv"; 967 function = "tdmb"; 968 bias-disable; 969 }; 970 }; 971 972 tdmc_fs_pins: tdmc_fs { 973 mux { 974 groups = "tdmc_fs"; 975 function = "tdmc"; 976 bias-disable; 977 }; 978 }; 979 980 tdmc_fs_slv_pins: tdmc_fs_slv { 981 mux { 982 groups = "tdmc_fs_slv"; 983 function = "tdmc"; 984 bias-disable; 985 }; 986 }; 987 988 tdmc_sclk_pins: tdmc_sclk { 989 mux { 990 groups = "tdmc_sclk"; 991 function = "tdmc"; 992 bias-disable; 993 }; 994 }; 995 996 tdmc_sclk_slv_pins: tdmc_sclk_slv { 997 mux { 998 groups = "tdmc_sclk_slv"; 999 function = "tdmc"; 1000 bias-disable; 1001 }; 1002 }; 1003 1004 tdmc_din0_pins: tdmc_din0 { 1005 mux { 1006 groups = "tdmc_din0"; 1007 function = "tdmc"; 1008 bias-disable; 1009 }; 1010 }; 1011 1012 tdmc_din1_pins: tdmc_din1 { 1013 mux { 1014 groups = "tdmc_din1"; 1015 function = "tdmc"; 1016 bias-disable; 1017 }; 1018 }; 1019 1020 tdmc_din2_pins: tdmc_din2 { 1021 mux { 1022 groups = "tdmc_din2"; 1023 function = "tdmc"; 1024 bias-disable; 1025 }; 1026 }; 1027 1028 tdmc_din3_pins: tdmc_din3 { 1029 mux { 1030 groups = "tdmc_din3"; 1031 function = "tdmc"; 1032 bias-disable; 1033 }; 1034 }; 1035 1036 tdmc_dout0_pins: tdmc_dout0 { 1037 mux { 1038 groups = "tdmc_dout0"; 1039 function = "tdmc"; 1040 bias-disable; 1041 }; 1042 }; 1043 1044 tdmc_dout1_pins: tdmc_dout1 { 1045 mux { 1046 groups = "tdmc_dout1"; 1047 function = "tdmc"; 1048 bias-disable; 1049 }; 1050 }; 1051 1052 tdmc_dout2_pins: tdmc_dout2 { 1053 mux { 1054 groups = "tdmc_dout2"; 1055 function = "tdmc"; 1056 bias-disable; 1057 }; 1058 }; 1059 1060 tdmc_dout3_pins: tdmc_dout3 { 1061 mux { 1062 groups = "tdmc_dout3"; 1063 function = "tdmc"; 1064 bias-disable; 1065 }; 1066 }; 1067 1068 uart_a_pins: uart_a { 1069 mux { 1070 groups = "uart_tx_a", 1071 "uart_rx_a"; 1072 function = "uart_a"; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 uart_a_cts_rts_pins: uart_a_cts_rts { 1078 mux { 1079 groups = "uart_cts_a", 1080 "uart_rts_a"; 1081 function = "uart_a"; 1082 bias-disable; 1083 }; 1084 }; 1085 1086 uart_b_x_pins: uart_b_x { 1087 mux { 1088 groups = "uart_tx_b_x", 1089 "uart_rx_b_x"; 1090 function = "uart_b"; 1091 bias-disable; 1092 }; 1093 }; 1094 1095 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1096 mux { 1097 groups = "uart_cts_b_x", 1098 "uart_rts_b_x"; 1099 function = "uart_b"; 1100 bias-disable; 1101 }; 1102 }; 1103 1104 uart_b_z_pins: uart_b_z { 1105 mux { 1106 groups = "uart_tx_b_z", 1107 "uart_rx_b_z"; 1108 function = "uart_b"; 1109 bias-disable; 1110 }; 1111 }; 1112 1113 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1114 mux { 1115 groups = "uart_cts_b_z", 1116 "uart_rts_b_z"; 1117 function = "uart_b"; 1118 bias-disable; 1119 }; 1120 }; 1121 1122 uart_ao_b_z_pins: uart_ao_b_z { 1123 mux { 1124 groups = "uart_ao_tx_b_z", 1125 "uart_ao_rx_b_z"; 1126 function = "uart_ao_b_z"; 1127 bias-disable; 1128 }; 1129 }; 1130 1131 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1132 mux { 1133 groups = "uart_ao_cts_b_z", 1134 "uart_ao_rts_b_z"; 1135 function = "uart_ao_b_z"; 1136 bias-disable; 1137 }; 1138 }; 1139 }; 1140 }; 1141 1142 hiubus: bus@ff63c000 { 1143 compatible = "simple-bus"; 1144 reg = <0x0 0xff63c000 0x0 0x1c00>; 1145 #address-cells = <2>; 1146 #size-cells = <2>; 1147 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1148 1149 sysctrl: system-controller@0 { 1150 compatible = "amlogic,meson-axg-hhi-sysctrl", 1151 "simple-mfd", "syscon"; 1152 reg = <0 0 0 0x400>; 1153 1154 clkc: clock-controller { 1155 compatible = "amlogic,axg-clkc"; 1156 #clock-cells = <1>; 1157 clocks = <&xtal>; 1158 clock-names = "xtal"; 1159 }; 1160 }; 1161 }; 1162 1163 mailbox: mailbox@ff63c404 { 1164 compatible = "amlogic,meson-gxbb-mhu"; 1165 reg = <0 0xff63c404 0 0x4c>; 1166 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1167 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1168 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1169 #mbox-cells = <1>; 1170 }; 1171 1172 audio: bus@ff642000 { 1173 compatible = "simple-bus"; 1174 reg = <0x0 0xff642000 0x0 0x2000>; 1175 #address-cells = <2>; 1176 #size-cells = <2>; 1177 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1178 1179 clkc_audio: clock-controller@0 { 1180 compatible = "amlogic,axg-audio-clkc"; 1181 reg = <0x0 0x0 0x0 0xb4>; 1182 #clock-cells = <1>; 1183 1184 clocks = <&clkc CLKID_AUDIO>, 1185 <&clkc CLKID_MPLL0>, 1186 <&clkc CLKID_MPLL1>, 1187 <&clkc CLKID_MPLL2>, 1188 <&clkc CLKID_MPLL3>, 1189 <&clkc CLKID_HIFI_PLL>, 1190 <&clkc CLKID_FCLK_DIV3>, 1191 <&clkc CLKID_FCLK_DIV4>, 1192 <&clkc CLKID_GP0_PLL>; 1193 clock-names = "pclk", 1194 "mst_in0", 1195 "mst_in1", 1196 "mst_in2", 1197 "mst_in3", 1198 "mst_in4", 1199 "mst_in5", 1200 "mst_in6", 1201 "mst_in7"; 1202 1203 resets = <&reset RESET_AUDIO>; 1204 }; 1205 1206 toddr_a: audio-controller@100 { 1207 compatible = "amlogic,axg-toddr"; 1208 reg = <0x0 0x100 0x0 0x2c>; 1209 #sound-dai-cells = <0>; 1210 sound-name-prefix = "TODDR_A"; 1211 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1212 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1213 resets = <&arb AXG_ARB_TODDR_A>; 1214 amlogic,fifo-depth = <512>; 1215 status = "disabled"; 1216 }; 1217 1218 toddr_b: audio-controller@140 { 1219 compatible = "amlogic,axg-toddr"; 1220 reg = <0x0 0x140 0x0 0x2c>; 1221 #sound-dai-cells = <0>; 1222 sound-name-prefix = "TODDR_B"; 1223 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1224 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1225 resets = <&arb AXG_ARB_TODDR_B>; 1226 amlogic,fifo-depth = <256>; 1227 status = "disabled"; 1228 }; 1229 1230 toddr_c: audio-controller@180 { 1231 compatible = "amlogic,axg-toddr"; 1232 reg = <0x0 0x180 0x0 0x2c>; 1233 #sound-dai-cells = <0>; 1234 sound-name-prefix = "TODDR_C"; 1235 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1236 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1237 resets = <&arb AXG_ARB_TODDR_C>; 1238 amlogic,fifo-depth = <256>; 1239 status = "disabled"; 1240 }; 1241 1242 frddr_a: audio-controller@1c0 { 1243 compatible = "amlogic,axg-frddr"; 1244 reg = <0x0 0x1c0 0x0 0x2c>; 1245 #sound-dai-cells = <0>; 1246 sound-name-prefix = "FRDDR_A"; 1247 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1248 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1249 resets = <&arb AXG_ARB_FRDDR_A>; 1250 amlogic,fifo-depth = <512>; 1251 status = "disabled"; 1252 }; 1253 1254 frddr_b: audio-controller@200 { 1255 compatible = "amlogic,axg-frddr"; 1256 reg = <0x0 0x200 0x0 0x2c>; 1257 #sound-dai-cells = <0>; 1258 sound-name-prefix = "FRDDR_B"; 1259 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1260 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1261 resets = <&arb AXG_ARB_FRDDR_B>; 1262 amlogic,fifo-depth = <256>; 1263 status = "disabled"; 1264 }; 1265 1266 frddr_c: audio-controller@240 { 1267 compatible = "amlogic,axg-frddr"; 1268 reg = <0x0 0x240 0x0 0x2c>; 1269 #sound-dai-cells = <0>; 1270 sound-name-prefix = "FRDDR_C"; 1271 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1272 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1273 resets = <&arb AXG_ARB_FRDDR_C>; 1274 amlogic,fifo-depth = <256>; 1275 status = "disabled"; 1276 }; 1277 1278 arb: reset-controller@280 { 1279 compatible = "amlogic,meson-axg-audio-arb"; 1280 reg = <0x0 0x280 0x0 0x4>; 1281 #reset-cells = <1>; 1282 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1283 }; 1284 1285 tdmin_a: audio-controller@300 { 1286 compatible = "amlogic,axg-tdmin"; 1287 reg = <0x0 0x300 0x0 0x40>; 1288 sound-name-prefix = "TDMIN_A"; 1289 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1290 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1291 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1292 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1293 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1294 clock-names = "pclk", "sclk", "sclk_sel", 1295 "lrclk", "lrclk_sel"; 1296 status = "disabled"; 1297 }; 1298 1299 tdmin_b: audio-controller@340 { 1300 compatible = "amlogic,axg-tdmin"; 1301 reg = <0x0 0x340 0x0 0x40>; 1302 sound-name-prefix = "TDMIN_B"; 1303 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1304 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1305 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1306 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1307 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1308 clock-names = "pclk", "sclk", "sclk_sel", 1309 "lrclk", "lrclk_sel"; 1310 status = "disabled"; 1311 }; 1312 1313 tdmin_c: audio-controller@380 { 1314 compatible = "amlogic,axg-tdmin"; 1315 reg = <0x0 0x380 0x0 0x40>; 1316 sound-name-prefix = "TDMIN_C"; 1317 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1318 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1319 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1320 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1321 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1322 clock-names = "pclk", "sclk", "sclk_sel", 1323 "lrclk", "lrclk_sel"; 1324 status = "disabled"; 1325 }; 1326 1327 tdmin_lb: audio-controller@3c0 { 1328 compatible = "amlogic,axg-tdmin"; 1329 reg = <0x0 0x3c0 0x0 0x40>; 1330 sound-name-prefix = "TDMIN_LB"; 1331 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1332 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1333 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1334 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1335 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1336 clock-names = "pclk", "sclk", "sclk_sel", 1337 "lrclk", "lrclk_sel"; 1338 status = "disabled"; 1339 }; 1340 1341 spdifin: audio-controller@400 { 1342 compatible = "amlogic,axg-spdifin"; 1343 reg = <0x0 0x400 0x0 0x30>; 1344 #sound-dai-cells = <0>; 1345 sound-name-prefix = "SPDIFIN"; 1346 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1347 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1348 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1349 clock-names = "pclk", "refclk"; 1350 status = "disabled"; 1351 }; 1352 1353 spdifout: audio-controller@480 { 1354 compatible = "amlogic,axg-spdifout"; 1355 reg = <0x0 0x480 0x0 0x50>; 1356 #sound-dai-cells = <0>; 1357 sound-name-prefix = "SPDIFOUT"; 1358 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1359 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1360 clock-names = "pclk", "mclk"; 1361 status = "disabled"; 1362 }; 1363 1364 tdmout_a: audio-controller@500 { 1365 compatible = "amlogic,axg-tdmout"; 1366 reg = <0x0 0x500 0x0 0x40>; 1367 sound-name-prefix = "TDMOUT_A"; 1368 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1369 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1370 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1371 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1372 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1373 clock-names = "pclk", "sclk", "sclk_sel", 1374 "lrclk", "lrclk_sel"; 1375 status = "disabled"; 1376 }; 1377 1378 tdmout_b: audio-controller@540 { 1379 compatible = "amlogic,axg-tdmout"; 1380 reg = <0x0 0x540 0x0 0x40>; 1381 sound-name-prefix = "TDMOUT_B"; 1382 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1383 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1384 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1385 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1386 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1387 clock-names = "pclk", "sclk", "sclk_sel", 1388 "lrclk", "lrclk_sel"; 1389 status = "disabled"; 1390 }; 1391 1392 tdmout_c: audio-controller@580 { 1393 compatible = "amlogic,axg-tdmout"; 1394 reg = <0x0 0x580 0x0 0x40>; 1395 sound-name-prefix = "TDMOUT_C"; 1396 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1397 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1398 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1399 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1400 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1401 clock-names = "pclk", "sclk", "sclk_sel", 1402 "lrclk", "lrclk_sel"; 1403 status = "disabled"; 1404 }; 1405 }; 1406 1407 aobus: bus@ff800000 { 1408 compatible = "simple-bus"; 1409 reg = <0x0 0xff800000 0x0 0x100000>; 1410 #address-cells = <2>; 1411 #size-cells = <2>; 1412 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1413 1414 sysctrl_AO: sys-ctrl@0 { 1415 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1416 reg = <0x0 0x0 0x0 0x100>; 1417 1418 clkc_AO: clock-controller { 1419 compatible = "amlogic,meson-axg-aoclkc"; 1420 #clock-cells = <1>; 1421 #reset-cells = <1>; 1422 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1423 clock-names = "xtal", "mpeg-clk"; 1424 }; 1425 }; 1426 1427 pinctrl_aobus: pinctrl@14 { 1428 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1429 #address-cells = <2>; 1430 #size-cells = <2>; 1431 ranges; 1432 1433 gpio_ao: bank@14 { 1434 reg = <0x0 0x00014 0x0 0x8>, 1435 <0x0 0x0002c 0x0 0x4>, 1436 <0x0 0x00024 0x0 0x8>; 1437 reg-names = "mux", "pull", "gpio"; 1438 gpio-controller; 1439 #gpio-cells = <2>; 1440 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1441 }; 1442 1443 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1444 mux { 1445 groups = "i2c_ao_sck_4"; 1446 function = "i2c_ao"; 1447 bias-disable; 1448 }; 1449 }; 1450 1451 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1452 mux { 1453 groups = "i2c_ao_sck_8"; 1454 function = "i2c_ao"; 1455 bias-disable; 1456 }; 1457 }; 1458 1459 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1460 mux { 1461 groups = "i2c_ao_sck_10"; 1462 function = "i2c_ao"; 1463 bias-disable; 1464 }; 1465 }; 1466 1467 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1468 mux { 1469 groups = "i2c_ao_sda_5"; 1470 function = "i2c_ao"; 1471 bias-disable; 1472 }; 1473 }; 1474 1475 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1476 mux { 1477 groups = "i2c_ao_sda_9"; 1478 function = "i2c_ao"; 1479 bias-disable; 1480 }; 1481 }; 1482 1483 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1484 mux { 1485 groups = "i2c_ao_sda_11"; 1486 function = "i2c_ao"; 1487 bias-disable; 1488 }; 1489 }; 1490 1491 remote_input_ao_pins: remote_input_ao { 1492 mux { 1493 groups = "remote_input_ao"; 1494 function = "remote_input_ao"; 1495 bias-disable; 1496 }; 1497 }; 1498 1499 uart_ao_a_pins: uart_ao_a { 1500 mux { 1501 groups = "uart_ao_tx_a", 1502 "uart_ao_rx_a"; 1503 function = "uart_ao_a"; 1504 bias-disable; 1505 }; 1506 }; 1507 1508 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1509 mux { 1510 groups = "uart_ao_cts_a", 1511 "uart_ao_rts_a"; 1512 function = "uart_ao_a"; 1513 bias-disable; 1514 }; 1515 }; 1516 1517 uart_ao_b_pins: uart_ao_b { 1518 mux { 1519 groups = "uart_ao_tx_b", 1520 "uart_ao_rx_b"; 1521 function = "uart_ao_b"; 1522 bias-disable; 1523 }; 1524 }; 1525 1526 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1527 mux { 1528 groups = "uart_ao_cts_b", 1529 "uart_ao_rts_b"; 1530 function = "uart_ao_b"; 1531 bias-disable; 1532 }; 1533 }; 1534 }; 1535 1536 sec_AO: ao-secure@140 { 1537 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1538 reg = <0x0 0x140 0x0 0x140>; 1539 amlogic,has-chip-id; 1540 }; 1541 1542 pwm_AO_cd: pwm@2000 { 1543 compatible = "amlogic,meson-axg-ao-pwm"; 1544 reg = <0x0 0x02000 0x0 0x20>; 1545 #pwm-cells = <3>; 1546 status = "disabled"; 1547 }; 1548 1549 uart_AO: serial@3000 { 1550 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1551 reg = <0x0 0x3000 0x0 0x18>; 1552 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1553 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1554 clock-names = "xtal", "pclk", "baud"; 1555 status = "disabled"; 1556 }; 1557 1558 uart_AO_B: serial@4000 { 1559 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1560 reg = <0x0 0x4000 0x0 0x18>; 1561 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1562 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1563 clock-names = "xtal", "pclk", "baud"; 1564 status = "disabled"; 1565 }; 1566 1567 i2c_AO: i2c@5000 { 1568 compatible = "amlogic,meson-axg-i2c"; 1569 reg = <0x0 0x05000 0x0 0x20>; 1570 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1571 clocks = <&clkc CLKID_AO_I2C>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 pwm_AO_ab: pwm@7000 { 1578 compatible = "amlogic,meson-axg-ao-pwm"; 1579 reg = <0x0 0x07000 0x0 0x20>; 1580 #pwm-cells = <3>; 1581 status = "disabled"; 1582 }; 1583 1584 ir: ir@8000 { 1585 compatible = "amlogic,meson-gxbb-ir"; 1586 reg = <0x0 0x8000 0x0 0x20>; 1587 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1588 status = "disabled"; 1589 }; 1590 1591 saradc: adc@9000 { 1592 compatible = "amlogic,meson-axg-saradc", 1593 "amlogic,meson-saradc"; 1594 reg = <0x0 0x9000 0x0 0x38>; 1595 #io-channel-cells = <1>; 1596 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1597 clocks = <&xtal>, 1598 <&clkc_AO CLKID_AO_SAR_ADC>, 1599 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1600 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1601 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1602 status = "disabled"; 1603 }; 1604 }; 1605 1606 gic: interrupt-controller@ffc01000 { 1607 compatible = "arm,gic-400"; 1608 reg = <0x0 0xffc01000 0 0x1000>, 1609 <0x0 0xffc02000 0 0x2000>, 1610 <0x0 0xffc04000 0 0x2000>, 1611 <0x0 0xffc06000 0 0x2000>; 1612 interrupt-controller; 1613 interrupts = <GIC_PPI 9 1614 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1615 #interrupt-cells = <3>; 1616 #address-cells = <0>; 1617 }; 1618 1619 cbus: bus@ffd00000 { 1620 compatible = "simple-bus"; 1621 reg = <0x0 0xffd00000 0x0 0x25000>; 1622 #address-cells = <2>; 1623 #size-cells = <2>; 1624 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1625 1626 reset: reset-controller@1004 { 1627 compatible = "amlogic,meson-axg-reset"; 1628 reg = <0x0 0x01004 0x0 0x9c>; 1629 #reset-cells = <1>; 1630 }; 1631 1632 gpio_intc: interrupt-controller@f080 { 1633 compatible = "amlogic,meson-axg-gpio-intc", 1634 "amlogic,meson-gpio-intc"; 1635 reg = <0x0 0xf080 0x0 0x10>; 1636 interrupt-controller; 1637 #interrupt-cells = <2>; 1638 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1639 }; 1640 1641 watchdog@f0d0 { 1642 compatible = "amlogic,meson-gxbb-wdt"; 1643 reg = <0x0 0xf0d0 0x0 0x10>; 1644 clocks = <&xtal>; 1645 }; 1646 1647 pwm_ab: pwm@1b000 { 1648 compatible = "amlogic,meson-axg-ee-pwm"; 1649 reg = <0x0 0x1b000 0x0 0x20>; 1650 #pwm-cells = <3>; 1651 status = "disabled"; 1652 }; 1653 1654 pwm_cd: pwm@1a000 { 1655 compatible = "amlogic,meson-axg-ee-pwm"; 1656 reg = <0x0 0x1a000 0x0 0x20>; 1657 #pwm-cells = <3>; 1658 status = "disabled"; 1659 }; 1660 1661 spicc0: spi@13000 { 1662 compatible = "amlogic,meson-axg-spicc"; 1663 reg = <0x0 0x13000 0x0 0x3c>; 1664 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&clkc CLKID_SPICC0>; 1666 clock-names = "core"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 spicc1: spi@15000 { 1673 compatible = "amlogic,meson-axg-spicc"; 1674 reg = <0x0 0x15000 0x0 0x3c>; 1675 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1676 clocks = <&clkc CLKID_SPICC1>; 1677 clock-names = "core"; 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 status = "disabled"; 1681 }; 1682 1683 clk_msr: clock-measure@18000 { 1684 compatible = "amlogic,meson-axg-clk-measure"; 1685 reg = <0x0 0x18000 0x0 0x10>; 1686 }; 1687 1688 i2c3: i2c@1c000 { 1689 compatible = "amlogic,meson-axg-i2c"; 1690 reg = <0x0 0x1c000 0x0 0x20>; 1691 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1692 clocks = <&clkc CLKID_I2C>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 status = "disabled"; 1696 }; 1697 1698 i2c2: i2c@1d000 { 1699 compatible = "amlogic,meson-axg-i2c"; 1700 reg = <0x0 0x1d000 0x0 0x20>; 1701 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1702 clocks = <&clkc CLKID_I2C>; 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 status = "disabled"; 1706 }; 1707 1708 i2c1: i2c@1e000 { 1709 compatible = "amlogic,meson-axg-i2c"; 1710 reg = <0x0 0x1e000 0x0 0x20>; 1711 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1712 clocks = <&clkc CLKID_I2C>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 status = "disabled"; 1716 }; 1717 1718 i2c0: i2c@1f000 { 1719 compatible = "amlogic,meson-axg-i2c"; 1720 reg = <0x0 0x1f000 0x0 0x20>; 1721 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1722 clocks = <&clkc CLKID_I2C>; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 uart_B: serial@23000 { 1729 compatible = "amlogic,meson-gx-uart"; 1730 reg = <0x0 0x23000 0x0 0x18>; 1731 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1732 status = "disabled"; 1733 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1734 clock-names = "xtal", "pclk", "baud"; 1735 }; 1736 1737 uart_A: serial@24000 { 1738 compatible = "amlogic,meson-gx-uart"; 1739 reg = <0x0 0x24000 0x0 0x18>; 1740 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1741 status = "disabled"; 1742 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1743 clock-names = "xtal", "pclk", "baud"; 1744 }; 1745 }; 1746 1747 apb: bus@ffe00000 { 1748 compatible = "simple-bus"; 1749 reg = <0x0 0xffe00000 0x0 0x200000>; 1750 #address-cells = <2>; 1751 #size-cells = <2>; 1752 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1753 1754 sd_emmc_b: sd@5000 { 1755 compatible = "amlogic,meson-axg-mmc"; 1756 reg = <0x0 0x5000 0x0 0x800>; 1757 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1758 status = "disabled"; 1759 clocks = <&clkc CLKID_SD_EMMC_B>, 1760 <&clkc CLKID_SD_EMMC_B_CLK0>, 1761 <&clkc CLKID_FCLK_DIV2>; 1762 clock-names = "core", "clkin0", "clkin1"; 1763 resets = <&reset RESET_SD_EMMC_B>; 1764 }; 1765 1766 sd_emmc_c: mmc@7000 { 1767 compatible = "amlogic,meson-axg-mmc"; 1768 reg = <0x0 0x7000 0x0 0x800>; 1769 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1770 status = "disabled"; 1771 clocks = <&clkc CLKID_SD_EMMC_C>, 1772 <&clkc CLKID_SD_EMMC_C_CLK0>, 1773 <&clkc CLKID_FCLK_DIV2>; 1774 clock-names = "core", "clkin0", "clkin1"; 1775 resets = <&reset RESET_SD_EMMC_C>; 1776 }; 1777 1778 usb2_phy1: phy@9020 { 1779 compatible = "amlogic,meson-gxl-usb2-phy"; 1780 #phy-cells = <0>; 1781 reg = <0x0 0x9020 0x0 0x20>; 1782 clocks = <&clkc CLKID_USB>; 1783 clock-names = "phy"; 1784 resets = <&reset RESET_USB_OTG>; 1785 reset-names = "phy"; 1786 }; 1787 }; 1788 1789 sram: sram@fffc0000 { 1790 compatible = "mmio-sram"; 1791 reg = <0x0 0xfffc0000 0x0 0x20000>; 1792 #address-cells = <1>; 1793 #size-cells = <1>; 1794 ranges = <0 0x0 0xfffc0000 0x20000>; 1795 1796 cpu_scp_lpri: scp-sram@13000 { 1797 compatible = "amlogic,meson-axg-scp-shmem"; 1798 reg = <0x13000 0x400>; 1799 }; 1800 1801 cpu_scp_hpri: scp-sram@13400 { 1802 compatible = "amlogic,meson-axg-scp-shmem"; 1803 reg = <0x13400 0x400>; 1804 }; 1805 }; 1806 }; 1807 1808 timer { 1809 compatible = "arm,armv8-timer"; 1810 interrupts = <GIC_PPI 13 1811 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1812 <GIC_PPI 14 1813 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1814 <GIC_PPI 11 1815 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1816 <GIC_PPI 10 1817 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1818 }; 1819 1820 xtal: xtal-clk { 1821 compatible = "fixed-clock"; 1822 clock-frequency = <24000000>; 1823 clock-output-names = "xtal"; 1824 #clock-cells = <0>; 1825 }; 1826}; 1827