1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-clkc.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11
12/ {
13	compatible = "amlogic,meson-axg";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		/* 16 MiB reserved for Hardware ROM Firmware */
25		hwrom_reserved: hwrom@0 {
26			reg = <0x0 0x0 0x0 0x1000000>;
27			no-map;
28		};
29
30		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
31		secmon_reserved: secmon@5000000 {
32			reg = <0x0 0x05000000 0x0 0x300000>;
33			no-map;
34		};
35	};
36
37	cpus {
38		#address-cells = <0x2>;
39		#size-cells = <0x0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0x0 0x0>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53", "arm,armv8";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		cpu2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63		};
64
65		cpu3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&l2>;
71		};
72
73		l2: l2-cache0 {
74			compatible = "cache";
75		};
76	};
77
78	arm-pmu {
79		compatible = "arm,cortex-a53-pmu";
80		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
85	};
86
87	psci {
88		compatible = "arm,psci-1.0";
89		method = "smc";
90	};
91
92	timer {
93		compatible = "arm,armv8-timer";
94		interrupts = <GIC_PPI 13
95			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14
97			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 11
99			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100			     <GIC_PPI 10
101			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
102	};
103
104	xtal: xtal-clk {
105		compatible = "fixed-clock";
106		clock-frequency = <24000000>;
107		clock-output-names = "xtal";
108		#clock-cells = <0>;
109	};
110
111	soc {
112		compatible = "simple-bus";
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		apb: apb@ffe00000 {
118			compatible = "simple-bus";
119			reg = <0x0 0xffe00000 0x0 0x200000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
123
124			sd_emmc_b: sd@5000 {
125				compatible = "amlogic,meson-axg-mmc";
126				reg = <0x0 0x5000 0x0 0x2000>;
127				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
128				status = "disabled";
129				clocks = <&clkc CLKID_SD_EMMC_B>,
130					<&clkc CLKID_SD_EMMC_B_CLK0>,
131					<&clkc CLKID_FCLK_DIV2>;
132				clock-names = "core", "clkin0", "clkin1";
133			};
134
135			sd_emmc_c: mmc@7000 {
136				compatible = "amlogic,meson-axg-mmc";
137				reg = <0x0 0x7000 0x0 0x2000>;
138				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
139				status = "disabled";
140				clocks = <&clkc CLKID_SD_EMMC_C>,
141					<&clkc CLKID_SD_EMMC_C_CLK0>,
142					<&clkc CLKID_FCLK_DIV2>;
143				clock-names = "core", "clkin0", "clkin1";
144			};
145		};
146
147		cbus: bus@ffd00000 {
148			compatible = "simple-bus";
149			reg = <0x0 0xffd00000 0x0 0x25000>;
150			#address-cells = <2>;
151			#size-cells = <2>;
152			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
153
154			gpio_intc: interrupt-controller@f080 {
155				compatible = "amlogic,meson-gpio-intc";
156				reg = <0x0 0xf080 0x0 0x10>;
157				interrupt-controller;
158				#interrupt-cells = <2>;
159				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
160				status = "disabled";
161			};
162
163			pwm_ab: pwm@1b000 {
164				compatible = "amlogic,meson-axg-ee-pwm";
165				reg = <0x0 0x1b000 0x0 0x20>;
166				#pwm-cells = <3>;
167				status = "disabled";
168			};
169
170			pwm_cd: pwm@1a000 {
171				compatible = "amlogic,meson-axg-ee-pwm";
172				reg = <0x0 0x1a000 0x0 0x20>;
173				#pwm-cells = <3>;
174				status = "disabled";
175			};
176
177			reset: reset-controller@1004 {
178				compatible = "amlogic,meson-axg-reset";
179				reg = <0x0 0x01004 0x0 0x9c>;
180				#reset-cells = <1>;
181			};
182
183			spicc0: spi@13000 {
184				compatible = "amlogic,meson-axg-spicc";
185				reg = <0x0 0x13000 0x0 0x3c>;
186				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
187				clocks = <&clkc CLKID_SPICC0>;
188				clock-names = "core";
189				#address-cells = <1>;
190				#size-cells = <0>;
191				status = "disabled";
192			};
193
194			spicc1: spi@15000 {
195				compatible = "amlogic,meson-axg-spicc";
196				reg = <0x0 0x15000 0x0 0x3c>;
197				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
198				clocks = <&clkc CLKID_SPICC1>;
199				clock-names = "core";
200				#address-cells = <1>;
201				#size-cells = <0>;
202				status = "disabled";
203			};
204
205			i2c0: i2c@1f000 {
206				compatible = "amlogic,meson-axg-i2c";
207				status = "disabled";
208				reg = <0x0 0x1f000 0x0 0x20>;
209				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
210					<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
211				#address-cells = <1>;
212				#size-cells = <0>;
213				clocks = <&clkc CLKID_I2C>;
214				clock-names = "clk_i2c";
215			};
216
217			i2c1: i2c@1e000 {
218				compatible = "amlogic,meson-axg-i2c";
219				#address-cells = <1>;
220				#size-cells = <0>;
221				reg = <0x0 0x1e000 0x0 0x20>;
222				status = "disabled";
223				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
224					<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
225				clocks = <&clkc CLKID_I2C>;
226				clock-names = "clk_i2c";
227			};
228
229			i2c2: i2c@1d000 {
230				compatible = "amlogic,meson-axg-i2c";
231				status = "disabled";
232				reg = <0x0 0x1d000 0x0 0x20>;
233				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
234					<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
235				#address-cells = <1>;
236				#size-cells = <0>;
237				clocks = <&clkc CLKID_I2C>;
238				clock-names = "clk_i2c";
239			};
240
241			i2c3: i2c@1c000 {
242				compatible = "amlogic,meson-axg-i2c";
243				status = "disabled";
244				reg = <0x0 0x1c000 0x0 0x20>;
245				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
246					<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
247				#address-cells = <1>;
248				#size-cells = <0>;
249				clocks = <&clkc CLKID_I2C>;
250				clock-names = "clk_i2c";
251			};
252
253			uart_A: serial@24000 {
254				compatible = "amlogic,meson-gx-uart";
255				reg = <0x0 0x24000 0x0 0x18>;
256				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
257				status = "disabled";
258				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
259				clock-names = "xtal", "pclk", "baud";
260			};
261
262			uart_B: serial@23000 {
263				compatible = "amlogic,meson-gx-uart";
264				reg = <0x0 0x23000 0x0 0x18>;
265				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
266				status = "disabled";
267				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
268				clock-names = "xtal", "pclk", "baud";
269			};
270		};
271
272		ethmac: ethernet@ff3f0000 {
273			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
274			reg = <0x0 0xff3f0000 0x0 0x10000
275				0x0 0xff634540 0x0 0x8>;
276			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
277			interrupt-names = "macirq";
278			clocks = <&clkc CLKID_ETH>,
279				 <&clkc CLKID_FCLK_DIV2>,
280				 <&clkc CLKID_MPLL2>;
281			clock-names = "stmmaceth", "clkin0", "clkin1";
282			status = "disabled";
283		};
284
285		gic: interrupt-controller@ffc01000 {
286			compatible = "arm,gic-400";
287			reg = <0x0 0xffc01000 0 0x1000>,
288			      <0x0 0xffc02000 0 0x2000>,
289			      <0x0 0xffc04000 0 0x2000>,
290			      <0x0 0xffc06000 0 0x2000>;
291			interrupt-controller;
292			interrupts = <GIC_PPI 9
293				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
294			#interrupt-cells = <3>;
295			#address-cells = <0>;
296		};
297
298		hiubus: bus@ff63c000 {
299			compatible = "simple-bus";
300			reg = <0x0 0xff63c000 0x0 0x1c00>;
301			#address-cells = <2>;
302			#size-cells = <2>;
303			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
304
305			sysctrl: system-controller@0 {
306				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
307				reg = <0 0 0 0x400>;
308
309				clkc: clock-controller {
310					compatible = "amlogic,axg-clkc";
311					#clock-cells = <1>;
312				};
313			};
314		};
315
316		mailbox: mailbox@ff63dc00 {
317			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
318			reg = <0 0xff63dc00 0 0x400>;
319			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
320				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
321				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
322			#mbox-cells = <1>;
323		};
324
325		periphs: periphs@ff634000 {
326			compatible = "simple-bus";
327			reg = <0x0 0xff634000 0x0 0x2000>;
328			#address-cells = <2>;
329			#size-cells = <2>;
330			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
331
332			hwrng: rng {
333				compatible = "amlogic,meson-rng";
334				reg = <0x0 0x18 0x0 0x4>;
335				clocks = <&clkc CLKID_RNG0>;
336				clock-names = "core";
337			};
338
339			pinctrl_periphs: pinctrl@480 {
340				compatible = "amlogic,meson-axg-periphs-pinctrl";
341				#address-cells = <2>;
342				#size-cells = <2>;
343				ranges;
344
345				gpio: bank@480 {
346					reg = <0x0 0x00480 0x0 0x40>,
347						<0x0 0x004e8 0x0 0x14>,
348						<0x0 0x00520 0x0 0x14>,
349						<0x0 0x00430 0x0 0x3c>;
350					reg-names = "mux", "pull", "pull-enable", "gpio";
351					gpio-controller;
352					#gpio-cells = <2>;
353					gpio-ranges = <&pinctrl_periphs 0 0 86>;
354				};
355
356				emmc_pins: emmc {
357					mux {
358						groups = "emmc_nand_d0",
359							"emmc_nand_d1",
360							"emmc_nand_d2",
361							"emmc_nand_d3",
362							"emmc_nand_d4",
363							"emmc_nand_d5",
364							"emmc_nand_d6",
365							"emmc_nand_d7",
366							"emmc_clk",
367							"emmc_cmd",
368							"emmc_ds";
369						function = "emmc";
370					};
371				};
372
373				emmc_clk_gate_pins: emmc_clk_gate {
374					mux {
375						groups = "BOOT_8";
376						function = "gpio_periphs";
377					};
378					cfg-pull-down {
379						pins = "BOOT_8";
380						bias-pull-down;
381					};
382				};
383
384				sdio_pins: sdio {
385					mux {
386						groups = "sdio_d0",
387							"sdio_d1",
388							"sdio_d2",
389							"sdio_d3",
390							"sdio_cmd",
391							"sdio_clk";
392						function = "sdio";
393					};
394				};
395
396				sdio_clk_gate_pins: sdio_clk_gate {
397					mux {
398						groups = "GPIOX_4";
399						function = "gpio_periphs";
400					};
401					cfg-pull-down {
402						pins = "GPIOX_4";
403						bias-pull-down;
404					};
405				};
406
407				eth_rmii_x_pins: eth-x-rmii {
408					mux {
409						groups = "eth_mdio_x",
410						       "eth_mdc_x",
411						       "eth_rgmii_rx_clk_x",
412						       "eth_rx_dv_x",
413						       "eth_rxd0_x",
414						       "eth_rxd1_x",
415						       "eth_txen_x",
416						       "eth_txd0_x",
417						       "eth_txd1_x";
418						function = "eth";
419					};
420				};
421
422				eth_rmii_y_pins: eth-y-rmii {
423					mux {
424						groups = "eth_mdio_y",
425						       "eth_mdc_y",
426						       "eth_rgmii_rx_clk_y",
427						       "eth_rx_dv_y",
428						       "eth_rxd0_y",
429						       "eth_rxd1_y",
430						       "eth_txen_y",
431						       "eth_txd0_y",
432						       "eth_txd1_y";
433						function = "eth";
434					};
435				};
436
437				eth_rgmii_x_pins: eth-x-rgmii {
438					mux {
439						groups = "eth_mdio_x",
440						       "eth_mdc_x",
441						       "eth_rgmii_rx_clk_x",
442						       "eth_rx_dv_x",
443						       "eth_rxd0_x",
444						       "eth_rxd1_x",
445						       "eth_rxd2_rgmii",
446						       "eth_rxd3_rgmii",
447						       "eth_rgmii_tx_clk",
448						       "eth_txen_x",
449						       "eth_txd0_x",
450						       "eth_txd1_x",
451						       "eth_txd2_rgmii",
452						       "eth_txd3_rgmii";
453						function = "eth";
454					};
455				};
456
457				eth_rgmii_y_pins: eth-y-rgmii {
458					mux {
459						groups = "eth_mdio_y",
460						       "eth_mdc_y",
461						       "eth_rgmii_rx_clk_y",
462						       "eth_rx_dv_y",
463						       "eth_rxd0_y",
464						       "eth_rxd1_y",
465						       "eth_rxd2_rgmii",
466						       "eth_rxd3_rgmii",
467						       "eth_rgmii_tx_clk",
468						       "eth_txen_y",
469						       "eth_txd0_y",
470						       "eth_txd1_y",
471						       "eth_txd2_rgmii",
472						       "eth_txd3_rgmii";
473						function = "eth";
474					};
475				};
476
477				pwm_a_a_pins: pwm_a_a {
478					mux {
479						groups = "pwm_a_a";
480						function = "pwm_a";
481					};
482				};
483
484				pwm_a_x18_pins: pwm_a_x18 {
485					mux {
486						groups = "pwm_a_x18";
487						function = "pwm_a";
488					};
489				};
490
491				pwm_a_x20_pins: pwm_a_x20 {
492					mux {
493						groups = "pwm_a_x20";
494						function = "pwm_a";
495					};
496				};
497
498				pwm_a_z_pins: pwm_a_z {
499					mux {
500						groups = "pwm_a_z";
501						function = "pwm_a";
502					};
503				};
504
505				pwm_b_a_pins: pwm_b_a {
506					mux {
507						groups = "pwm_b_a";
508						function = "pwm_b";
509					};
510				};
511
512				pwm_b_x_pins: pwm_b_x {
513					mux {
514						groups = "pwm_b_x";
515						function = "pwm_b";
516					};
517				};
518
519				pwm_b_z_pins: pwm_b_z {
520					mux {
521						groups = "pwm_b_z";
522						function = "pwm_b";
523					};
524				};
525
526				pwm_c_a_pins: pwm_c_a {
527					mux {
528						groups = "pwm_c_a";
529						function = "pwm_c";
530					};
531				};
532
533				pwm_c_x10_pins: pwm_c_x10 {
534					mux {
535						groups = "pwm_c_x10";
536						function = "pwm_c";
537					};
538				};
539
540				pwm_c_x17_pins: pwm_c_x17 {
541					mux {
542						groups = "pwm_c_x17";
543						function = "pwm_c";
544					};
545				};
546
547				pwm_d_x11_pins: pwm_d_x11 {
548					mux {
549						groups = "pwm_d_x11";
550						function = "pwm_d";
551					};
552				};
553
554				pwm_d_x16_pins: pwm_d_x16 {
555					mux {
556						groups = "pwm_d_x16";
557						function = "pwm_d";
558					};
559				};
560
561				spi0_pins: spi0 {
562					mux {
563						groups = "spi0_miso",
564							"spi0_mosi",
565							"spi0_clk";
566						function = "spi0";
567					};
568				};
569
570				spi0_ss0_pins: spi0_ss0 {
571					mux {
572						groups = "spi0_ss0";
573						function = "spi0";
574					};
575				};
576
577				spi0_ss1_pins: spi0_ss1 {
578					mux {
579						groups = "spi0_ss1";
580						function = "spi0";
581					};
582				};
583
584				spi0_ss2_pins: spi0_ss2 {
585					mux {
586						groups = "spi0_ss2";
587						function = "spi0";
588					};
589				};
590
591
592				spi1_a_pins: spi1_a {
593					mux {
594						groups = "spi1_miso_a",
595							"spi1_mosi_a",
596							"spi1_clk_a";
597						function = "spi1";
598					};
599				};
600
601				spi1_ss0_a_pins: spi1_ss0_a {
602					mux {
603						groups = "spi1_ss0_a";
604						function = "spi1";
605					};
606				};
607
608				spi1_ss1_pins: spi1_ss1 {
609					mux {
610						groups = "spi1_ss1";
611						function = "spi1";
612					};
613				};
614
615				spi1_x_pins: spi1_x {
616					mux {
617						groups = "spi1_miso_x",
618							"spi1_mosi_x",
619							"spi1_clk_x";
620						function = "spi1";
621					};
622				};
623
624				spi1_ss0_x_pins: spi1_ss0_x {
625					mux {
626						groups = "spi1_ss0_x";
627						function = "spi1";
628					};
629				};
630
631				i2c0_pins: i2c0 {
632					mux {
633						groups = "i2c0_sck",
634							"i2c0_sda";
635						function = "i2c0";
636					};
637				};
638
639				i2c1_z_pins: i2c1_z {
640					mux {
641						groups = "i2c1_sck_z",
642							"i2c1_sda_z";
643						function = "i2c1";
644					};
645				};
646
647				i2c1_x_pins: i2c1_x {
648					mux {
649						groups = "i2c1_sck_x",
650							"i2c1_sda_x";
651						function = "i2c1";
652					};
653				};
654
655				i2c2_x_pins: i2c2_x {
656					mux {
657						groups = "i2c2_sck_x",
658							"i2c2_sda_x";
659						function = "i2c2";
660					};
661				};
662
663				i2c2_a_pins: i2c2_a {
664					mux {
665						groups = "i2c2_sck_a",
666							"i2c2_sda_a";
667						function = "i2c2";
668					};
669				};
670
671				i2c3_a6_pins: i2c3_a6 {
672					mux {
673						groups = "i2c3_sda_a6",
674							"i2c3_sck_a7";
675						function = "i2c3";
676					};
677				};
678
679				i2c3_a12_pins: i2c3_a12 {
680					mux {
681						groups = "i2c3_sda_a12",
682							"i2c3_sck_a13";
683						function = "i2c3";
684					};
685				};
686
687				i2c3_a19_pins: i2c3_a19 {
688					mux {
689						groups = "i2c3_sda_a19",
690							"i2c3_sck_a20";
691						function = "i2c3";
692					};
693				};
694
695				uart_a_pins: uart_a {
696					mux {
697						groups = "uart_tx_a",
698							"uart_rx_a";
699						function = "uart_a";
700					};
701				};
702
703				uart_a_cts_rts_pins: uart_a_cts_rts {
704					mux {
705						groups = "uart_cts_a",
706							"uart_rts_a";
707						function = "uart_a";
708					};
709				};
710
711				uart_b_x_pins: uart_b_x {
712					mux {
713						groups = "uart_tx_b_x",
714							"uart_rx_b_x";
715						function = "uart_b";
716					};
717				};
718
719				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
720					mux {
721						groups = "uart_cts_b_x",
722							"uart_rts_b_x";
723						function = "uart_b";
724					};
725				};
726
727				uart_b_z_pins: uart_b_z {
728					mux {
729						groups = "uart_tx_b_z",
730							"uart_rx_b_z";
731						function = "uart_b";
732					};
733				};
734
735				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
736					mux {
737						groups = "uart_cts_b_z",
738							"uart_rts_b_z";
739						function = "uart_b";
740					};
741				};
742
743				uart_ao_b_z_pins: uart_ao_b_z {
744					mux {
745						groups = "uart_ao_tx_b_z",
746							"uart_ao_rx_b_z";
747						function = "uart_ao_b_z";
748					};
749				};
750
751				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
752					mux {
753						groups = "uart_ao_cts_b_z",
754							"uart_ao_rts_b_z";
755						function = "uart_ao_b_z";
756					};
757				};
758
759				mclk_b_pins: mclk_b {
760					mux {
761						groups = "mclk_b";
762						function = "mclk_b";
763					};
764				};
765
766				mclk_c_pins: mclk_c {
767					mux {
768						groups = "mclk_c";
769						function = "mclk_c";
770					};
771				};
772
773				tdma_sclk_pins: tdma_sclk {
774					mux {
775						groups = "tdma_sclk";
776						function = "tdma";
777					};
778				};
779
780				tdma_sclk_slv_pins: tdma_sclk_slv {
781					mux {
782						groups = "tdma_sclk_slv";
783						function = "tdma";
784					};
785				};
786
787				tdma_fs_pins: tdma_fs {
788					mux {
789						groups = "tdma_fs";
790						function = "tdma";
791					};
792				};
793
794				tdma_fs_slv_pins: tdma_fs_slv {
795					mux {
796						groups = "tdma_fs_slv";
797						function = "tdma";
798					};
799				};
800
801				tdma_din0_pins: tdma_din0 {
802					mux {
803						groups = "tdma_din0";
804						function = "tdma";
805					};
806				};
807
808				tdma_dout0_x14_pins: tdma_dout0_x14 {
809					mux {
810						groups = "tdma_dout0_x14";
811						function = "tdma";
812					};
813				};
814
815				tdma_dout0_x15_pins: tdma_dout0_x15 {
816					mux {
817						groups = "tdma_dout0_x15";
818						function = "tdma";
819					};
820				};
821
822				tdma_dout1_pins: tdma_dout1 {
823					mux {
824						groups = "tdma_dout1";
825						function = "tdma";
826					};
827				};
828
829				tdma_din1_pins: tdma_din1 {
830					mux {
831						groups = "tdma_din1";
832						function = "tdma";
833					};
834				};
835
836				tdmb_sclk_pins: tdmb_sclk {
837					mux {
838						groups = "tdmb_sclk";
839						function = "tdmb";
840					};
841				};
842
843				tdmb_sclk_slv_pins: tdmb_sclk_slv {
844					mux {
845						groups = "tdmb_sclk_slv";
846						function = "tdmb";
847					};
848				};
849
850				tdmb_fs_pins: tdmb_fs {
851					mux {
852						groups = "tdmb_fs";
853						function = "tdmb";
854					};
855				};
856
857				tdmb_fs_slv_pins: tdmb_fs_slv {
858					mux {
859						groups = "tdmb_fs_slv";
860						function = "tdmb";
861					};
862				};
863
864				tdmb_din0_pins: tdmb_din0 {
865					mux {
866						groups = "tdmb_din0";
867						function = "tdmb";
868					};
869				};
870
871				tdmb_dout0_pins: tdmb_dout0 {
872					mux {
873						groups = "tdmb_dout0";
874						function = "tdmb";
875					};
876				};
877
878				tdmb_din1_pins: tdmb_din1 {
879					mux {
880						groups = "tdmb_din1";
881						function = "tdmb";
882					};
883				};
884
885				tdmb_dout1_pins: tdmb_dout1 {
886					mux {
887						groups = "tdmb_dout1";
888						function = "tdmb";
889					};
890				};
891
892				tdmb_din2_pins: tdmb_din2 {
893					mux {
894						groups = "tdmb_din2";
895						function = "tdmb";
896					};
897				};
898
899				tdmb_dout2_pins: tdmb_dout2 {
900					mux {
901						groups = "tdmb_dout2";
902						function = "tdmb";
903					};
904				};
905
906				tdmb_din3_pins: tdmb_din3 {
907					mux {
908						groups = "tdmb_din3";
909						function = "tdmb";
910					};
911				};
912
913				tdmb_dout3_pins: tdmb_dout3 {
914					mux {
915						groups = "tdmb_dout3";
916						function = "tdmb";
917					};
918				};
919
920				tdmc_sclk_pins: tdmc_sclk {
921					mux {
922						groups = "tdmc_sclk";
923						function = "tdmc";
924					};
925				};
926
927				tdmc_sclk_slv_pins: tdmc_sclk_slv {
928					mux {
929						groups = "tdmc_sclk_slv";
930						function = "tdmc";
931					};
932				};
933
934				tdmc_fs_pins: tdmc_fs {
935					mux {
936						groups = "tdmc_fs";
937						function = "tdmc";
938					};
939				};
940
941				tdmc_fs_slv_pins: tdmc_fs_slv {
942					mux {
943						groups = "tdmc_fs_slv";
944						function = "tdmc";
945					};
946				};
947
948				tdmc_din0_pins: tdmc_din0 {
949					mux {
950						groups = "tdmc_din0";
951						function = "tdmc";
952					};
953				};
954
955				tdmc_dout0_pins: tdmc_dout0 {
956					mux {
957						groups = "tdmc_dout0";
958						function = "tdmc";
959					};
960				};
961
962				tdmc_din1_pins: tdmc_din1 {
963					mux {
964						groups = "tdmc_din1";
965						function = "tdmc";
966					};
967				};
968
969				tdmc_dout1_pins: tdmc_dout1 {
970					mux {
971						groups = "tdmc_dout1";
972						function = "tdmc";
973					};
974				};
975
976				tdmc_din2_pins: tdmc_din2 {
977					mux {
978						groups = "tdmc_din2";
979						function = "tdmc";
980					};
981				};
982
983				tdmc_dout2_pins: tdmc_dout2 {
984					mux {
985						groups = "tdmc_dout2";
986						function = "tdmc";
987					};
988				};
989
990				tdmc_din3_pins: tdmc_din3 {
991					mux {
992						groups = "tdmc_din3";
993						function = "tdmc";
994					};
995				};
996
997				tdmc_dout3_pins: tdmc_dout3 {
998					mux {
999						groups = "tdmc_dout3";
1000						function = "tdmc";
1001					};
1002				};
1003			};
1004		};
1005
1006		sram: sram@fffc0000 {
1007			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1008			reg = <0x0 0xfffc0000 0x0 0x20000>;
1009			#address-cells = <1>;
1010			#size-cells = <1>;
1011			ranges = <0 0x0 0xfffc0000 0x20000>;
1012
1013			cpu_scp_lpri: scp-shmem@0 {
1014				compatible = "amlogic,meson-axg-scp-shmem";
1015				reg = <0x13000 0x400>;
1016			};
1017
1018			cpu_scp_hpri: scp-shmem@200 {
1019				compatible = "amlogic,meson-axg-scp-shmem";
1020				reg = <0x13400 0x400>;
1021			};
1022		};
1023
1024		aobus: bus@ff800000 {
1025			compatible = "simple-bus";
1026			reg = <0x0 0xff800000 0x0 0x100000>;
1027			#address-cells = <2>;
1028			#size-cells = <2>;
1029			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1030
1031			pinctrl_aobus: pinctrl@14 {
1032				compatible = "amlogic,meson-axg-aobus-pinctrl";
1033				#address-cells = <2>;
1034				#size-cells = <2>;
1035				ranges;
1036
1037				gpio_ao: bank@14 {
1038					reg = <0x0 0x00014 0x0 0x8>,
1039						<0x0 0x0002c 0x0 0x4>,
1040						<0x0 0x00024 0x0 0x8>;
1041					reg-names = "mux", "pull", "gpio";
1042					gpio-controller;
1043					#gpio-cells = <2>;
1044					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1045				};
1046
1047				remote_input_ao_pins: remote_input_ao {
1048					mux {
1049						groups = "remote_input_ao";
1050						function = "remote_input_ao";
1051					};
1052				};
1053
1054				uart_ao_a_pins: uart_ao_a {
1055					mux {
1056						groups = "uart_ao_tx_a",
1057							"uart_ao_rx_a";
1058						function = "uart_ao_a";
1059					};
1060				};
1061
1062				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1063					mux {
1064						groups = "uart_ao_cts_a",
1065							"uart_ao_rts_a";
1066						function = "uart_ao_a";
1067					};
1068				};
1069
1070				uart_ao_b_pins: uart_ao_b {
1071					mux {
1072						groups = "uart_ao_tx_b",
1073							"uart_ao_rx_b";
1074						function = "uart_ao_b";
1075					};
1076				};
1077
1078				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1079					mux {
1080						groups = "uart_ao_cts_b",
1081							"uart_ao_rts_b";
1082						function = "uart_ao_b";
1083					};
1084				};
1085			};
1086
1087			sec_AO: ao-secure@140 {
1088				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1089				reg = <0x0 0x140 0x0 0x140>;
1090				amlogic,has-chip-id;
1091			};
1092
1093			pwm_AO_ab: pwm@7000 {
1094				compatible = "amlogic,meson-axg-ao-pwm";
1095				reg = <0x0 0x07000 0x0 0x20>;
1096				#pwm-cells = <3>;
1097				status = "disabled";
1098			};
1099
1100			pwm_AO_cd: pwm@2000 {
1101				compatible = "amlogic,meson-axg-ao-pwm";
1102				reg = <0x0 0x02000  0x0 0x20>;
1103				#pwm-cells = <3>;
1104				status = "disabled";
1105			};
1106
1107			i2c_AO: i2c@5000 {
1108				compatible = "amlogic,meson-axg-i2c";
1109				status = "disabled";
1110				reg = <0x0 0x05000 0x0 0x20>;
1111				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1112				#address-cells = <1>;
1113				#size-cells = <0>;
1114				clocks = <&clkc CLKID_I2C>;
1115				clock-names = "clk_i2c";
1116			};
1117
1118			uart_AO: serial@3000 {
1119				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1120				reg = <0x0 0x3000 0x0 0x18>;
1121				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1122				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1123				clock-names = "xtal", "pclk", "baud";
1124				status = "disabled";
1125			};
1126
1127			uart_AO_B: serial@4000 {
1128				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1129				reg = <0x0 0x4000 0x0 0x18>;
1130				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1131				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
1132				clock-names = "xtal", "pclk", "baud";
1133				status = "disabled";
1134			};
1135
1136			ir: ir@8000 {
1137				compatible = "amlogic,meson-gxbb-ir";
1138				reg = <0x0 0x8000 0x0 0x20>;
1139				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1140				status = "disabled";
1141			};
1142		};
1143	};
1144};
1145