1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15
16/ {
17	compatible = "amlogic,meson-axg";
18
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	tdmif_a: audio-controller-0 {
24		compatible = "amlogic,axg-tdm-iface";
25		#sound-dai-cells = <0>;
26		sound-name-prefix = "TDM_A";
27		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30		clock-names = "mclk", "sclk", "lrclk";
31		status = "disabled";
32	};
33
34	tdmif_b: audio-controller-1 {
35		compatible = "amlogic,axg-tdm-iface";
36		#sound-dai-cells = <0>;
37		sound-name-prefix = "TDM_B";
38		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41		clock-names = "mclk", "sclk", "lrclk";
42		status = "disabled";
43	};
44
45	tdmif_c: audio-controller-2 {
46		compatible = "amlogic,axg-tdm-iface";
47		#sound-dai-cells = <0>;
48		sound-name-prefix = "TDM_C";
49		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52		clock-names = "mclk", "sclk", "lrclk";
53		status = "disabled";
54	};
55
56	ao_alt_xtal: ao_alt_xtal-clk {
57		compatible = "fixed-clock";
58		clock-frequency = <32000000>;
59		clock-output-names = "ao_alt_xtal";
60		#clock-cells = <0>;
61	};
62
63	arm-pmu {
64		compatible = "arm,cortex-a53-pmu";
65		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
66			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
67			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
68			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
69		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
70	};
71
72	cpus {
73		#address-cells = <0x2>;
74		#size-cells = <0x0>;
75
76		cpu0: cpu@0 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a53", "arm,armv8";
79			reg = <0x0 0x0>;
80			enable-method = "psci";
81			next-level-cache = <&l2>;
82			clocks = <&scpi_dvfs 0>;
83		};
84
85		cpu1: cpu@1 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a53", "arm,armv8";
88			reg = <0x0 0x1>;
89			enable-method = "psci";
90			next-level-cache = <&l2>;
91			clocks = <&scpi_dvfs 0>;
92		};
93
94		cpu2: cpu@2 {
95			device_type = "cpu";
96			compatible = "arm,cortex-a53", "arm,armv8";
97			reg = <0x0 0x2>;
98			enable-method = "psci";
99			next-level-cache = <&l2>;
100			clocks = <&scpi_dvfs 0>;
101		};
102
103		cpu3: cpu@3 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a53", "arm,armv8";
106			reg = <0x0 0x3>;
107			enable-method = "psci";
108			next-level-cache = <&l2>;
109			clocks = <&scpi_dvfs 0>;
110		};
111
112		l2: l2-cache0 {
113			compatible = "cache";
114		};
115	};
116
117	sm: secure-monitor {
118		compatible = "amlogic,meson-gxbb-sm";
119	};
120
121	psci {
122		compatible = "arm,psci-1.0";
123		method = "smc";
124	};
125
126	reserved-memory {
127		#address-cells = <2>;
128		#size-cells = <2>;
129		ranges;
130
131		/* 16 MiB reserved for Hardware ROM Firmware */
132		hwrom_reserved: hwrom@0 {
133			reg = <0x0 0x0 0x0 0x1000000>;
134			no-map;
135		};
136
137		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
138		secmon_reserved: secmon@5000000 {
139			reg = <0x0 0x05000000 0x0 0x300000>;
140			no-map;
141		};
142	};
143
144	scpi {
145		compatible = "arm,scpi-pre-1.0";
146		mboxes = <&mailbox 1 &mailbox 2>;
147		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
148
149		scpi_clocks: clocks {
150			compatible = "arm,scpi-clocks";
151
152			scpi_dvfs: clock-controller {
153				compatible = "arm,scpi-dvfs-clocks";
154				#clock-cells = <1>;
155				clock-indices = <0>;
156				clock-output-names = "vcpu";
157			};
158		};
159
160		scpi_sensors: sensors {
161			compatible = "amlogic,meson-gxbb-scpi-sensors";
162			#thermal-sensor-cells = <1>;
163		};
164	};
165
166	soc {
167		compatible = "simple-bus";
168		#address-cells = <2>;
169		#size-cells = <2>;
170		ranges;
171
172		ethmac: ethernet@ff3f0000 {
173			compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
174			reg = <0x0 0xff3f0000 0x0 0x10000
175			       0x0 0xff634540 0x0 0x8>;
176			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
177			interrupt-names = "macirq";
178			clocks = <&clkc CLKID_ETH>,
179				 <&clkc CLKID_FCLK_DIV2>,
180				 <&clkc CLKID_MPLL2>;
181			clock-names = "stmmaceth", "clkin0", "clkin1";
182			status = "disabled";
183		};
184
185		pdm: audio-controller@ff632000 {
186			compatible = "amlogic,axg-pdm";
187			reg = <0x0 0xff632000 0x0 0x34>;
188			#sound-dai-cells = <0>;
189			sound-name-prefix = "PDM";
190			clocks = <&clkc_audio AUD_CLKID_PDM>,
191				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
192				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
193			clock-names = "pclk", "dclk", "sysclk";
194			status = "disabled";
195		};
196
197		periphs: bus@ff634000 {
198			compatible = "simple-bus";
199			reg = <0x0 0xff634000 0x0 0x2000>;
200			#address-cells = <2>;
201			#size-cells = <2>;
202			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
203
204			hwrng: rng@18 {
205				compatible = "amlogic,meson-rng";
206				reg = <0x0 0x18 0x0 0x4>;
207				clocks = <&clkc CLKID_RNG0>;
208				clock-names = "core";
209			};
210
211			pinctrl_periphs: pinctrl@480 {
212				compatible = "amlogic,meson-axg-periphs-pinctrl";
213				#address-cells = <2>;
214				#size-cells = <2>;
215				ranges;
216
217				gpio: bank@480 {
218					reg = <0x0 0x00480 0x0 0x40>,
219					      <0x0 0x004e8 0x0 0x14>,
220					      <0x0 0x00520 0x0 0x14>,
221					      <0x0 0x00430 0x0 0x3c>;
222					reg-names = "mux", "pull", "pull-enable", "gpio";
223					gpio-controller;
224					#gpio-cells = <2>;
225					gpio-ranges = <&pinctrl_periphs 0 0 86>;
226				};
227
228				i2c0_pins: i2c0 {
229					mux {
230						groups = "i2c0_sck",
231							 "i2c0_sda";
232						function = "i2c0";
233					};
234				};
235
236				i2c1_x_pins: i2c1_x {
237					mux {
238						groups = "i2c1_sck_x",
239							 "i2c1_sda_x";
240						function = "i2c1";
241					};
242				};
243
244				i2c1_z_pins: i2c1_z {
245					mux {
246						groups = "i2c1_sck_z",
247							 "i2c1_sda_z";
248						function = "i2c1";
249					};
250				};
251
252				i2c2_a_pins: i2c2_a {
253					mux {
254						groups = "i2c2_sck_a",
255							 "i2c2_sda_a";
256						function = "i2c2";
257					};
258				};
259
260				i2c2_x_pins: i2c2_x {
261					mux {
262						groups = "i2c2_sck_x",
263							 "i2c2_sda_x";
264						function = "i2c2";
265					};
266				};
267
268				i2c3_a6_pins: i2c3_a6 {
269					mux {
270						groups = "i2c3_sda_a6",
271							 "i2c3_sck_a7";
272						function = "i2c3";
273					};
274				};
275
276				i2c3_a12_pins: i2c3_a12 {
277					mux {
278						groups = "i2c3_sda_a12",
279							 "i2c3_sck_a13";
280						function = "i2c3";
281					};
282				};
283
284				i2c3_a19_pins: i2c3_a19 {
285					mux {
286						groups = "i2c3_sda_a19",
287							 "i2c3_sck_a20";
288						function = "i2c3";
289					};
290				};
291
292				emmc_pins: emmc {
293					mux {
294						groups = "emmc_nand_d0",
295							 "emmc_nand_d1",
296							 "emmc_nand_d2",
297							 "emmc_nand_d3",
298							 "emmc_nand_d4",
299							 "emmc_nand_d5",
300							 "emmc_nand_d6",
301							 "emmc_nand_d7",
302							 "emmc_clk",
303							 "emmc_cmd",
304							 "emmc_ds";
305						function = "emmc";
306					};
307				};
308
309				emmc_clk_gate_pins: emmc_clk_gate {
310					mux {
311						groups = "BOOT_8";
312						function = "gpio_periphs";
313						bias-pull-down;
314					};
315				};
316
317				eth_rgmii_x_pins: eth-x-rgmii {
318					mux {
319						groups = "eth_mdio_x",
320							 "eth_mdc_x",
321							 "eth_rgmii_rx_clk_x",
322							 "eth_rx_dv_x",
323							 "eth_rxd0_x",
324							 "eth_rxd1_x",
325							 "eth_rxd2_rgmii",
326							 "eth_rxd3_rgmii",
327							 "eth_rgmii_tx_clk",
328							 "eth_txen_x",
329							 "eth_txd0_x",
330							 "eth_txd1_x",
331							 "eth_txd2_rgmii",
332							 "eth_txd3_rgmii";
333						function = "eth";
334					};
335				};
336
337				eth_rgmii_y_pins: eth-y-rgmii {
338					mux {
339						groups = "eth_mdio_y",
340							 "eth_mdc_y",
341							 "eth_rgmii_rx_clk_y",
342							 "eth_rx_dv_y",
343							 "eth_rxd0_y",
344							 "eth_rxd1_y",
345							 "eth_rxd2_rgmii",
346							 "eth_rxd3_rgmii",
347							 "eth_rgmii_tx_clk",
348							 "eth_txen_y",
349							 "eth_txd0_y",
350							 "eth_txd1_y",
351							 "eth_txd2_rgmii",
352							 "eth_txd3_rgmii";
353						function = "eth";
354					};
355				};
356
357				eth_rmii_x_pins: eth-x-rmii {
358					mux {
359						groups = "eth_mdio_x",
360							 "eth_mdc_x",
361							 "eth_rgmii_rx_clk_x",
362							 "eth_rx_dv_x",
363							 "eth_rxd0_x",
364							 "eth_rxd1_x",
365							 "eth_txen_x",
366							 "eth_txd0_x",
367							 "eth_txd1_x";
368						function = "eth";
369					};
370				};
371
372				eth_rmii_y_pins: eth-y-rmii {
373					mux {
374						groups = "eth_mdio_y",
375							 "eth_mdc_y",
376							 "eth_rgmii_rx_clk_y",
377							 "eth_rx_dv_y",
378							 "eth_rxd0_y",
379							 "eth_rxd1_y",
380							 "eth_txen_y",
381							 "eth_txd0_y",
382							 "eth_txd1_y";
383						function = "eth";
384					};
385				};
386
387				mclk_b_pins: mclk_b {
388					mux {
389						groups = "mclk_b";
390						function = "mclk_b";
391					};
392				};
393
394				mclk_c_pins: mclk_c {
395					mux {
396						groups = "mclk_c";
397						function = "mclk_c";
398					};
399				};
400
401				pdm_dclk_a14_pins: pdm_dclk_a14 {
402					mux {
403						groups = "pdm_dclk_a14";
404						function = "pdm";
405					};
406				};
407
408				pdm_dclk_a19_pins: pdm_dclk_a19 {
409					mux {
410						groups = "pdm_dclk_a19";
411						function = "pdm";
412					};
413				};
414
415				pdm_din0_pins: pdm_din0 {
416					mux {
417						groups = "pdm_din0";
418						function = "pdm";
419					};
420				};
421
422				pdm_din1_pins: pdm_din1 {
423					mux {
424						groups = "pdm_din1";
425						function = "pdm";
426					};
427				};
428
429				pdm_din2_pins: pdm_din2 {
430					mux {
431						groups = "pdm_din2";
432						function = "pdm";
433					};
434				};
435
436				pdm_din3_pins: pdm_din3 {
437					mux {
438						groups = "pdm_din3";
439						function = "pdm";
440					};
441				};
442
443				pwm_a_a_pins: pwm_a_a {
444					mux {
445						groups = "pwm_a_a";
446						function = "pwm_a";
447					};
448				};
449
450				pwm_a_x18_pins: pwm_a_x18 {
451					mux {
452						groups = "pwm_a_x18";
453						function = "pwm_a";
454					};
455				};
456
457				pwm_a_x20_pins: pwm_a_x20 {
458					mux {
459						groups = "pwm_a_x20";
460						function = "pwm_a";
461					};
462				};
463
464				pwm_a_z_pins: pwm_a_z {
465					mux {
466						groups = "pwm_a_z";
467						function = "pwm_a";
468					};
469				};
470
471				pwm_b_a_pins: pwm_b_a {
472					mux {
473						groups = "pwm_b_a";
474						function = "pwm_b";
475					};
476				};
477
478				pwm_b_x_pins: pwm_b_x {
479					mux {
480						groups = "pwm_b_x";
481						function = "pwm_b";
482					};
483				};
484
485				pwm_b_z_pins: pwm_b_z {
486					mux {
487						groups = "pwm_b_z";
488						function = "pwm_b";
489					};
490				};
491
492				pwm_c_a_pins: pwm_c_a {
493					mux {
494						groups = "pwm_c_a";
495						function = "pwm_c";
496					};
497				};
498
499				pwm_c_x10_pins: pwm_c_x10 {
500					mux {
501						groups = "pwm_c_x10";
502						function = "pwm_c";
503					};
504				};
505
506				pwm_c_x17_pins: pwm_c_x17 {
507					mux {
508						groups = "pwm_c_x17";
509						function = "pwm_c";
510					};
511				};
512
513				pwm_d_x11_pins: pwm_d_x11 {
514					mux {
515						groups = "pwm_d_x11";
516						function = "pwm_d";
517					};
518				};
519
520				pwm_d_x16_pins: pwm_d_x16 {
521					mux {
522						groups = "pwm_d_x16";
523						function = "pwm_d";
524					};
525				};
526
527				sdio_pins: sdio {
528					mux {
529						groups = "sdio_d0",
530							 "sdio_d1",
531							 "sdio_d2",
532							 "sdio_d3",
533							 "sdio_cmd",
534							 "sdio_clk";
535						function = "sdio";
536					};
537				};
538
539				sdio_clk_gate_pins: sdio_clk_gate {
540					mux {
541						groups = "GPIOX_4";
542						function = "gpio_periphs";
543						bias-pull-down;
544					};
545				};
546
547				spdif_in_z_pins: spdif_in_z {
548					mux {
549						groups = "spdif_in_z";
550						function = "spdif_in";
551					};
552				};
553
554				spdif_in_a1_pins: spdif_in_a1 {
555					mux {
556						groups = "spdif_in_a1";
557						function = "spdif_in";
558					};
559				};
560
561				spdif_in_a7_pins: spdif_in_a7 {
562					mux {
563						groups = "spdif_in_a7";
564						function = "spdif_in";
565					};
566				};
567
568				spdif_in_a19_pins: spdif_in_a19 {
569					mux {
570						groups = "spdif_in_a19";
571						function = "spdif_in";
572					};
573				};
574
575				spdif_in_a20_pins: spdif_in_a20 {
576					mux {
577						groups = "spdif_in_a20";
578						function = "spdif_in";
579					};
580				};
581
582				spdif_out_a1_pins: spdif_out_a1 {
583					mux {
584						groups = "spdif_out_a1";
585						function = "spdif_out";
586					};
587				};
588
589				spdif_out_a11_pins: spdif_out_a11 {
590					mux {
591						groups = "spdif_out_a11";
592						function = "spdif_out";
593					};
594				};
595
596				spdif_out_a19_pins: spdif_out_a19 {
597					mux {
598						groups = "spdif_out_a19";
599						function = "spdif_out";
600					};
601				};
602
603				spdif_out_a20_pins: spdif_out_a20 {
604					mux {
605						groups = "spdif_out_a20";
606						function = "spdif_out";
607					};
608				};
609
610				spdif_out_z_pins: spdif_out_z {
611					mux {
612						groups = "spdif_out_z";
613						function = "spdif_out";
614					};
615				};
616
617				spi0_pins: spi0 {
618					mux {
619						groups = "spi0_miso",
620							 "spi0_mosi",
621							 "spi0_clk";
622						function = "spi0";
623					};
624				};
625
626				spi0_ss0_pins: spi0_ss0 {
627					mux {
628						groups = "spi0_ss0";
629						function = "spi0";
630					};
631				};
632
633				spi0_ss1_pins: spi0_ss1 {
634					mux {
635						groups = "spi0_ss1";
636						function = "spi0";
637					};
638				};
639
640				spi0_ss2_pins: spi0_ss2 {
641					mux {
642						groups = "spi0_ss2";
643						function = "spi0";
644					};
645				};
646
647				spi1_a_pins: spi1_a {
648					mux {
649						groups = "spi1_miso_a",
650							 "spi1_mosi_a",
651							 "spi1_clk_a";
652						function = "spi1";
653					};
654				};
655
656				spi1_ss0_a_pins: spi1_ss0_a {
657					mux {
658						groups = "spi1_ss0_a";
659						function = "spi1";
660					};
661				};
662
663				spi1_ss1_pins: spi1_ss1 {
664					mux {
665						groups = "spi1_ss1";
666						function = "spi1";
667					};
668				};
669
670				spi1_x_pins: spi1_x {
671					mux {
672						groups = "spi1_miso_x",
673							 "spi1_mosi_x",
674							 "spi1_clk_x";
675						function = "spi1";
676					};
677				};
678
679				spi1_ss0_x_pins: spi1_ss0_x {
680					mux {
681						groups = "spi1_ss0_x";
682						function = "spi1";
683					};
684				};
685
686				tdma_din0_pins: tdma_din0 {
687					mux {
688						groups = "tdma_din0";
689						function = "tdma";
690					};
691				};
692
693				tdma_dout0_x14_pins: tdma_dout0_x14 {
694					mux {
695						groups = "tdma_dout0_x14";
696						function = "tdma";
697					};
698				};
699
700				tdma_dout0_x15_pins: tdma_dout0_x15 {
701					mux {
702						groups = "tdma_dout0_x15";
703						function = "tdma";
704					};
705				};
706
707				tdma_dout1_pins: tdma_dout1 {
708					mux {
709						groups = "tdma_dout1";
710						function = "tdma";
711					};
712				};
713
714				tdma_din1_pins: tdma_din1 {
715					mux {
716						groups = "tdma_din1";
717						function = "tdma";
718					};
719				};
720
721				tdma_fs_pins: tdma_fs {
722					mux {
723						groups = "tdma_fs";
724						function = "tdma";
725					};
726				};
727
728				tdma_fs_slv_pins: tdma_fs_slv {
729					mux {
730						groups = "tdma_fs_slv";
731						function = "tdma";
732					};
733				};
734
735				tdma_sclk_pins: tdma_sclk {
736					mux {
737						groups = "tdma_sclk";
738						function = "tdma";
739					};
740				};
741
742				tdma_sclk_slv_pins: tdma_sclk_slv {
743					mux {
744						groups = "tdma_sclk_slv";
745						function = "tdma";
746					};
747				};
748
749				tdmb_din0_pins: tdmb_din0 {
750					mux {
751						groups = "tdmb_din0";
752						function = "tdmb";
753					};
754				};
755
756				tdmb_din1_pins: tdmb_din1 {
757					mux {
758						groups = "tdmb_din1";
759						function = "tdmb";
760					};
761				};
762
763				tdmb_din2_pins: tdmb_din2 {
764					mux {
765						groups = "tdmb_din2";
766						function = "tdmb";
767					};
768				};
769
770				tdmb_din3_pins: tdmb_din3 {
771					mux {
772						groups = "tdmb_din3";
773						function = "tdmb";
774					};
775				};
776
777				tdmb_dout0_pins: tdmb_dout0 {
778					mux {
779						groups = "tdmb_dout0";
780						function = "tdmb";
781					};
782				};
783
784				tdmb_dout1_pins: tdmb_dout1 {
785					mux {
786						groups = "tdmb_dout1";
787						function = "tdmb";
788					};
789				};
790
791				tdmb_dout2_pins: tdmb_dout2 {
792					mux {
793						groups = "tdmb_dout2";
794						function = "tdmb";
795					};
796				};
797
798				tdmb_dout3_pins: tdmb_dout3 {
799					mux {
800						groups = "tdmb_dout3";
801						function = "tdmb";
802					};
803				};
804
805				tdmb_fs_pins: tdmb_fs {
806					mux {
807						groups = "tdmb_fs";
808						function = "tdmb";
809					};
810				};
811
812				tdmb_fs_slv_pins: tdmb_fs_slv {
813					mux {
814						groups = "tdmb_fs_slv";
815						function = "tdmb";
816					};
817				};
818
819				tdmb_sclk_pins: tdmb_sclk {
820					mux {
821						groups = "tdmb_sclk";
822						function = "tdmb";
823					};
824				};
825
826				tdmb_sclk_slv_pins: tdmb_sclk_slv {
827					mux {
828						groups = "tdmb_sclk_slv";
829						function = "tdmb";
830					};
831				};
832
833				tdmc_fs_pins: tdmc_fs {
834					mux {
835						groups = "tdmc_fs";
836						function = "tdmc";
837					};
838				};
839
840				tdmc_fs_slv_pins: tdmc_fs_slv {
841					mux {
842						groups = "tdmc_fs_slv";
843						function = "tdmc";
844					};
845				};
846
847				tdmc_sclk_pins: tdmc_sclk {
848					mux {
849						groups = "tdmc_sclk";
850						function = "tdmc";
851					};
852				};
853
854				tdmc_sclk_slv_pins: tdmc_sclk_slv {
855					mux {
856						groups = "tdmc_sclk_slv";
857						function = "tdmc";
858					};
859				};
860
861				tdmc_din0_pins: tdmc_din0 {
862					mux {
863						groups = "tdmc_din0";
864						function = "tdmc";
865					};
866				};
867
868				tdmc_din1_pins: tdmc_din1 {
869					mux {
870						groups = "tdmc_din1";
871						function = "tdmc";
872					};
873				};
874
875				tdmc_din2_pins: tdmc_din2 {
876					mux {
877						groups = "tdmc_din2";
878						function = "tdmc";
879					};
880				};
881
882				tdmc_din3_pins: tdmc_din3 {
883					mux {
884						groups = "tdmc_din3";
885						function = "tdmc";
886					};
887				};
888
889				tdmc_dout0_pins: tdmc_dout0 {
890					mux {
891						groups = "tdmc_dout0";
892						function = "tdmc";
893					};
894				};
895
896				tdmc_dout1_pins: tdmc_dout1 {
897					mux {
898						groups = "tdmc_dout1";
899						function = "tdmc";
900					};
901				};
902
903				tdmc_dout2_pins: tdmc_dout2 {
904					mux {
905						groups = "tdmc_dout2";
906						function = "tdmc";
907					};
908				};
909
910				tdmc_dout3_pins: tdmc_dout3 {
911					mux {
912						groups = "tdmc_dout3";
913						function = "tdmc";
914					};
915				};
916
917				uart_a_pins: uart_a {
918					mux {
919						groups = "uart_tx_a",
920							 "uart_rx_a";
921						function = "uart_a";
922					};
923				};
924
925				uart_a_cts_rts_pins: uart_a_cts_rts {
926					mux {
927						groups = "uart_cts_a",
928							 "uart_rts_a";
929						function = "uart_a";
930					};
931				};
932
933				uart_b_x_pins: uart_b_x {
934					mux {
935						groups = "uart_tx_b_x",
936							 "uart_rx_b_x";
937						function = "uart_b";
938					};
939				};
940
941				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
942					mux {
943						groups = "uart_cts_b_x",
944							 "uart_rts_b_x";
945						function = "uart_b";
946					};
947				};
948
949				uart_b_z_pins: uart_b_z {
950					mux {
951						groups = "uart_tx_b_z",
952							 "uart_rx_b_z";
953						function = "uart_b";
954					};
955				};
956
957				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
958					mux {
959						groups = "uart_cts_b_z",
960							 "uart_rts_b_z";
961						function = "uart_b";
962					};
963				};
964
965				uart_ao_b_z_pins: uart_ao_b_z {
966					mux {
967						groups = "uart_ao_tx_b_z",
968							 "uart_ao_rx_b_z";
969						function = "uart_ao_b_z";
970					};
971				};
972
973				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
974					mux {
975						groups = "uart_ao_cts_b_z",
976							 "uart_ao_rts_b_z";
977						function = "uart_ao_b_z";
978					};
979				};
980			};
981		};
982
983		hiubus: bus@ff63c000 {
984			compatible = "simple-bus";
985			reg = <0x0 0xff63c000 0x0 0x1c00>;
986			#address-cells = <2>;
987			#size-cells = <2>;
988			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
989
990			sysctrl: system-controller@0 {
991				compatible = "amlogic,meson-axg-hhi-sysctrl",
992					     "simple-mfd", "syscon";
993				reg = <0 0 0 0x400>;
994
995				clkc: clock-controller {
996					compatible = "amlogic,axg-clkc";
997					#clock-cells = <1>;
998				};
999			};
1000		};
1001
1002		mailbox: mailbox@ff63c404 {
1003			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1004			reg = <0 0xff63c404 0 0x4c>;
1005			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1006				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1007				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1008			#mbox-cells = <1>;
1009		};
1010
1011		audio: bus@ff642000 {
1012			compatible = "simple-bus";
1013			reg = <0x0 0xff642000 0x0 0x2000>;
1014			#address-cells = <2>;
1015			#size-cells = <2>;
1016			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1017
1018			clkc_audio: clock-controller@0 {
1019				compatible = "amlogic,axg-audio-clkc";
1020				reg = <0x0 0x0 0x0 0xb4>;
1021				#clock-cells = <1>;
1022
1023				clocks = <&clkc CLKID_AUDIO>,
1024					 <&clkc CLKID_MPLL0>,
1025					 <&clkc CLKID_MPLL1>,
1026					 <&clkc CLKID_MPLL2>,
1027					 <&clkc CLKID_MPLL3>,
1028					 <&clkc CLKID_HIFI_PLL>,
1029					 <&clkc CLKID_FCLK_DIV3>,
1030					 <&clkc CLKID_FCLK_DIV4>,
1031					 <&clkc CLKID_GP0_PLL>;
1032				clock-names = "pclk",
1033					      "mst_in0",
1034					      "mst_in1",
1035					      "mst_in2",
1036					      "mst_in3",
1037					      "mst_in4",
1038					      "mst_in5",
1039					      "mst_in6",
1040					      "mst_in7";
1041
1042				resets = <&reset RESET_AUDIO>;
1043			};
1044
1045			toddr_a: audio-controller@100 {
1046				compatible = "amlogic,axg-toddr";
1047				reg = <0x0 0x100 0x0 0x1c>;
1048				#sound-dai-cells = <0>;
1049				sound-name-prefix = "TODDR_A";
1050				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1051				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1052				resets = <&arb AXG_ARB_TODDR_A>;
1053				status = "disabled";
1054			};
1055
1056			toddr_b: audio-controller@140 {
1057				compatible = "amlogic,axg-toddr";
1058				reg = <0x0 0x140 0x0 0x1c>;
1059				#sound-dai-cells = <0>;
1060				sound-name-prefix = "TODDR_B";
1061				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1062				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1063				resets = <&arb AXG_ARB_TODDR_B>;
1064				status = "disabled";
1065			};
1066
1067			toddr_c: audio-controller@180 {
1068				compatible = "amlogic,axg-toddr";
1069				reg = <0x0 0x180 0x0 0x1c>;
1070				#sound-dai-cells = <0>;
1071				sound-name-prefix = "TODDR_C";
1072				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1073				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1074				resets = <&arb AXG_ARB_TODDR_C>;
1075				status = "disabled";
1076			};
1077
1078			frddr_a: audio-controller@1c0 {
1079				compatible = "amlogic,axg-frddr";
1080				reg = <0x0 0x1c0 0x0 0x1c>;
1081				#sound-dai-cells = <0>;
1082				sound-name-prefix = "FRDDR_A";
1083				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1084				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1085				resets = <&arb AXG_ARB_FRDDR_A>;
1086				status = "disabled";
1087			};
1088
1089			frddr_b: audio-controller@200 {
1090				compatible = "amlogic,axg-frddr";
1091				reg = <0x0 0x200 0x0 0x1c>;
1092				#sound-dai-cells = <0>;
1093				sound-name-prefix = "FRDDR_B";
1094				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1095				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1096				resets = <&arb AXG_ARB_FRDDR_B>;
1097				status = "disabled";
1098			};
1099
1100			frddr_c: audio-controller@240 {
1101				compatible = "amlogic,axg-frddr";
1102				reg = <0x0 0x240 0x0 0x1c>;
1103				#sound-dai-cells = <0>;
1104				sound-name-prefix = "FRDDR_C";
1105				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1106				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1107				resets = <&arb AXG_ARB_FRDDR_C>;
1108				status = "disabled";
1109			};
1110
1111			arb: reset-controller@280 {
1112				compatible = "amlogic,meson-axg-audio-arb";
1113				reg = <0x0 0x280 0x0 0x4>;
1114				#reset-cells = <1>;
1115				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1116			};
1117
1118			tdmin_a: audio-controller@300 {
1119				compatible = "amlogic,axg-tdmin";
1120				reg = <0x0 0x300 0x0 0x40>;
1121				sound-name-prefix = "TDMIN_A";
1122				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1123					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1124					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1125					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1126					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1127				clock-names = "pclk", "sclk", "sclk_sel",
1128					      "lrclk", "lrclk_sel";
1129				status = "disabled";
1130			};
1131
1132			tdmin_b: audio-controller@340 {
1133				compatible = "amlogic,axg-tdmin";
1134				reg = <0x0 0x340 0x0 0x40>;
1135				sound-name-prefix = "TDMIN_B";
1136				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1137					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1138					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1139					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1140					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1141				clock-names = "pclk", "sclk", "sclk_sel",
1142					      "lrclk", "lrclk_sel";
1143				status = "disabled";
1144			};
1145
1146			tdmin_c: audio-controller@380 {
1147				compatible = "amlogic,axg-tdmin";
1148				reg = <0x0 0x380 0x0 0x40>;
1149				sound-name-prefix = "TDMIN_C";
1150				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1151					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1152					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1153					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1154					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1155				clock-names = "pclk", "sclk", "sclk_sel",
1156					      "lrclk", "lrclk_sel";
1157				status = "disabled";
1158			};
1159
1160			tdmin_lb: audio-controller@3c0 {
1161				compatible = "amlogic,axg-tdmin";
1162				reg = <0x0 0x3c0 0x0 0x40>;
1163				sound-name-prefix = "TDMIN_LB";
1164				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1165					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1166					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1167					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1168					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1169				clock-names = "pclk", "sclk", "sclk_sel",
1170					      "lrclk", "lrclk_sel";
1171				status = "disabled";
1172			};
1173
1174			spdifout: audio-controller@480 {
1175				compatible = "amlogic,axg-spdifout";
1176				reg = <0x0 0x480 0x0 0x50>;
1177				#sound-dai-cells = <0>;
1178				sound-name-prefix = "SPDIFOUT";
1179				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1180					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1181				clock-names = "pclk", "mclk";
1182				status = "disabled";
1183			};
1184
1185			tdmout_a: audio-controller@500 {
1186				compatible = "amlogic,axg-tdmout";
1187				reg = <0x0 0x500 0x0 0x40>;
1188				sound-name-prefix = "TDMOUT_A";
1189				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1190					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1191					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1192					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1193					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1194				clock-names = "pclk", "sclk", "sclk_sel",
1195					      "lrclk", "lrclk_sel";
1196				status = "disabled";
1197			};
1198
1199			tdmout_b: audio-controller@540 {
1200				compatible = "amlogic,axg-tdmout";
1201				reg = <0x0 0x540 0x0 0x40>;
1202				sound-name-prefix = "TDMOUT_B";
1203				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1204					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1205					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1206					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1207					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1208				clock-names = "pclk", "sclk", "sclk_sel",
1209					      "lrclk", "lrclk_sel";
1210				status = "disabled";
1211			};
1212
1213			tdmout_c: audio-controller@580 {
1214				compatible = "amlogic,axg-tdmout";
1215				reg = <0x0 0x580 0x0 0x40>;
1216				sound-name-prefix = "TDMOUT_C";
1217				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1218					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1219					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1220					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1221					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1222				clock-names = "pclk", "sclk", "sclk_sel",
1223					      "lrclk", "lrclk_sel";
1224				status = "disabled";
1225			};
1226		};
1227
1228		aobus: bus@ff800000 {
1229			compatible = "simple-bus";
1230			reg = <0x0 0xff800000 0x0 0x100000>;
1231			#address-cells = <2>;
1232			#size-cells = <2>;
1233			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1234
1235			sysctrl_AO: sys-ctrl@0 {
1236				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1237				reg =  <0x0 0x0 0x0 0x100>;
1238
1239				clkc_AO: clock-controller {
1240					compatible = "amlogic,meson-axg-aoclkc";
1241					#clock-cells = <1>;
1242					#reset-cells = <1>;
1243				};
1244			};
1245
1246			pinctrl_aobus: pinctrl@14 {
1247				compatible = "amlogic,meson-axg-aobus-pinctrl";
1248				#address-cells = <2>;
1249				#size-cells = <2>;
1250				ranges;
1251
1252				gpio_ao: bank@14 {
1253					reg = <0x0 0x00014 0x0 0x8>,
1254					      <0x0 0x0002c 0x0 0x4>,
1255					      <0x0 0x00024 0x0 0x8>;
1256					reg-names = "mux", "pull", "gpio";
1257					gpio-controller;
1258					#gpio-cells = <2>;
1259					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1260				};
1261
1262				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1263					mux {
1264						groups = "i2c_ao_sck_4";
1265						function = "i2c_ao";
1266					};
1267				};
1268
1269				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1270					mux {
1271						groups = "i2c_ao_sck_8";
1272						function = "i2c_ao";
1273					};
1274				};
1275
1276				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1277					mux {
1278						groups = "i2c_ao_sck_10";
1279						function = "i2c_ao";
1280					};
1281				};
1282
1283				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1284					mux {
1285						groups = "i2c_ao_sda_5";
1286						function = "i2c_ao";
1287					};
1288				};
1289
1290				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1291					mux {
1292						groups = "i2c_ao_sda_9";
1293						function = "i2c_ao";
1294					};
1295				};
1296
1297				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1298					mux {
1299						groups = "i2c_ao_sda_11";
1300						function = "i2c_ao";
1301					};
1302				};
1303
1304				remote_input_ao_pins: remote_input_ao {
1305					mux {
1306						groups = "remote_input_ao";
1307						function = "remote_input_ao";
1308					};
1309				};
1310
1311				uart_ao_a_pins: uart_ao_a {
1312					mux {
1313						groups = "uart_ao_tx_a",
1314							 "uart_ao_rx_a";
1315						function = "uart_ao_a";
1316					};
1317				};
1318
1319				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1320					mux {
1321						groups = "uart_ao_cts_a",
1322							 "uart_ao_rts_a";
1323						function = "uart_ao_a";
1324					};
1325				};
1326
1327				uart_ao_b_pins: uart_ao_b {
1328					mux {
1329						groups = "uart_ao_tx_b",
1330							 "uart_ao_rx_b";
1331						function = "uart_ao_b";
1332					};
1333				};
1334
1335				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1336					mux {
1337						groups = "uart_ao_cts_b",
1338							 "uart_ao_rts_b";
1339						function = "uart_ao_b";
1340					};
1341				};
1342			};
1343
1344			sec_AO: ao-secure@140 {
1345				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1346				reg = <0x0 0x140 0x0 0x140>;
1347				amlogic,has-chip-id;
1348			};
1349
1350			pwm_AO_cd: pwm@2000 {
1351				compatible = "amlogic,meson-axg-ao-pwm";
1352				reg = <0x0 0x02000  0x0 0x20>;
1353				#pwm-cells = <3>;
1354				status = "disabled";
1355			};
1356
1357			uart_AO: serial@3000 {
1358				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1359				reg = <0x0 0x3000 0x0 0x18>;
1360				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1361				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1362				clock-names = "xtal", "pclk", "baud";
1363				status = "disabled";
1364			};
1365
1366			uart_AO_B: serial@4000 {
1367				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1368				reg = <0x0 0x4000 0x0 0x18>;
1369				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1370				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1371				clock-names = "xtal", "pclk", "baud";
1372				status = "disabled";
1373			};
1374
1375			i2c_AO: i2c@5000 {
1376				compatible = "amlogic,meson-axg-i2c";
1377				reg = <0x0 0x05000 0x0 0x20>;
1378				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1379				clocks = <&clkc CLKID_AO_I2C>;
1380				#address-cells = <1>;
1381				#size-cells = <0>;
1382				status = "disabled";
1383			};
1384
1385			pwm_AO_ab: pwm@7000 {
1386				compatible = "amlogic,meson-axg-ao-pwm";
1387				reg = <0x0 0x07000 0x0 0x20>;
1388				#pwm-cells = <3>;
1389				status = "disabled";
1390			};
1391
1392			ir: ir@8000 {
1393				compatible = "amlogic,meson-gxbb-ir";
1394				reg = <0x0 0x8000 0x0 0x20>;
1395				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1396				status = "disabled";
1397			};
1398
1399			saradc: adc@9000 {
1400				compatible = "amlogic,meson-axg-saradc",
1401					"amlogic,meson-saradc";
1402				reg = <0x0 0x9000 0x0 0x38>;
1403				#io-channel-cells = <1>;
1404				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1405				clocks = <&xtal>,
1406					 <&clkc_AO CLKID_AO_SAR_ADC>,
1407					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1408					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1409				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1410				status = "disabled";
1411			};
1412		};
1413
1414		gic: interrupt-controller@ffc01000 {
1415			compatible = "arm,gic-400";
1416			reg = <0x0 0xffc01000 0 0x1000>,
1417			      <0x0 0xffc02000 0 0x2000>,
1418			      <0x0 0xffc04000 0 0x2000>,
1419			      <0x0 0xffc06000 0 0x2000>;
1420			interrupt-controller;
1421			interrupts = <GIC_PPI 9
1422				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1423			#interrupt-cells = <3>;
1424			#address-cells = <0>;
1425		};
1426
1427		cbus: bus@ffd00000 {
1428			compatible = "simple-bus";
1429			reg = <0x0 0xffd00000 0x0 0x25000>;
1430			#address-cells = <2>;
1431			#size-cells = <2>;
1432			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1433
1434			reset: reset-controller@1004 {
1435				compatible = "amlogic,meson-axg-reset";
1436				reg = <0x0 0x01004 0x0 0x9c>;
1437				#reset-cells = <1>;
1438			};
1439
1440			gpio_intc: interrupt-controller@f080 {
1441				compatible = "amlogic,meson-gpio-intc";
1442				reg = <0x0 0xf080 0x0 0x10>;
1443				interrupt-controller;
1444				#interrupt-cells = <2>;
1445				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1446				status = "disabled";
1447			};
1448
1449			pwm_ab: pwm@1b000 {
1450				compatible = "amlogic,meson-axg-ee-pwm";
1451				reg = <0x0 0x1b000 0x0 0x20>;
1452				#pwm-cells = <3>;
1453				status = "disabled";
1454			};
1455
1456			pwm_cd: pwm@1a000 {
1457				compatible = "amlogic,meson-axg-ee-pwm";
1458				reg = <0x0 0x1a000 0x0 0x20>;
1459				#pwm-cells = <3>;
1460				status = "disabled";
1461			};
1462
1463			spicc0: spi@13000 {
1464				compatible = "amlogic,meson-axg-spicc";
1465				reg = <0x0 0x13000 0x0 0x3c>;
1466				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1467				clocks = <&clkc CLKID_SPICC0>;
1468				clock-names = "core";
1469				#address-cells = <1>;
1470				#size-cells = <0>;
1471				status = "disabled";
1472			};
1473
1474			spicc1: spi@15000 {
1475				compatible = "amlogic,meson-axg-spicc";
1476				reg = <0x0 0x15000 0x0 0x3c>;
1477				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1478				clocks = <&clkc CLKID_SPICC1>;
1479				clock-names = "core";
1480				#address-cells = <1>;
1481				#size-cells = <0>;
1482				status = "disabled";
1483			};
1484
1485			i2c3: i2c@1c000 {
1486				compatible = "amlogic,meson-axg-i2c";
1487				reg = <0x0 0x1c000 0x0 0x20>;
1488				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1489				clocks = <&clkc CLKID_I2C>;
1490				#address-cells = <1>;
1491				#size-cells = <0>;
1492				status = "disabled";
1493			};
1494
1495			i2c2: i2c@1d000 {
1496				compatible = "amlogic,meson-axg-i2c";
1497				reg = <0x0 0x1d000 0x0 0x20>;
1498				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1499				clocks = <&clkc CLKID_I2C>;
1500				#address-cells = <1>;
1501				#size-cells = <0>;
1502				status = "disabled";
1503			};
1504
1505			i2c1: i2c@1e000 {
1506				compatible = "amlogic,meson-axg-i2c";
1507				reg = <0x0 0x1e000 0x0 0x20>;
1508				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1509				clocks = <&clkc CLKID_I2C>;
1510				#address-cells = <1>;
1511				#size-cells = <0>;
1512				status = "disabled";
1513			};
1514
1515			i2c0: i2c@1f000 {
1516				compatible = "amlogic,meson-axg-i2c";
1517				reg = <0x0 0x1f000 0x0 0x20>;
1518				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1519				clocks = <&clkc CLKID_I2C>;
1520				#address-cells = <1>;
1521				#size-cells = <0>;
1522				status = "disabled";
1523			};
1524
1525			uart_B: serial@23000 {
1526				compatible = "amlogic,meson-gx-uart";
1527				reg = <0x0 0x23000 0x0 0x18>;
1528				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1529				status = "disabled";
1530				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1531				clock-names = "xtal", "pclk", "baud";
1532			};
1533
1534			uart_A: serial@24000 {
1535				compatible = "amlogic,meson-gx-uart";
1536				reg = <0x0 0x24000 0x0 0x18>;
1537				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1538				status = "disabled";
1539				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1540				clock-names = "xtal", "pclk", "baud";
1541			};
1542		};
1543
1544		apb: bus@ffe00000 {
1545			compatible = "simple-bus";
1546			reg = <0x0 0xffe00000 0x0 0x200000>;
1547			#address-cells = <2>;
1548			#size-cells = <2>;
1549			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1550
1551			sd_emmc_b: sd@5000 {
1552				compatible = "amlogic,meson-axg-mmc";
1553				reg = <0x0 0x5000 0x0 0x800>;
1554				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1555				status = "disabled";
1556				clocks = <&clkc CLKID_SD_EMMC_B>,
1557					<&clkc CLKID_SD_EMMC_B_CLK0>,
1558					<&clkc CLKID_FCLK_DIV2>;
1559				clock-names = "core", "clkin0", "clkin1";
1560				resets = <&reset RESET_SD_EMMC_B>;
1561			};
1562
1563			sd_emmc_c: mmc@7000 {
1564				compatible = "amlogic,meson-axg-mmc";
1565				reg = <0x0 0x7000 0x0 0x800>;
1566				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1567				status = "disabled";
1568				clocks = <&clkc CLKID_SD_EMMC_C>,
1569					<&clkc CLKID_SD_EMMC_C_CLK0>,
1570					<&clkc CLKID_FCLK_DIV2>;
1571				clock-names = "core", "clkin0", "clkin1";
1572				resets = <&reset RESET_SD_EMMC_C>;
1573			};
1574		};
1575
1576		sram: sram@fffc0000 {
1577			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1578			reg = <0x0 0xfffc0000 0x0 0x20000>;
1579			#address-cells = <1>;
1580			#size-cells = <1>;
1581			ranges = <0 0x0 0xfffc0000 0x20000>;
1582
1583			cpu_scp_lpri: scp-shmem@13000 {
1584				compatible = "amlogic,meson-axg-scp-shmem";
1585				reg = <0x13000 0x400>;
1586			};
1587
1588			cpu_scp_hpri: scp-shmem@13400 {
1589				compatible = "amlogic,meson-axg-scp-shmem";
1590				reg = <0x13400 0x400>;
1591			};
1592		};
1593	};
1594
1595	timer {
1596		compatible = "arm,armv8-timer";
1597		interrupts = <GIC_PPI 13
1598			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1599			     <GIC_PPI 14
1600			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1601			     <GIC_PPI 11
1602			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1603			     <GIC_PPI 10
1604			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1605	};
1606
1607	xtal: xtal-clk {
1608		compatible = "fixed-clock";
1609		clock-frequency = <24000000>;
1610		clock-output-names = "xtal";
1611		#clock-cells = <0>;
1612	};
1613};
1614