1114abfe1SNeil Armstrong// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 29d59b708SYixun Lan/* 39d59b708SYixun Lan * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 49d59b708SYixun Lan */ 59d59b708SYixun Lan 68c0cf40fSJerome Brunet#include <dt-bindings/clock/axg-aoclkc.h> 78909e722SJerome Brunet#include <dt-bindings/clock/axg-audio-clkc.h> 806b7a631SYixun Lan#include <dt-bindings/clock/axg-clkc.h> 98c0cf40fSJerome Brunet#include <dt-bindings/gpio/gpio.h> 10221cf34bSNan Li#include <dt-bindings/gpio/meson-axg-gpio.h> 118c0cf40fSJerome Brunet#include <dt-bindings/interrupt-controller/irq.h> 128c0cf40fSJerome Brunet#include <dt-bindings/interrupt-controller/arm-gic.h> 13f2b8f6a9SJerome Brunet#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 148c0cf40fSJerome Brunet#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 1578a6dcb5SNeil Armstrong#include <dt-bindings/power/meson-axg-power.h> 169d59b708SYixun Lan 179d59b708SYixun Lan/ { 189d59b708SYixun Lan compatible = "amlogic,meson-axg"; 199d59b708SYixun Lan 209d59b708SYixun Lan interrupt-parent = <&gic>; 219d59b708SYixun Lan #address-cells = <2>; 229d59b708SYixun Lan #size-cells = <2>; 239d59b708SYixun Lan 24fbd5cbc5SJerome Brunet tdmif_a: audio-controller-0 { 258c0cf40fSJerome Brunet compatible = "amlogic,axg-tdm-iface"; 268c0cf40fSJerome Brunet #sound-dai-cells = <0>; 278c0cf40fSJerome Brunet sound-name-prefix = "TDM_A"; 288c0cf40fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 298c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_A_SCLK>, 308c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 318c0cf40fSJerome Brunet clock-names = "mclk", "sclk", "lrclk"; 328c0cf40fSJerome Brunet status = "disabled"; 339d59b708SYixun Lan }; 349d59b708SYixun Lan 35fbd5cbc5SJerome Brunet tdmif_b: audio-controller-1 { 368c0cf40fSJerome Brunet compatible = "amlogic,axg-tdm-iface"; 378c0cf40fSJerome Brunet #sound-dai-cells = <0>; 388c0cf40fSJerome Brunet sound-name-prefix = "TDM_B"; 398c0cf40fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 408c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_B_SCLK>, 418c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 428c0cf40fSJerome Brunet clock-names = "mclk", "sclk", "lrclk"; 438c0cf40fSJerome Brunet status = "disabled"; 449d59b708SYixun Lan }; 458c0cf40fSJerome Brunet 46fbd5cbc5SJerome Brunet tdmif_c: audio-controller-2 { 478c0cf40fSJerome Brunet compatible = "amlogic,axg-tdm-iface"; 488c0cf40fSJerome Brunet #sound-dai-cells = <0>; 498c0cf40fSJerome Brunet sound-name-prefix = "TDM_C"; 508c0cf40fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 518c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_C_SCLK>, 528c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 538c0cf40fSJerome Brunet clock-names = "mclk", "sclk", "lrclk"; 548c0cf40fSJerome Brunet status = "disabled"; 558c0cf40fSJerome Brunet }; 568c0cf40fSJerome Brunet 578c0cf40fSJerome Brunet arm-pmu { 588c0cf40fSJerome Brunet compatible = "arm,cortex-a53-pmu"; 598c0cf40fSJerome Brunet interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 608c0cf40fSJerome Brunet <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 618c0cf40fSJerome Brunet <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 628c0cf40fSJerome Brunet <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 638c0cf40fSJerome Brunet interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 649d59b708SYixun Lan }; 659d59b708SYixun Lan 669d59b708SYixun Lan cpus { 679d59b708SYixun Lan #address-cells = <0x2>; 689d59b708SYixun Lan #size-cells = <0x0>; 699d59b708SYixun Lan 709d59b708SYixun Lan cpu0: cpu@0 { 719d59b708SYixun Lan device_type = "cpu"; 7231af04cdSRob Herring compatible = "arm,cortex-a53"; 739d59b708SYixun Lan reg = <0x0 0x0>; 749d59b708SYixun Lan enable-method = "psci"; 759d59b708SYixun Lan next-level-cache = <&l2>; 762c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 779d59b708SYixun Lan }; 789d59b708SYixun Lan 799d59b708SYixun Lan cpu1: cpu@1 { 809d59b708SYixun Lan device_type = "cpu"; 8131af04cdSRob Herring compatible = "arm,cortex-a53"; 829d59b708SYixun Lan reg = <0x0 0x1>; 839d59b708SYixun Lan enable-method = "psci"; 849d59b708SYixun Lan next-level-cache = <&l2>; 852c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 869d59b708SYixun Lan }; 879d59b708SYixun Lan 889d59b708SYixun Lan cpu2: cpu@2 { 899d59b708SYixun Lan device_type = "cpu"; 9031af04cdSRob Herring compatible = "arm,cortex-a53"; 919d59b708SYixun Lan reg = <0x0 0x2>; 929d59b708SYixun Lan enable-method = "psci"; 939d59b708SYixun Lan next-level-cache = <&l2>; 942c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 959d59b708SYixun Lan }; 969d59b708SYixun Lan 979d59b708SYixun Lan cpu3: cpu@3 { 989d59b708SYixun Lan device_type = "cpu"; 9931af04cdSRob Herring compatible = "arm,cortex-a53"; 1009d59b708SYixun Lan reg = <0x0 0x3>; 1019d59b708SYixun Lan enable-method = "psci"; 1029d59b708SYixun Lan next-level-cache = <&l2>; 1032c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 1049d59b708SYixun Lan }; 1059d59b708SYixun Lan 1069d59b708SYixun Lan l2: l2-cache0 { 1079d59b708SYixun Lan compatible = "cache"; 1089d59b708SYixun Lan }; 1099d59b708SYixun Lan }; 1109d59b708SYixun Lan 11196dc5702SJerome Brunet sm: secure-monitor { 11296dc5702SJerome Brunet compatible = "amlogic,meson-gxbb-sm"; 11396dc5702SJerome Brunet }; 11496dc5702SJerome Brunet 1159ab2d15cSJerome Brunet efuse: efuse { 1169ab2d15cSJerome Brunet compatible = "amlogic,meson-gxbb-efuse"; 1179ab2d15cSJerome Brunet clocks = <&clkc CLKID_EFUSE>; 1189ab2d15cSJerome Brunet #address-cells = <1>; 1199ab2d15cSJerome Brunet #size-cells = <1>; 1209ab2d15cSJerome Brunet read-only; 121de82e74aSCarlo Caione secure-monitor = <&sm>; 1229ab2d15cSJerome Brunet }; 1239ab2d15cSJerome Brunet 1249d59b708SYixun Lan psci { 1259d59b708SYixun Lan compatible = "arm,psci-1.0"; 1269d59b708SYixun Lan method = "smc"; 1279d59b708SYixun Lan }; 1289d59b708SYixun Lan 1298c0cf40fSJerome Brunet reserved-memory { 1308c0cf40fSJerome Brunet #address-cells = <2>; 1318c0cf40fSJerome Brunet #size-cells = <2>; 1328c0cf40fSJerome Brunet ranges; 1338c0cf40fSJerome Brunet 1348c0cf40fSJerome Brunet /* 16 MiB reserved for Hardware ROM Firmware */ 1358c0cf40fSJerome Brunet hwrom_reserved: hwrom@0 { 1368c0cf40fSJerome Brunet reg = <0x0 0x0 0x0 0x1000000>; 1378c0cf40fSJerome Brunet no-map; 13808307aabSJerome Brunet }; 13908307aabSJerome Brunet 1408c0cf40fSJerome Brunet /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 1418c0cf40fSJerome Brunet secmon_reserved: secmon@5000000 { 1428c0cf40fSJerome Brunet reg = <0x0 0x05000000 0x0 0x300000>; 1438c0cf40fSJerome Brunet no-map; 14408307aabSJerome Brunet }; 1455e395e14SYixun Lan }; 1465e395e14SYixun Lan 1472c130695SJerome Brunet scpi { 1482c130695SJerome Brunet compatible = "arm,scpi-pre-1.0"; 1492c130695SJerome Brunet mboxes = <&mailbox 1 &mailbox 2>; 1502c130695SJerome Brunet shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 1512c130695SJerome Brunet 1522c130695SJerome Brunet scpi_clocks: clocks { 1532c130695SJerome Brunet compatible = "arm,scpi-clocks"; 1542c130695SJerome Brunet 1552c130695SJerome Brunet scpi_dvfs: clock-controller { 1562c130695SJerome Brunet compatible = "arm,scpi-dvfs-clocks"; 1572c130695SJerome Brunet #clock-cells = <1>; 1582c130695SJerome Brunet clock-indices = <0>; 1592c130695SJerome Brunet clock-output-names = "vcpu"; 1602c130695SJerome Brunet }; 1612c130695SJerome Brunet }; 1622c130695SJerome Brunet 1632c130695SJerome Brunet scpi_sensors: sensors { 1642c130695SJerome Brunet compatible = "amlogic,meson-gxbb-scpi-sensors"; 1652c130695SJerome Brunet #thermal-sensor-cells = <1>; 1662c130695SJerome Brunet }; 1672c130695SJerome Brunet }; 1682c130695SJerome Brunet 1699d59b708SYixun Lan soc { 1709d59b708SYixun Lan compatible = "simple-bus"; 1719d59b708SYixun Lan #address-cells = <2>; 1729d59b708SYixun Lan #size-cells = <2>; 1739d59b708SYixun Lan ranges; 1749d59b708SYixun Lan 1755b3a9c20SNeil Armstrong pcieA: pcie@f9800000 { 1765b3a9c20SNeil Armstrong compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 1775b3a9c20SNeil Armstrong reg = <0x0 0xf9800000 0x0 0x400000>, 1785b3a9c20SNeil Armstrong <0x0 0xff646000 0x0 0x2000>, 1795b3a9c20SNeil Armstrong <0x0 0xf9f00000 0x0 0x100000>; 1805b3a9c20SNeil Armstrong reg-names = "elbi", "cfg", "config"; 1815b3a9c20SNeil Armstrong interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 1825b3a9c20SNeil Armstrong #interrupt-cells = <1>; 1835b3a9c20SNeil Armstrong interrupt-map-mask = <0 0 0 0>; 1845b3a9c20SNeil Armstrong interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1855b3a9c20SNeil Armstrong bus-range = <0x0 0xff>; 1865b3a9c20SNeil Armstrong #address-cells = <3>; 1875b3a9c20SNeil Armstrong #size-cells = <2>; 1885b3a9c20SNeil Armstrong device_type = "pci"; 1895b3a9c20SNeil Armstrong ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; 1905b3a9c20SNeil Armstrong 1915b3a9c20SNeil Armstrong clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; 1925b3a9c20SNeil Armstrong clock-names = "general", "pclk", "port"; 1935b3a9c20SNeil Armstrong resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; 1945b3a9c20SNeil Armstrong reset-names = "port", "apb"; 1955b3a9c20SNeil Armstrong num-lanes = <1>; 1965b3a9c20SNeil Armstrong phys = <&pcie_phy>; 1975b3a9c20SNeil Armstrong phy-names = "pcie"; 1985b3a9c20SNeil Armstrong status = "disabled"; 1995b3a9c20SNeil Armstrong }; 2005b3a9c20SNeil Armstrong 2015b3a9c20SNeil Armstrong pcieB: pcie@fa000000 { 2025b3a9c20SNeil Armstrong compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 2035b3a9c20SNeil Armstrong reg = <0x0 0xfa000000 0x0 0x400000>, 2045b3a9c20SNeil Armstrong <0x0 0xff648000 0x0 0x2000>, 2055b3a9c20SNeil Armstrong <0x0 0xfa400000 0x0 0x100000>; 2065b3a9c20SNeil Armstrong reg-names = "elbi", "cfg", "config"; 2075b3a9c20SNeil Armstrong interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; 2085b3a9c20SNeil Armstrong #interrupt-cells = <1>; 2095b3a9c20SNeil Armstrong interrupt-map-mask = <0 0 0 0>; 2105b3a9c20SNeil Armstrong interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 2115b3a9c20SNeil Armstrong bus-range = <0x0 0xff>; 2125b3a9c20SNeil Armstrong #address-cells = <3>; 2135b3a9c20SNeil Armstrong #size-cells = <2>; 2145b3a9c20SNeil Armstrong device_type = "pci"; 2155b3a9c20SNeil Armstrong ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; 2165b3a9c20SNeil Armstrong 2175b3a9c20SNeil Armstrong clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; 2185b3a9c20SNeil Armstrong clock-names = "general", "pclk", "port"; 2195b3a9c20SNeil Armstrong resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; 2205b3a9c20SNeil Armstrong reset-names = "port", "apb"; 2215b3a9c20SNeil Armstrong num-lanes = <1>; 2225b3a9c20SNeil Armstrong phys = <&pcie_phy>; 2235b3a9c20SNeil Armstrong phy-names = "pcie"; 2245b3a9c20SNeil Armstrong status = "disabled"; 2255b3a9c20SNeil Armstrong }; 2265b3a9c20SNeil Armstrong 2271b208babSNeil Armstrong usb: usb@ffe09080 { 2281b208babSNeil Armstrong compatible = "amlogic,meson-axg-usb-ctrl"; 2291b208babSNeil Armstrong reg = <0x0 0xffe09080 0x0 0x20>; 2301b208babSNeil Armstrong interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2311b208babSNeil Armstrong #address-cells = <2>; 2321b208babSNeil Armstrong #size-cells = <2>; 2331b208babSNeil Armstrong ranges; 2341b208babSNeil Armstrong 2351b208babSNeil Armstrong clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; 2361b208babSNeil Armstrong clock-names = "usb_ctrl", "ddr"; 2371b208babSNeil Armstrong resets = <&reset RESET_USB_OTG>; 2381b208babSNeil Armstrong 2391b208babSNeil Armstrong dr_mode = "otg"; 2401b208babSNeil Armstrong 2411b208babSNeil Armstrong phys = <&usb2_phy1>; 2421b208babSNeil Armstrong phy-names = "usb2-phy1"; 2431b208babSNeil Armstrong 2441b208babSNeil Armstrong dwc2: usb@ff400000 { 2451b208babSNeil Armstrong compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2461b208babSNeil Armstrong reg = <0x0 0xff400000 0x0 0x40000>; 2471b208babSNeil Armstrong interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2481b208babSNeil Armstrong clocks = <&clkc CLKID_USB1>; 2491b208babSNeil Armstrong clock-names = "otg"; 2501b208babSNeil Armstrong phys = <&usb2_phy1>; 2511b208babSNeil Armstrong dr_mode = "peripheral"; 2521b208babSNeil Armstrong g-rx-fifo-size = <192>; 2531b208babSNeil Armstrong g-np-tx-fifo-size = <128>; 2541b208babSNeil Armstrong g-tx-fifo-size = <128 128 16 16 16>; 2551b208babSNeil Armstrong }; 2561b208babSNeil Armstrong 2571b208babSNeil Armstrong dwc3: usb@ff500000 { 2581b208babSNeil Armstrong compatible = "snps,dwc3"; 2591b208babSNeil Armstrong reg = <0x0 0xff500000 0x0 0x100000>; 2601b208babSNeil Armstrong interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2611b208babSNeil Armstrong dr_mode = "host"; 2621b208babSNeil Armstrong maximum-speed = "high-speed"; 2631b208babSNeil Armstrong snps,dis_u2_susphy_quirk; 2641b208babSNeil Armstrong }; 2651b208babSNeil Armstrong }; 2661b208babSNeil Armstrong 2678c0cf40fSJerome Brunet ethmac: ethernet@ff3f0000 { 2689d63f5d1SJerome Brunet compatible = "amlogic,meson-axg-dwmac", 2699d63f5d1SJerome Brunet "snps,dwmac-3.70a", 2709d63f5d1SJerome Brunet "snps,dwmac"; 2713ad6c9e3SNeil Armstrong reg = <0x0 0xff3f0000 0x0 0x10000>, 2723ad6c9e3SNeil Armstrong <0x0 0xff634540 0x0 0x8>; 2738b3e6f89SCarlo Caione interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2748c0cf40fSJerome Brunet interrupt-names = "macirq"; 2758c0cf40fSJerome Brunet clocks = <&clkc CLKID_ETH>, 2768c0cf40fSJerome Brunet <&clkc CLKID_FCLK_DIV2>, 27732b5f4b6SMartin Blumenstingl <&clkc CLKID_MPLL2>, 27832b5f4b6SMartin Blumenstingl <&clkc CLKID_FCLK_DIV2>; 27932b5f4b6SMartin Blumenstingl clock-names = "stmmaceth", "clkin0", "clkin1", 28032b5f4b6SMartin Blumenstingl "timing-adjustment"; 281ef68984eSJerome Brunet rx-fifo-depth = <4096>; 282ef68984eSJerome Brunet tx-fifo-depth = <2048>; 28378a6dcb5SNeil Armstrong power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; 2848c0cf40fSJerome Brunet status = "disabled"; 2858c0cf40fSJerome Brunet }; 2868c0cf40fSJerome Brunet 2875b3a9c20SNeil Armstrong pcie_phy: phy@ff644000 { 2885b3a9c20SNeil Armstrong compatible = "amlogic,axg-pcie-phy"; 2895b3a9c20SNeil Armstrong reg = <0x0 0xff644000 0x0 0x1c>; 2905b3a9c20SNeil Armstrong resets = <&reset RESET_PCIE_PHY>; 2915b3a9c20SNeil Armstrong phys = <&mipi_pcie_analog_dphy>; 2925b3a9c20SNeil Armstrong phy-names = "analog"; 2935b3a9c20SNeil Armstrong #phy-cells = <0>; 2945b3a9c20SNeil Armstrong }; 2955b3a9c20SNeil Armstrong 296c362e4e0SJerome Brunet pdm: audio-controller@ff632000 { 297c362e4e0SJerome Brunet compatible = "amlogic,axg-pdm"; 298c362e4e0SJerome Brunet reg = <0x0 0xff632000 0x0 0x34>; 299c362e4e0SJerome Brunet #sound-dai-cells = <0>; 300c362e4e0SJerome Brunet sound-name-prefix = "PDM"; 301c362e4e0SJerome Brunet clocks = <&clkc_audio AUD_CLKID_PDM>, 302c362e4e0SJerome Brunet <&clkc_audio AUD_CLKID_PDM_DCLK>, 303c362e4e0SJerome Brunet <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 304c362e4e0SJerome Brunet clock-names = "pclk", "dclk", "sysclk"; 305c362e4e0SJerome Brunet status = "disabled"; 306c362e4e0SJerome Brunet }; 307c362e4e0SJerome Brunet 3088c0cf40fSJerome Brunet periphs: bus@ff634000 { 309221cf34bSNan Li compatible = "simple-bus"; 3108c0cf40fSJerome Brunet reg = <0x0 0xff634000 0x0 0x2000>; 311221cf34bSNan Li #address-cells = <2>; 312221cf34bSNan Li #size-cells = <2>; 3138c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 314221cf34bSNan Li 3158c0cf40fSJerome Brunet hwrng: rng@18 { 3168c0cf40fSJerome Brunet compatible = "amlogic,meson-rng"; 3178c0cf40fSJerome Brunet reg = <0x0 0x18 0x0 0x4>; 3188c0cf40fSJerome Brunet clocks = <&clkc CLKID_RNG0>; 3198c0cf40fSJerome Brunet clock-names = "core"; 320221cf34bSNan Li }; 321221cf34bSNan Li 3228c0cf40fSJerome Brunet pinctrl_periphs: pinctrl@480 { 3238c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-periphs-pinctrl"; 3248c0cf40fSJerome Brunet #address-cells = <2>; 3258c0cf40fSJerome Brunet #size-cells = <2>; 3268c0cf40fSJerome Brunet ranges; 3278c0cf40fSJerome Brunet 3288c0cf40fSJerome Brunet gpio: bank@480 { 3298c0cf40fSJerome Brunet reg = <0x0 0x00480 0x0 0x40>, 3308c0cf40fSJerome Brunet <0x0 0x004e8 0x0 0x14>, 3318c0cf40fSJerome Brunet <0x0 0x00520 0x0 0x14>, 3328c0cf40fSJerome Brunet <0x0 0x00430 0x0 0x3c>; 3338c0cf40fSJerome Brunet reg-names = "mux", "pull", "pull-enable", "gpio"; 3348c0cf40fSJerome Brunet gpio-controller; 3358c0cf40fSJerome Brunet #gpio-cells = <2>; 3368c0cf40fSJerome Brunet gpio-ranges = <&pinctrl_periphs 0 0 86>; 337221cf34bSNan Li }; 3388c0cf40fSJerome Brunet 3398c0cf40fSJerome Brunet i2c0_pins: i2c0 { 3408c0cf40fSJerome Brunet mux { 3418c0cf40fSJerome Brunet groups = "i2c0_sck", 3428c0cf40fSJerome Brunet "i2c0_sda"; 3438c0cf40fSJerome Brunet function = "i2c0"; 3441c5cc1c8SJerome Brunet bias-disable; 3458c0cf40fSJerome Brunet }; 3468c0cf40fSJerome Brunet }; 3478c0cf40fSJerome Brunet 3488c0cf40fSJerome Brunet i2c1_x_pins: i2c1_x { 3498c0cf40fSJerome Brunet mux { 3508c0cf40fSJerome Brunet groups = "i2c1_sck_x", 3518c0cf40fSJerome Brunet "i2c1_sda_x"; 3528c0cf40fSJerome Brunet function = "i2c1"; 3531c5cc1c8SJerome Brunet bias-disable; 3548c0cf40fSJerome Brunet }; 3558c0cf40fSJerome Brunet }; 3568c0cf40fSJerome Brunet 3578c0cf40fSJerome Brunet i2c1_z_pins: i2c1_z { 3588c0cf40fSJerome Brunet mux { 3598c0cf40fSJerome Brunet groups = "i2c1_sck_z", 3608c0cf40fSJerome Brunet "i2c1_sda_z"; 3618c0cf40fSJerome Brunet function = "i2c1"; 3621c5cc1c8SJerome Brunet bias-disable; 3638c0cf40fSJerome Brunet }; 3648c0cf40fSJerome Brunet }; 3658c0cf40fSJerome Brunet 3668c0cf40fSJerome Brunet i2c2_a_pins: i2c2_a { 3678c0cf40fSJerome Brunet mux { 3688c0cf40fSJerome Brunet groups = "i2c2_sck_a", 3698c0cf40fSJerome Brunet "i2c2_sda_a"; 3708c0cf40fSJerome Brunet function = "i2c2"; 3711c5cc1c8SJerome Brunet bias-disable; 3728c0cf40fSJerome Brunet }; 3738c0cf40fSJerome Brunet }; 3748c0cf40fSJerome Brunet 3758c0cf40fSJerome Brunet i2c2_x_pins: i2c2_x { 3768c0cf40fSJerome Brunet mux { 3778c0cf40fSJerome Brunet groups = "i2c2_sck_x", 3788c0cf40fSJerome Brunet "i2c2_sda_x"; 3798c0cf40fSJerome Brunet function = "i2c2"; 3801c5cc1c8SJerome Brunet bias-disable; 3818c0cf40fSJerome Brunet }; 3828c0cf40fSJerome Brunet }; 3838c0cf40fSJerome Brunet 3848c0cf40fSJerome Brunet i2c3_a6_pins: i2c3_a6 { 3858c0cf40fSJerome Brunet mux { 3868c0cf40fSJerome Brunet groups = "i2c3_sda_a6", 3878c0cf40fSJerome Brunet "i2c3_sck_a7"; 3888c0cf40fSJerome Brunet function = "i2c3"; 3891c5cc1c8SJerome Brunet bias-disable; 3908c0cf40fSJerome Brunet }; 3918c0cf40fSJerome Brunet }; 3928c0cf40fSJerome Brunet 3938c0cf40fSJerome Brunet i2c3_a12_pins: i2c3_a12 { 3948c0cf40fSJerome Brunet mux { 3958c0cf40fSJerome Brunet groups = "i2c3_sda_a12", 3968c0cf40fSJerome Brunet "i2c3_sck_a13"; 3978c0cf40fSJerome Brunet function = "i2c3"; 3981c5cc1c8SJerome Brunet bias-disable; 3998c0cf40fSJerome Brunet }; 4008c0cf40fSJerome Brunet }; 4018c0cf40fSJerome Brunet 4028c0cf40fSJerome Brunet i2c3_a19_pins: i2c3_a19 { 4038c0cf40fSJerome Brunet mux { 4048c0cf40fSJerome Brunet groups = "i2c3_sda_a19", 4058c0cf40fSJerome Brunet "i2c3_sck_a20"; 4068c0cf40fSJerome Brunet function = "i2c3"; 4071c5cc1c8SJerome Brunet bias-disable; 4088c0cf40fSJerome Brunet }; 4098c0cf40fSJerome Brunet }; 4108c0cf40fSJerome Brunet 4118c0cf40fSJerome Brunet emmc_pins: emmc { 412b43033b1SJerome Brunet mux-0 { 4138c0cf40fSJerome Brunet groups = "emmc_nand_d0", 4148c0cf40fSJerome Brunet "emmc_nand_d1", 4158c0cf40fSJerome Brunet "emmc_nand_d2", 4168c0cf40fSJerome Brunet "emmc_nand_d3", 4178c0cf40fSJerome Brunet "emmc_nand_d4", 4188c0cf40fSJerome Brunet "emmc_nand_d5", 4198c0cf40fSJerome Brunet "emmc_nand_d6", 4208c0cf40fSJerome Brunet "emmc_nand_d7", 421b43033b1SJerome Brunet "emmc_cmd"; 422b43033b1SJerome Brunet function = "emmc"; 423b43033b1SJerome Brunet bias-pull-up; 424b43033b1SJerome Brunet }; 425b43033b1SJerome Brunet 426b43033b1SJerome Brunet mux-1 { 427b43033b1SJerome Brunet groups = "emmc_clk"; 4288c0cf40fSJerome Brunet function = "emmc"; 42996a13691SJerome Brunet bias-disable; 4308c0cf40fSJerome Brunet }; 4318c0cf40fSJerome Brunet }; 4328c0cf40fSJerome Brunet 433b43033b1SJerome Brunet emmc_ds_pins: emmc_ds { 434b43033b1SJerome Brunet mux { 435b43033b1SJerome Brunet groups = "emmc_ds"; 436b43033b1SJerome Brunet function = "emmc"; 437b43033b1SJerome Brunet bias-pull-down; 438b43033b1SJerome Brunet }; 439b43033b1SJerome Brunet }; 440b43033b1SJerome Brunet 4418c0cf40fSJerome Brunet emmc_clk_gate_pins: emmc_clk_gate { 4428c0cf40fSJerome Brunet mux { 4438c0cf40fSJerome Brunet groups = "BOOT_8"; 4448c0cf40fSJerome Brunet function = "gpio_periphs"; 4458c0cf40fSJerome Brunet bias-pull-down; 4468c0cf40fSJerome Brunet }; 4478c0cf40fSJerome Brunet }; 4488c0cf40fSJerome Brunet 4498c0cf40fSJerome Brunet eth_rgmii_x_pins: eth-x-rgmii { 4508c0cf40fSJerome Brunet mux { 4518c0cf40fSJerome Brunet groups = "eth_mdio_x", 4528c0cf40fSJerome Brunet "eth_mdc_x", 4538c0cf40fSJerome Brunet "eth_rgmii_rx_clk_x", 4548c0cf40fSJerome Brunet "eth_rx_dv_x", 4558c0cf40fSJerome Brunet "eth_rxd0_x", 4568c0cf40fSJerome Brunet "eth_rxd1_x", 4578c0cf40fSJerome Brunet "eth_rxd2_rgmii", 4588c0cf40fSJerome Brunet "eth_rxd3_rgmii", 4598c0cf40fSJerome Brunet "eth_rgmii_tx_clk", 4608c0cf40fSJerome Brunet "eth_txen_x", 4618c0cf40fSJerome Brunet "eth_txd0_x", 4628c0cf40fSJerome Brunet "eth_txd1_x", 4638c0cf40fSJerome Brunet "eth_txd2_rgmii", 4648c0cf40fSJerome Brunet "eth_txd3_rgmii"; 4658c0cf40fSJerome Brunet function = "eth"; 4661c5cc1c8SJerome Brunet bias-disable; 4678c0cf40fSJerome Brunet }; 4688c0cf40fSJerome Brunet }; 4698c0cf40fSJerome Brunet 4708c0cf40fSJerome Brunet eth_rgmii_y_pins: eth-y-rgmii { 4718c0cf40fSJerome Brunet mux { 4728c0cf40fSJerome Brunet groups = "eth_mdio_y", 4738c0cf40fSJerome Brunet "eth_mdc_y", 4748c0cf40fSJerome Brunet "eth_rgmii_rx_clk_y", 4758c0cf40fSJerome Brunet "eth_rx_dv_y", 4768c0cf40fSJerome Brunet "eth_rxd0_y", 4778c0cf40fSJerome Brunet "eth_rxd1_y", 4788c0cf40fSJerome Brunet "eth_rxd2_rgmii", 4798c0cf40fSJerome Brunet "eth_rxd3_rgmii", 4808c0cf40fSJerome Brunet "eth_rgmii_tx_clk", 4818c0cf40fSJerome Brunet "eth_txen_y", 4828c0cf40fSJerome Brunet "eth_txd0_y", 4838c0cf40fSJerome Brunet "eth_txd1_y", 4848c0cf40fSJerome Brunet "eth_txd2_rgmii", 4858c0cf40fSJerome Brunet "eth_txd3_rgmii"; 4868c0cf40fSJerome Brunet function = "eth"; 4871c5cc1c8SJerome Brunet bias-disable; 4888c0cf40fSJerome Brunet }; 4898c0cf40fSJerome Brunet }; 4908c0cf40fSJerome Brunet 4918c0cf40fSJerome Brunet eth_rmii_x_pins: eth-x-rmii { 4928c0cf40fSJerome Brunet mux { 4938c0cf40fSJerome Brunet groups = "eth_mdio_x", 4948c0cf40fSJerome Brunet "eth_mdc_x", 4958c0cf40fSJerome Brunet "eth_rgmii_rx_clk_x", 4968c0cf40fSJerome Brunet "eth_rx_dv_x", 4978c0cf40fSJerome Brunet "eth_rxd0_x", 4988c0cf40fSJerome Brunet "eth_rxd1_x", 4998c0cf40fSJerome Brunet "eth_txen_x", 5008c0cf40fSJerome Brunet "eth_txd0_x", 5018c0cf40fSJerome Brunet "eth_txd1_x"; 5028c0cf40fSJerome Brunet function = "eth"; 5031c5cc1c8SJerome Brunet bias-disable; 5048c0cf40fSJerome Brunet }; 5058c0cf40fSJerome Brunet }; 5068c0cf40fSJerome Brunet 5078c0cf40fSJerome Brunet eth_rmii_y_pins: eth-y-rmii { 5088c0cf40fSJerome Brunet mux { 5098c0cf40fSJerome Brunet groups = "eth_mdio_y", 5108c0cf40fSJerome Brunet "eth_mdc_y", 5118c0cf40fSJerome Brunet "eth_rgmii_rx_clk_y", 5128c0cf40fSJerome Brunet "eth_rx_dv_y", 5138c0cf40fSJerome Brunet "eth_rxd0_y", 5148c0cf40fSJerome Brunet "eth_rxd1_y", 5158c0cf40fSJerome Brunet "eth_txen_y", 5168c0cf40fSJerome Brunet "eth_txd0_y", 5178c0cf40fSJerome Brunet "eth_txd1_y"; 5188c0cf40fSJerome Brunet function = "eth"; 5191c5cc1c8SJerome Brunet bias-disable; 5208c0cf40fSJerome Brunet }; 5218c0cf40fSJerome Brunet }; 5228c0cf40fSJerome Brunet 5238c0cf40fSJerome Brunet mclk_b_pins: mclk_b { 5248c0cf40fSJerome Brunet mux { 5258c0cf40fSJerome Brunet groups = "mclk_b"; 5268c0cf40fSJerome Brunet function = "mclk_b"; 5271c5cc1c8SJerome Brunet bias-disable; 5288c0cf40fSJerome Brunet }; 5298c0cf40fSJerome Brunet }; 5308c0cf40fSJerome Brunet 5318c0cf40fSJerome Brunet mclk_c_pins: mclk_c { 5328c0cf40fSJerome Brunet mux { 5338c0cf40fSJerome Brunet groups = "mclk_c"; 5348c0cf40fSJerome Brunet function = "mclk_c"; 5351c5cc1c8SJerome Brunet bias-disable; 5368c0cf40fSJerome Brunet }; 5378c0cf40fSJerome Brunet }; 5388c0cf40fSJerome Brunet 5398c0cf40fSJerome Brunet pdm_dclk_a14_pins: pdm_dclk_a14 { 5408c0cf40fSJerome Brunet mux { 5418c0cf40fSJerome Brunet groups = "pdm_dclk_a14"; 5428c0cf40fSJerome Brunet function = "pdm"; 5431c5cc1c8SJerome Brunet bias-disable; 5448c0cf40fSJerome Brunet }; 5458c0cf40fSJerome Brunet }; 5468c0cf40fSJerome Brunet 5478c0cf40fSJerome Brunet pdm_dclk_a19_pins: pdm_dclk_a19 { 5488c0cf40fSJerome Brunet mux { 5498c0cf40fSJerome Brunet groups = "pdm_dclk_a19"; 5508c0cf40fSJerome Brunet function = "pdm"; 5511c5cc1c8SJerome Brunet bias-disable; 5528c0cf40fSJerome Brunet }; 5538c0cf40fSJerome Brunet }; 5548c0cf40fSJerome Brunet 5558c0cf40fSJerome Brunet pdm_din0_pins: pdm_din0 { 5568c0cf40fSJerome Brunet mux { 5578c0cf40fSJerome Brunet groups = "pdm_din0"; 5588c0cf40fSJerome Brunet function = "pdm"; 5591c5cc1c8SJerome Brunet bias-disable; 5608c0cf40fSJerome Brunet }; 5618c0cf40fSJerome Brunet }; 5628c0cf40fSJerome Brunet 5638c0cf40fSJerome Brunet pdm_din1_pins: pdm_din1 { 5648c0cf40fSJerome Brunet mux { 5658c0cf40fSJerome Brunet groups = "pdm_din1"; 5668c0cf40fSJerome Brunet function = "pdm"; 5671c5cc1c8SJerome Brunet bias-disable; 5688c0cf40fSJerome Brunet }; 5698c0cf40fSJerome Brunet }; 5708c0cf40fSJerome Brunet 5718c0cf40fSJerome Brunet pdm_din2_pins: pdm_din2 { 5728c0cf40fSJerome Brunet mux { 5738c0cf40fSJerome Brunet groups = "pdm_din2"; 5748c0cf40fSJerome Brunet function = "pdm"; 5751c5cc1c8SJerome Brunet bias-disable; 5768c0cf40fSJerome Brunet }; 5778c0cf40fSJerome Brunet }; 5788c0cf40fSJerome Brunet 5798c0cf40fSJerome Brunet pdm_din3_pins: pdm_din3 { 5808c0cf40fSJerome Brunet mux { 5818c0cf40fSJerome Brunet groups = "pdm_din3"; 5828c0cf40fSJerome Brunet function = "pdm"; 5831c5cc1c8SJerome Brunet bias-disable; 5848c0cf40fSJerome Brunet }; 5858c0cf40fSJerome Brunet }; 5868c0cf40fSJerome Brunet 5878c0cf40fSJerome Brunet pwm_a_a_pins: pwm_a_a { 5888c0cf40fSJerome Brunet mux { 5898c0cf40fSJerome Brunet groups = "pwm_a_a"; 5908c0cf40fSJerome Brunet function = "pwm_a"; 5911c5cc1c8SJerome Brunet bias-disable; 5928c0cf40fSJerome Brunet }; 5938c0cf40fSJerome Brunet }; 5948c0cf40fSJerome Brunet 5958c0cf40fSJerome Brunet pwm_a_x18_pins: pwm_a_x18 { 5968c0cf40fSJerome Brunet mux { 5978c0cf40fSJerome Brunet groups = "pwm_a_x18"; 5988c0cf40fSJerome Brunet function = "pwm_a"; 5991c5cc1c8SJerome Brunet bias-disable; 6008c0cf40fSJerome Brunet }; 6018c0cf40fSJerome Brunet }; 6028c0cf40fSJerome Brunet 6038c0cf40fSJerome Brunet pwm_a_x20_pins: pwm_a_x20 { 6048c0cf40fSJerome Brunet mux { 6058c0cf40fSJerome Brunet groups = "pwm_a_x20"; 6068c0cf40fSJerome Brunet function = "pwm_a"; 6071c5cc1c8SJerome Brunet bias-disable; 6088c0cf40fSJerome Brunet }; 6098c0cf40fSJerome Brunet }; 6108c0cf40fSJerome Brunet 6118c0cf40fSJerome Brunet pwm_a_z_pins: pwm_a_z { 6128c0cf40fSJerome Brunet mux { 6138c0cf40fSJerome Brunet groups = "pwm_a_z"; 6148c0cf40fSJerome Brunet function = "pwm_a"; 6151c5cc1c8SJerome Brunet bias-disable; 6168c0cf40fSJerome Brunet }; 6178c0cf40fSJerome Brunet }; 6188c0cf40fSJerome Brunet 6198c0cf40fSJerome Brunet pwm_b_a_pins: pwm_b_a { 6208c0cf40fSJerome Brunet mux { 6218c0cf40fSJerome Brunet groups = "pwm_b_a"; 6228c0cf40fSJerome Brunet function = "pwm_b"; 6231c5cc1c8SJerome Brunet bias-disable; 6248c0cf40fSJerome Brunet }; 6258c0cf40fSJerome Brunet }; 6268c0cf40fSJerome Brunet 6278c0cf40fSJerome Brunet pwm_b_x_pins: pwm_b_x { 6288c0cf40fSJerome Brunet mux { 6298c0cf40fSJerome Brunet groups = "pwm_b_x"; 6308c0cf40fSJerome Brunet function = "pwm_b"; 6311c5cc1c8SJerome Brunet bias-disable; 6328c0cf40fSJerome Brunet }; 6338c0cf40fSJerome Brunet }; 6348c0cf40fSJerome Brunet 6358c0cf40fSJerome Brunet pwm_b_z_pins: pwm_b_z { 6368c0cf40fSJerome Brunet mux { 6378c0cf40fSJerome Brunet groups = "pwm_b_z"; 6388c0cf40fSJerome Brunet function = "pwm_b"; 6391c5cc1c8SJerome Brunet bias-disable; 6408c0cf40fSJerome Brunet }; 6418c0cf40fSJerome Brunet }; 6428c0cf40fSJerome Brunet 6438c0cf40fSJerome Brunet pwm_c_a_pins: pwm_c_a { 6448c0cf40fSJerome Brunet mux { 6458c0cf40fSJerome Brunet groups = "pwm_c_a"; 6468c0cf40fSJerome Brunet function = "pwm_c"; 6471c5cc1c8SJerome Brunet bias-disable; 6488c0cf40fSJerome Brunet }; 6498c0cf40fSJerome Brunet }; 6508c0cf40fSJerome Brunet 6518c0cf40fSJerome Brunet pwm_c_x10_pins: pwm_c_x10 { 6528c0cf40fSJerome Brunet mux { 6538c0cf40fSJerome Brunet groups = "pwm_c_x10"; 6548c0cf40fSJerome Brunet function = "pwm_c"; 6551c5cc1c8SJerome Brunet bias-disable; 6568c0cf40fSJerome Brunet }; 6578c0cf40fSJerome Brunet }; 6588c0cf40fSJerome Brunet 6598c0cf40fSJerome Brunet pwm_c_x17_pins: pwm_c_x17 { 6608c0cf40fSJerome Brunet mux { 6618c0cf40fSJerome Brunet groups = "pwm_c_x17"; 6628c0cf40fSJerome Brunet function = "pwm_c"; 6631c5cc1c8SJerome Brunet bias-disable; 6648c0cf40fSJerome Brunet }; 6658c0cf40fSJerome Brunet }; 6668c0cf40fSJerome Brunet 6678c0cf40fSJerome Brunet pwm_d_x11_pins: pwm_d_x11 { 6688c0cf40fSJerome Brunet mux { 6698c0cf40fSJerome Brunet groups = "pwm_d_x11"; 6708c0cf40fSJerome Brunet function = "pwm_d"; 6711c5cc1c8SJerome Brunet bias-disable; 6728c0cf40fSJerome Brunet }; 6738c0cf40fSJerome Brunet }; 6748c0cf40fSJerome Brunet 6758c0cf40fSJerome Brunet pwm_d_x16_pins: pwm_d_x16 { 6768c0cf40fSJerome Brunet mux { 6778c0cf40fSJerome Brunet groups = "pwm_d_x16"; 6788c0cf40fSJerome Brunet function = "pwm_d"; 6791c5cc1c8SJerome Brunet bias-disable; 6808c0cf40fSJerome Brunet }; 6818c0cf40fSJerome Brunet }; 6828c0cf40fSJerome Brunet 6838c0cf40fSJerome Brunet sdio_pins: sdio { 684b43033b1SJerome Brunet mux-0 { 6858c0cf40fSJerome Brunet groups = "sdio_d0", 6868c0cf40fSJerome Brunet "sdio_d1", 6878c0cf40fSJerome Brunet "sdio_d2", 6888c0cf40fSJerome Brunet "sdio_d3", 689b43033b1SJerome Brunet "sdio_cmd"; 690b43033b1SJerome Brunet function = "sdio"; 691b43033b1SJerome Brunet bias-pull-up; 692b43033b1SJerome Brunet }; 693b43033b1SJerome Brunet 694b43033b1SJerome Brunet mux-1 { 695b43033b1SJerome Brunet groups = "sdio_clk"; 6968c0cf40fSJerome Brunet function = "sdio"; 69796a13691SJerome Brunet bias-disable; 6988c0cf40fSJerome Brunet }; 6998c0cf40fSJerome Brunet }; 7008c0cf40fSJerome Brunet 7018c0cf40fSJerome Brunet sdio_clk_gate_pins: sdio_clk_gate { 7028c0cf40fSJerome Brunet mux { 7038c0cf40fSJerome Brunet groups = "GPIOX_4"; 7048c0cf40fSJerome Brunet function = "gpio_periphs"; 7058c0cf40fSJerome Brunet bias-pull-down; 7068c0cf40fSJerome Brunet }; 7078c0cf40fSJerome Brunet }; 7088c0cf40fSJerome Brunet 7098c0cf40fSJerome Brunet spdif_in_z_pins: spdif_in_z { 7108c0cf40fSJerome Brunet mux { 7118c0cf40fSJerome Brunet groups = "spdif_in_z"; 7128c0cf40fSJerome Brunet function = "spdif_in"; 7131c5cc1c8SJerome Brunet bias-disable; 7148c0cf40fSJerome Brunet }; 7158c0cf40fSJerome Brunet }; 7168c0cf40fSJerome Brunet 7178c0cf40fSJerome Brunet spdif_in_a1_pins: spdif_in_a1 { 7188c0cf40fSJerome Brunet mux { 7198c0cf40fSJerome Brunet groups = "spdif_in_a1"; 7208c0cf40fSJerome Brunet function = "spdif_in"; 7211c5cc1c8SJerome Brunet bias-disable; 7228c0cf40fSJerome Brunet }; 7238c0cf40fSJerome Brunet }; 7248c0cf40fSJerome Brunet 7258c0cf40fSJerome Brunet spdif_in_a7_pins: spdif_in_a7 { 7268c0cf40fSJerome Brunet mux { 7278c0cf40fSJerome Brunet groups = "spdif_in_a7"; 7288c0cf40fSJerome Brunet function = "spdif_in"; 7291c5cc1c8SJerome Brunet bias-disable; 7308c0cf40fSJerome Brunet }; 7318c0cf40fSJerome Brunet }; 7328c0cf40fSJerome Brunet 7338c0cf40fSJerome Brunet spdif_in_a19_pins: spdif_in_a19 { 7348c0cf40fSJerome Brunet mux { 7358c0cf40fSJerome Brunet groups = "spdif_in_a19"; 7368c0cf40fSJerome Brunet function = "spdif_in"; 7371c5cc1c8SJerome Brunet bias-disable; 7388c0cf40fSJerome Brunet }; 7398c0cf40fSJerome Brunet }; 7408c0cf40fSJerome Brunet 7418c0cf40fSJerome Brunet spdif_in_a20_pins: spdif_in_a20 { 7428c0cf40fSJerome Brunet mux { 7438c0cf40fSJerome Brunet groups = "spdif_in_a20"; 7448c0cf40fSJerome Brunet function = "spdif_in"; 7451c5cc1c8SJerome Brunet bias-disable; 7468c0cf40fSJerome Brunet }; 7478c0cf40fSJerome Brunet }; 7488c0cf40fSJerome Brunet 7498c0cf40fSJerome Brunet spdif_out_a1_pins: spdif_out_a1 { 7508c0cf40fSJerome Brunet mux { 7518c0cf40fSJerome Brunet groups = "spdif_out_a1"; 7528c0cf40fSJerome Brunet function = "spdif_out"; 7531c5cc1c8SJerome Brunet bias-disable; 7548c0cf40fSJerome Brunet }; 7558c0cf40fSJerome Brunet }; 7568c0cf40fSJerome Brunet 7578c0cf40fSJerome Brunet spdif_out_a11_pins: spdif_out_a11 { 7588c0cf40fSJerome Brunet mux { 7598c0cf40fSJerome Brunet groups = "spdif_out_a11"; 7608c0cf40fSJerome Brunet function = "spdif_out"; 7611c5cc1c8SJerome Brunet bias-disable; 7628c0cf40fSJerome Brunet }; 7638c0cf40fSJerome Brunet }; 7648c0cf40fSJerome Brunet 7658c0cf40fSJerome Brunet spdif_out_a19_pins: spdif_out_a19 { 7668c0cf40fSJerome Brunet mux { 7678c0cf40fSJerome Brunet groups = "spdif_out_a19"; 7688c0cf40fSJerome Brunet function = "spdif_out"; 7691c5cc1c8SJerome Brunet bias-disable; 7708c0cf40fSJerome Brunet }; 7718c0cf40fSJerome Brunet }; 7728c0cf40fSJerome Brunet 7738c0cf40fSJerome Brunet spdif_out_a20_pins: spdif_out_a20 { 7748c0cf40fSJerome Brunet mux { 7758c0cf40fSJerome Brunet groups = "spdif_out_a20"; 7768c0cf40fSJerome Brunet function = "spdif_out"; 7771c5cc1c8SJerome Brunet bias-disable; 7788c0cf40fSJerome Brunet }; 7798c0cf40fSJerome Brunet }; 7808c0cf40fSJerome Brunet 7818c0cf40fSJerome Brunet spdif_out_z_pins: spdif_out_z { 7828c0cf40fSJerome Brunet mux { 7838c0cf40fSJerome Brunet groups = "spdif_out_z"; 7848c0cf40fSJerome Brunet function = "spdif_out"; 7851c5cc1c8SJerome Brunet bias-disable; 7868c0cf40fSJerome Brunet }; 7878c0cf40fSJerome Brunet }; 7888c0cf40fSJerome Brunet 7898c0cf40fSJerome Brunet spi0_pins: spi0 { 7908c0cf40fSJerome Brunet mux { 7918c0cf40fSJerome Brunet groups = "spi0_miso", 7928c0cf40fSJerome Brunet "spi0_mosi", 7938c0cf40fSJerome Brunet "spi0_clk"; 7948c0cf40fSJerome Brunet function = "spi0"; 7951c5cc1c8SJerome Brunet bias-disable; 7968c0cf40fSJerome Brunet }; 7978c0cf40fSJerome Brunet }; 7988c0cf40fSJerome Brunet 7998c0cf40fSJerome Brunet spi0_ss0_pins: spi0_ss0 { 8008c0cf40fSJerome Brunet mux { 8018c0cf40fSJerome Brunet groups = "spi0_ss0"; 8028c0cf40fSJerome Brunet function = "spi0"; 8031c5cc1c8SJerome Brunet bias-disable; 8048c0cf40fSJerome Brunet }; 8058c0cf40fSJerome Brunet }; 8068c0cf40fSJerome Brunet 8078c0cf40fSJerome Brunet spi0_ss1_pins: spi0_ss1 { 8088c0cf40fSJerome Brunet mux { 8098c0cf40fSJerome Brunet groups = "spi0_ss1"; 8108c0cf40fSJerome Brunet function = "spi0"; 8111c5cc1c8SJerome Brunet bias-disable; 8128c0cf40fSJerome Brunet }; 8138c0cf40fSJerome Brunet }; 8148c0cf40fSJerome Brunet 8158c0cf40fSJerome Brunet spi0_ss2_pins: spi0_ss2 { 8168c0cf40fSJerome Brunet mux { 8178c0cf40fSJerome Brunet groups = "spi0_ss2"; 8188c0cf40fSJerome Brunet function = "spi0"; 8191c5cc1c8SJerome Brunet bias-disable; 8208c0cf40fSJerome Brunet }; 8218c0cf40fSJerome Brunet }; 8228c0cf40fSJerome Brunet 8238c0cf40fSJerome Brunet spi1_a_pins: spi1_a { 8248c0cf40fSJerome Brunet mux { 8258c0cf40fSJerome Brunet groups = "spi1_miso_a", 8268c0cf40fSJerome Brunet "spi1_mosi_a", 8278c0cf40fSJerome Brunet "spi1_clk_a"; 8288c0cf40fSJerome Brunet function = "spi1"; 8291c5cc1c8SJerome Brunet bias-disable; 8308c0cf40fSJerome Brunet }; 8318c0cf40fSJerome Brunet }; 8328c0cf40fSJerome Brunet 8338c0cf40fSJerome Brunet spi1_ss0_a_pins: spi1_ss0_a { 8348c0cf40fSJerome Brunet mux { 8358c0cf40fSJerome Brunet groups = "spi1_ss0_a"; 8368c0cf40fSJerome Brunet function = "spi1"; 8371c5cc1c8SJerome Brunet bias-disable; 8388c0cf40fSJerome Brunet }; 8398c0cf40fSJerome Brunet }; 8408c0cf40fSJerome Brunet 8418c0cf40fSJerome Brunet spi1_ss1_pins: spi1_ss1 { 8428c0cf40fSJerome Brunet mux { 8438c0cf40fSJerome Brunet groups = "spi1_ss1"; 8448c0cf40fSJerome Brunet function = "spi1"; 8451c5cc1c8SJerome Brunet bias-disable; 8468c0cf40fSJerome Brunet }; 8478c0cf40fSJerome Brunet }; 8488c0cf40fSJerome Brunet 8498c0cf40fSJerome Brunet spi1_x_pins: spi1_x { 8508c0cf40fSJerome Brunet mux { 8518c0cf40fSJerome Brunet groups = "spi1_miso_x", 8528c0cf40fSJerome Brunet "spi1_mosi_x", 8538c0cf40fSJerome Brunet "spi1_clk_x"; 8548c0cf40fSJerome Brunet function = "spi1"; 8551c5cc1c8SJerome Brunet bias-disable; 8568c0cf40fSJerome Brunet }; 8578c0cf40fSJerome Brunet }; 8588c0cf40fSJerome Brunet 8598c0cf40fSJerome Brunet spi1_ss0_x_pins: spi1_ss0_x { 8608c0cf40fSJerome Brunet mux { 8618c0cf40fSJerome Brunet groups = "spi1_ss0_x"; 8628c0cf40fSJerome Brunet function = "spi1"; 8631c5cc1c8SJerome Brunet bias-disable; 8648c0cf40fSJerome Brunet }; 8658c0cf40fSJerome Brunet }; 8668c0cf40fSJerome Brunet 8678c0cf40fSJerome Brunet tdma_din0_pins: tdma_din0 { 8688c0cf40fSJerome Brunet mux { 8698c0cf40fSJerome Brunet groups = "tdma_din0"; 8708c0cf40fSJerome Brunet function = "tdma"; 8711c5cc1c8SJerome Brunet bias-disable; 8728c0cf40fSJerome Brunet }; 8738c0cf40fSJerome Brunet }; 8748c0cf40fSJerome Brunet 8758c0cf40fSJerome Brunet tdma_dout0_x14_pins: tdma_dout0_x14 { 8768c0cf40fSJerome Brunet mux { 8778c0cf40fSJerome Brunet groups = "tdma_dout0_x14"; 8788c0cf40fSJerome Brunet function = "tdma"; 8791c5cc1c8SJerome Brunet bias-disable; 8808c0cf40fSJerome Brunet }; 8818c0cf40fSJerome Brunet }; 8828c0cf40fSJerome Brunet 8838c0cf40fSJerome Brunet tdma_dout0_x15_pins: tdma_dout0_x15 { 8848c0cf40fSJerome Brunet mux { 8858c0cf40fSJerome Brunet groups = "tdma_dout0_x15"; 8868c0cf40fSJerome Brunet function = "tdma"; 8871c5cc1c8SJerome Brunet bias-disable; 8888c0cf40fSJerome Brunet }; 8898c0cf40fSJerome Brunet }; 8908c0cf40fSJerome Brunet 8918c0cf40fSJerome Brunet tdma_dout1_pins: tdma_dout1 { 8928c0cf40fSJerome Brunet mux { 8938c0cf40fSJerome Brunet groups = "tdma_dout1"; 8948c0cf40fSJerome Brunet function = "tdma"; 8951c5cc1c8SJerome Brunet bias-disable; 8968c0cf40fSJerome Brunet }; 8978c0cf40fSJerome Brunet }; 8988c0cf40fSJerome Brunet 8998c0cf40fSJerome Brunet tdma_din1_pins: tdma_din1 { 9008c0cf40fSJerome Brunet mux { 9018c0cf40fSJerome Brunet groups = "tdma_din1"; 9028c0cf40fSJerome Brunet function = "tdma"; 9031c5cc1c8SJerome Brunet bias-disable; 9048c0cf40fSJerome Brunet }; 9058c0cf40fSJerome Brunet }; 9068c0cf40fSJerome Brunet 9078c0cf40fSJerome Brunet tdma_fs_pins: tdma_fs { 9088c0cf40fSJerome Brunet mux { 9098c0cf40fSJerome Brunet groups = "tdma_fs"; 9108c0cf40fSJerome Brunet function = "tdma"; 9111c5cc1c8SJerome Brunet bias-disable; 9128c0cf40fSJerome Brunet }; 9138c0cf40fSJerome Brunet }; 9148c0cf40fSJerome Brunet 9158c0cf40fSJerome Brunet tdma_fs_slv_pins: tdma_fs_slv { 9168c0cf40fSJerome Brunet mux { 9178c0cf40fSJerome Brunet groups = "tdma_fs_slv"; 9188c0cf40fSJerome Brunet function = "tdma"; 9191c5cc1c8SJerome Brunet bias-disable; 9208c0cf40fSJerome Brunet }; 9218c0cf40fSJerome Brunet }; 9228c0cf40fSJerome Brunet 9238c0cf40fSJerome Brunet tdma_sclk_pins: tdma_sclk { 9248c0cf40fSJerome Brunet mux { 9258c0cf40fSJerome Brunet groups = "tdma_sclk"; 9268c0cf40fSJerome Brunet function = "tdma"; 9271c5cc1c8SJerome Brunet bias-disable; 9288c0cf40fSJerome Brunet }; 9298c0cf40fSJerome Brunet }; 9308c0cf40fSJerome Brunet 9318c0cf40fSJerome Brunet tdma_sclk_slv_pins: tdma_sclk_slv { 9328c0cf40fSJerome Brunet mux { 9338c0cf40fSJerome Brunet groups = "tdma_sclk_slv"; 9348c0cf40fSJerome Brunet function = "tdma"; 9351c5cc1c8SJerome Brunet bias-disable; 9368c0cf40fSJerome Brunet }; 9378c0cf40fSJerome Brunet }; 9388c0cf40fSJerome Brunet 9398c0cf40fSJerome Brunet tdmb_din0_pins: tdmb_din0 { 9408c0cf40fSJerome Brunet mux { 9418c0cf40fSJerome Brunet groups = "tdmb_din0"; 9428c0cf40fSJerome Brunet function = "tdmb"; 9431c5cc1c8SJerome Brunet bias-disable; 9448c0cf40fSJerome Brunet }; 9458c0cf40fSJerome Brunet }; 9468c0cf40fSJerome Brunet 9478c0cf40fSJerome Brunet tdmb_din1_pins: tdmb_din1 { 9488c0cf40fSJerome Brunet mux { 9498c0cf40fSJerome Brunet groups = "tdmb_din1"; 9508c0cf40fSJerome Brunet function = "tdmb"; 9511c5cc1c8SJerome Brunet bias-disable; 9528c0cf40fSJerome Brunet }; 9538c0cf40fSJerome Brunet }; 9548c0cf40fSJerome Brunet 9558c0cf40fSJerome Brunet tdmb_din2_pins: tdmb_din2 { 9568c0cf40fSJerome Brunet mux { 9578c0cf40fSJerome Brunet groups = "tdmb_din2"; 9588c0cf40fSJerome Brunet function = "tdmb"; 9591c5cc1c8SJerome Brunet bias-disable; 9608c0cf40fSJerome Brunet }; 9618c0cf40fSJerome Brunet }; 9628c0cf40fSJerome Brunet 9638c0cf40fSJerome Brunet tdmb_din3_pins: tdmb_din3 { 9648c0cf40fSJerome Brunet mux { 9658c0cf40fSJerome Brunet groups = "tdmb_din3"; 9668c0cf40fSJerome Brunet function = "tdmb"; 9671c5cc1c8SJerome Brunet bias-disable; 9688c0cf40fSJerome Brunet }; 9698c0cf40fSJerome Brunet }; 9708c0cf40fSJerome Brunet 9718c0cf40fSJerome Brunet tdmb_dout0_pins: tdmb_dout0 { 9728c0cf40fSJerome Brunet mux { 9738c0cf40fSJerome Brunet groups = "tdmb_dout0"; 9748c0cf40fSJerome Brunet function = "tdmb"; 9751c5cc1c8SJerome Brunet bias-disable; 9768c0cf40fSJerome Brunet }; 9778c0cf40fSJerome Brunet }; 9788c0cf40fSJerome Brunet 9798c0cf40fSJerome Brunet tdmb_dout1_pins: tdmb_dout1 { 9808c0cf40fSJerome Brunet mux { 9818c0cf40fSJerome Brunet groups = "tdmb_dout1"; 9828c0cf40fSJerome Brunet function = "tdmb"; 9831c5cc1c8SJerome Brunet bias-disable; 9848c0cf40fSJerome Brunet }; 9858c0cf40fSJerome Brunet }; 9868c0cf40fSJerome Brunet 9878c0cf40fSJerome Brunet tdmb_dout2_pins: tdmb_dout2 { 9888c0cf40fSJerome Brunet mux { 9898c0cf40fSJerome Brunet groups = "tdmb_dout2"; 9908c0cf40fSJerome Brunet function = "tdmb"; 9911c5cc1c8SJerome Brunet bias-disable; 9928c0cf40fSJerome Brunet }; 9938c0cf40fSJerome Brunet }; 9948c0cf40fSJerome Brunet 9958c0cf40fSJerome Brunet tdmb_dout3_pins: tdmb_dout3 { 9968c0cf40fSJerome Brunet mux { 9978c0cf40fSJerome Brunet groups = "tdmb_dout3"; 9988c0cf40fSJerome Brunet function = "tdmb"; 9991c5cc1c8SJerome Brunet bias-disable; 10008c0cf40fSJerome Brunet }; 10018c0cf40fSJerome Brunet }; 10028c0cf40fSJerome Brunet 10038c0cf40fSJerome Brunet tdmb_fs_pins: tdmb_fs { 10048c0cf40fSJerome Brunet mux { 10058c0cf40fSJerome Brunet groups = "tdmb_fs"; 10068c0cf40fSJerome Brunet function = "tdmb"; 10071c5cc1c8SJerome Brunet bias-disable; 10088c0cf40fSJerome Brunet }; 10098c0cf40fSJerome Brunet }; 10108c0cf40fSJerome Brunet 10118c0cf40fSJerome Brunet tdmb_fs_slv_pins: tdmb_fs_slv { 10128c0cf40fSJerome Brunet mux { 10138c0cf40fSJerome Brunet groups = "tdmb_fs_slv"; 10148c0cf40fSJerome Brunet function = "tdmb"; 10151c5cc1c8SJerome Brunet bias-disable; 10168c0cf40fSJerome Brunet }; 10178c0cf40fSJerome Brunet }; 10188c0cf40fSJerome Brunet 10198c0cf40fSJerome Brunet tdmb_sclk_pins: tdmb_sclk { 10208c0cf40fSJerome Brunet mux { 10218c0cf40fSJerome Brunet groups = "tdmb_sclk"; 10228c0cf40fSJerome Brunet function = "tdmb"; 10231c5cc1c8SJerome Brunet bias-disable; 10248c0cf40fSJerome Brunet }; 10258c0cf40fSJerome Brunet }; 10268c0cf40fSJerome Brunet 10278c0cf40fSJerome Brunet tdmb_sclk_slv_pins: tdmb_sclk_slv { 10288c0cf40fSJerome Brunet mux { 10298c0cf40fSJerome Brunet groups = "tdmb_sclk_slv"; 10308c0cf40fSJerome Brunet function = "tdmb"; 10311c5cc1c8SJerome Brunet bias-disable; 10328c0cf40fSJerome Brunet }; 10338c0cf40fSJerome Brunet }; 10348c0cf40fSJerome Brunet 10358c0cf40fSJerome Brunet tdmc_fs_pins: tdmc_fs { 10368c0cf40fSJerome Brunet mux { 10378c0cf40fSJerome Brunet groups = "tdmc_fs"; 10388c0cf40fSJerome Brunet function = "tdmc"; 10391c5cc1c8SJerome Brunet bias-disable; 10408c0cf40fSJerome Brunet }; 10418c0cf40fSJerome Brunet }; 10428c0cf40fSJerome Brunet 10438c0cf40fSJerome Brunet tdmc_fs_slv_pins: tdmc_fs_slv { 10448c0cf40fSJerome Brunet mux { 10458c0cf40fSJerome Brunet groups = "tdmc_fs_slv"; 10468c0cf40fSJerome Brunet function = "tdmc"; 10471c5cc1c8SJerome Brunet bias-disable; 10488c0cf40fSJerome Brunet }; 10498c0cf40fSJerome Brunet }; 10508c0cf40fSJerome Brunet 10518c0cf40fSJerome Brunet tdmc_sclk_pins: tdmc_sclk { 10528c0cf40fSJerome Brunet mux { 10538c0cf40fSJerome Brunet groups = "tdmc_sclk"; 10548c0cf40fSJerome Brunet function = "tdmc"; 10551c5cc1c8SJerome Brunet bias-disable; 10568c0cf40fSJerome Brunet }; 10578c0cf40fSJerome Brunet }; 10588c0cf40fSJerome Brunet 10598c0cf40fSJerome Brunet tdmc_sclk_slv_pins: tdmc_sclk_slv { 10608c0cf40fSJerome Brunet mux { 10618c0cf40fSJerome Brunet groups = "tdmc_sclk_slv"; 10628c0cf40fSJerome Brunet function = "tdmc"; 10631c5cc1c8SJerome Brunet bias-disable; 10648c0cf40fSJerome Brunet }; 10658c0cf40fSJerome Brunet }; 10668c0cf40fSJerome Brunet 10678c0cf40fSJerome Brunet tdmc_din0_pins: tdmc_din0 { 10688c0cf40fSJerome Brunet mux { 10698c0cf40fSJerome Brunet groups = "tdmc_din0"; 10708c0cf40fSJerome Brunet function = "tdmc"; 10711c5cc1c8SJerome Brunet bias-disable; 10728c0cf40fSJerome Brunet }; 10738c0cf40fSJerome Brunet }; 10748c0cf40fSJerome Brunet 10758c0cf40fSJerome Brunet tdmc_din1_pins: tdmc_din1 { 10768c0cf40fSJerome Brunet mux { 10778c0cf40fSJerome Brunet groups = "tdmc_din1"; 10788c0cf40fSJerome Brunet function = "tdmc"; 10791c5cc1c8SJerome Brunet bias-disable; 10808c0cf40fSJerome Brunet }; 10818c0cf40fSJerome Brunet }; 10828c0cf40fSJerome Brunet 10838c0cf40fSJerome Brunet tdmc_din2_pins: tdmc_din2 { 10848c0cf40fSJerome Brunet mux { 10858c0cf40fSJerome Brunet groups = "tdmc_din2"; 10868c0cf40fSJerome Brunet function = "tdmc"; 10871c5cc1c8SJerome Brunet bias-disable; 10888c0cf40fSJerome Brunet }; 10898c0cf40fSJerome Brunet }; 10908c0cf40fSJerome Brunet 10918c0cf40fSJerome Brunet tdmc_din3_pins: tdmc_din3 { 10928c0cf40fSJerome Brunet mux { 10938c0cf40fSJerome Brunet groups = "tdmc_din3"; 10948c0cf40fSJerome Brunet function = "tdmc"; 10951c5cc1c8SJerome Brunet bias-disable; 10968c0cf40fSJerome Brunet }; 10978c0cf40fSJerome Brunet }; 10988c0cf40fSJerome Brunet 10998c0cf40fSJerome Brunet tdmc_dout0_pins: tdmc_dout0 { 11008c0cf40fSJerome Brunet mux { 11018c0cf40fSJerome Brunet groups = "tdmc_dout0"; 11028c0cf40fSJerome Brunet function = "tdmc"; 11031c5cc1c8SJerome Brunet bias-disable; 11048c0cf40fSJerome Brunet }; 11058c0cf40fSJerome Brunet }; 11068c0cf40fSJerome Brunet 11078c0cf40fSJerome Brunet tdmc_dout1_pins: tdmc_dout1 { 11088c0cf40fSJerome Brunet mux { 11098c0cf40fSJerome Brunet groups = "tdmc_dout1"; 11108c0cf40fSJerome Brunet function = "tdmc"; 11111c5cc1c8SJerome Brunet bias-disable; 11128c0cf40fSJerome Brunet }; 11138c0cf40fSJerome Brunet }; 11148c0cf40fSJerome Brunet 11158c0cf40fSJerome Brunet tdmc_dout2_pins: tdmc_dout2 { 11168c0cf40fSJerome Brunet mux { 11178c0cf40fSJerome Brunet groups = "tdmc_dout2"; 11188c0cf40fSJerome Brunet function = "tdmc"; 11191c5cc1c8SJerome Brunet bias-disable; 11208c0cf40fSJerome Brunet }; 11218c0cf40fSJerome Brunet }; 11228c0cf40fSJerome Brunet 11238c0cf40fSJerome Brunet tdmc_dout3_pins: tdmc_dout3 { 11248c0cf40fSJerome Brunet mux { 11258c0cf40fSJerome Brunet groups = "tdmc_dout3"; 11268c0cf40fSJerome Brunet function = "tdmc"; 11271c5cc1c8SJerome Brunet bias-disable; 11288c0cf40fSJerome Brunet }; 11298c0cf40fSJerome Brunet }; 11308c0cf40fSJerome Brunet 11318c0cf40fSJerome Brunet uart_a_pins: uart_a { 11328c0cf40fSJerome Brunet mux { 11338c0cf40fSJerome Brunet groups = "uart_tx_a", 11348c0cf40fSJerome Brunet "uart_rx_a"; 11358c0cf40fSJerome Brunet function = "uart_a"; 11361c5cc1c8SJerome Brunet bias-disable; 11378c0cf40fSJerome Brunet }; 11388c0cf40fSJerome Brunet }; 11398c0cf40fSJerome Brunet 11408c0cf40fSJerome Brunet uart_a_cts_rts_pins: uart_a_cts_rts { 11418c0cf40fSJerome Brunet mux { 11428c0cf40fSJerome Brunet groups = "uart_cts_a", 11438c0cf40fSJerome Brunet "uart_rts_a"; 11448c0cf40fSJerome Brunet function = "uart_a"; 11451c5cc1c8SJerome Brunet bias-disable; 11468c0cf40fSJerome Brunet }; 11478c0cf40fSJerome Brunet }; 11488c0cf40fSJerome Brunet 11498c0cf40fSJerome Brunet uart_b_x_pins: uart_b_x { 11508c0cf40fSJerome Brunet mux { 11518c0cf40fSJerome Brunet groups = "uart_tx_b_x", 11528c0cf40fSJerome Brunet "uart_rx_b_x"; 11538c0cf40fSJerome Brunet function = "uart_b"; 11541c5cc1c8SJerome Brunet bias-disable; 11558c0cf40fSJerome Brunet }; 11568c0cf40fSJerome Brunet }; 11578c0cf40fSJerome Brunet 11588c0cf40fSJerome Brunet uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 11598c0cf40fSJerome Brunet mux { 11608c0cf40fSJerome Brunet groups = "uart_cts_b_x", 11618c0cf40fSJerome Brunet "uart_rts_b_x"; 11628c0cf40fSJerome Brunet function = "uart_b"; 11631c5cc1c8SJerome Brunet bias-disable; 11648c0cf40fSJerome Brunet }; 11658c0cf40fSJerome Brunet }; 11668c0cf40fSJerome Brunet 11678c0cf40fSJerome Brunet uart_b_z_pins: uart_b_z { 11688c0cf40fSJerome Brunet mux { 11698c0cf40fSJerome Brunet groups = "uart_tx_b_z", 11708c0cf40fSJerome Brunet "uart_rx_b_z"; 11718c0cf40fSJerome Brunet function = "uart_b"; 11721c5cc1c8SJerome Brunet bias-disable; 11738c0cf40fSJerome Brunet }; 11748c0cf40fSJerome Brunet }; 11758c0cf40fSJerome Brunet 11768c0cf40fSJerome Brunet uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 11778c0cf40fSJerome Brunet mux { 11788c0cf40fSJerome Brunet groups = "uart_cts_b_z", 11798c0cf40fSJerome Brunet "uart_rts_b_z"; 11808c0cf40fSJerome Brunet function = "uart_b"; 11811c5cc1c8SJerome Brunet bias-disable; 11828c0cf40fSJerome Brunet }; 11838c0cf40fSJerome Brunet }; 11848c0cf40fSJerome Brunet 11858c0cf40fSJerome Brunet uart_ao_b_z_pins: uart_ao_b_z { 11868c0cf40fSJerome Brunet mux { 11878c0cf40fSJerome Brunet groups = "uart_ao_tx_b_z", 11888c0cf40fSJerome Brunet "uart_ao_rx_b_z"; 11898c0cf40fSJerome Brunet function = "uart_ao_b_z"; 11901c5cc1c8SJerome Brunet bias-disable; 11918c0cf40fSJerome Brunet }; 11928c0cf40fSJerome Brunet }; 11938c0cf40fSJerome Brunet 11948c0cf40fSJerome Brunet uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 11958c0cf40fSJerome Brunet mux { 11968c0cf40fSJerome Brunet groups = "uart_ao_cts_b_z", 11978c0cf40fSJerome Brunet "uart_ao_rts_b_z"; 11988c0cf40fSJerome Brunet function = "uart_ao_b_z"; 11991c5cc1c8SJerome Brunet bias-disable; 12008c0cf40fSJerome Brunet }; 12018c0cf40fSJerome Brunet }; 12028c0cf40fSJerome Brunet }; 12038c0cf40fSJerome Brunet }; 12048c0cf40fSJerome Brunet 12058c0cf40fSJerome Brunet hiubus: bus@ff63c000 { 12068c0cf40fSJerome Brunet compatible = "simple-bus"; 12078c0cf40fSJerome Brunet reg = <0x0 0xff63c000 0x0 0x1c00>; 12088c0cf40fSJerome Brunet #address-cells = <2>; 12098c0cf40fSJerome Brunet #size-cells = <2>; 12108c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 12118c0cf40fSJerome Brunet 12128c0cf40fSJerome Brunet sysctrl: system-controller@0 { 12138c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-hhi-sysctrl", 1214445f2bdaSNeil Armstrong "simple-mfd", "syscon"; 12158c0cf40fSJerome Brunet reg = <0 0 0 0x400>; 12168c0cf40fSJerome Brunet 12178c0cf40fSJerome Brunet clkc: clock-controller { 12188c0cf40fSJerome Brunet compatible = "amlogic,axg-clkc"; 12198c0cf40fSJerome Brunet #clock-cells = <1>; 122016361ff2SJerome Brunet clocks = <&xtal>; 122116361ff2SJerome Brunet clock-names = "xtal"; 12228c0cf40fSJerome Brunet }; 122378a6dcb5SNeil Armstrong 122478a6dcb5SNeil Armstrong pwrc: power-controller { 122578a6dcb5SNeil Armstrong compatible = "amlogic,meson-axg-pwrc"; 122678a6dcb5SNeil Armstrong #power-domain-cells = <1>; 122778a6dcb5SNeil Armstrong amlogic,ao-sysctrl = <&sysctrl_AO>; 122878a6dcb5SNeil Armstrong resets = <&reset RESET_VIU>, 122978a6dcb5SNeil Armstrong <&reset RESET_VENC>, 123078a6dcb5SNeil Armstrong <&reset RESET_VCBUS>, 123178a6dcb5SNeil Armstrong <&reset RESET_VENCL>, 123278a6dcb5SNeil Armstrong <&reset RESET_VID_LOCK>; 123378a6dcb5SNeil Armstrong reset-names = "viu", "venc", "vcbus", 123478a6dcb5SNeil Armstrong "vencl", "vid_lock"; 123578a6dcb5SNeil Armstrong clocks = <&clkc CLKID_VPU>, 123678a6dcb5SNeil Armstrong <&clkc CLKID_VAPB>; 123778a6dcb5SNeil Armstrong clock-names = "vpu", "vapb"; 123878a6dcb5SNeil Armstrong /* 123978a6dcb5SNeil Armstrong * VPU clocking is provided by two identical clock paths 124078a6dcb5SNeil Armstrong * VPU_0 and VPU_1 muxed to a single clock by a glitch 124178a6dcb5SNeil Armstrong * free mux to safely change frequency while running. 124278a6dcb5SNeil Armstrong * Same for VAPB but with a final gate after the glitch free mux. 124378a6dcb5SNeil Armstrong */ 124478a6dcb5SNeil Armstrong assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 124578a6dcb5SNeil Armstrong <&clkc CLKID_VPU_0>, 124678a6dcb5SNeil Armstrong <&clkc CLKID_VPU>, /* Glitch free mux */ 124778a6dcb5SNeil Armstrong <&clkc CLKID_VAPB_0_SEL>, 124878a6dcb5SNeil Armstrong <&clkc CLKID_VAPB_0>, 124978a6dcb5SNeil Armstrong <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 125078a6dcb5SNeil Armstrong assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, 125178a6dcb5SNeil Armstrong <0>, /* Do Nothing */ 125278a6dcb5SNeil Armstrong <&clkc CLKID_VPU_0>, 125378a6dcb5SNeil Armstrong <&clkc CLKID_FCLK_DIV4>, 125478a6dcb5SNeil Armstrong <0>, /* Do Nothing */ 125578a6dcb5SNeil Armstrong <&clkc CLKID_VAPB_0>; 125678a6dcb5SNeil Armstrong assigned-clock-rates = <0>, /* Do Nothing */ 125778a6dcb5SNeil Armstrong <250000000>, 125878a6dcb5SNeil Armstrong <0>, /* Do Nothing */ 125978a6dcb5SNeil Armstrong <0>, /* Do Nothing */ 126078a6dcb5SNeil Armstrong <250000000>, 126178a6dcb5SNeil Armstrong <0>; /* Do Nothing */ 126278a6dcb5SNeil Armstrong }; 12633d3f1dfaSNeil Armstrong 12643d3f1dfaSNeil Armstrong mipi_pcie_analog_dphy: phy { 12653d3f1dfaSNeil Armstrong compatible = "amlogic,axg-mipi-pcie-analog-phy"; 12663d3f1dfaSNeil Armstrong #phy-cells = <0>; 12673d3f1dfaSNeil Armstrong status = "disabled"; 12683d3f1dfaSNeil Armstrong }; 12698c0cf40fSJerome Brunet }; 12708c0cf40fSJerome Brunet }; 12718c0cf40fSJerome Brunet 12729fdff382SJerome Brunet mailbox: mailbox@ff63c404 { 127301efc19cSNeil Armstrong compatible = "amlogic,meson-gxbb-mhu"; 12749fdff382SJerome Brunet reg = <0 0xff63c404 0 0x4c>; 12758c0cf40fSJerome Brunet interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 12768c0cf40fSJerome Brunet <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 12778c0cf40fSJerome Brunet <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 12788c0cf40fSJerome Brunet #mbox-cells = <1>; 1279221cf34bSNan Li }; 1280221cf34bSNan Li 12813d3f1dfaSNeil Armstrong mipi_dphy: phy@ff640000 { 12823d3f1dfaSNeil Armstrong compatible = "amlogic,axg-mipi-dphy"; 12833d3f1dfaSNeil Armstrong reg = <0x0 0xff640000 0x0 0x100>; 12843d3f1dfaSNeil Armstrong clocks = <&clkc CLKID_MIPI_DSI_PHY>; 12853d3f1dfaSNeil Armstrong clock-names = "pclk"; 12863d3f1dfaSNeil Armstrong resets = <&reset RESET_MIPI_PHY>; 12873d3f1dfaSNeil Armstrong reset-names = "phy"; 12883d3f1dfaSNeil Armstrong phys = <&mipi_pcie_analog_dphy>; 12893d3f1dfaSNeil Armstrong phy-names = "analog"; 12903d3f1dfaSNeil Armstrong #phy-cells = <0>; 12913d3f1dfaSNeil Armstrong status = "disabled"; 12923d3f1dfaSNeil Armstrong }; 12933d3f1dfaSNeil Armstrong 12948909e722SJerome Brunet audio: bus@ff642000 { 12958909e722SJerome Brunet compatible = "simple-bus"; 12968909e722SJerome Brunet reg = <0x0 0xff642000 0x0 0x2000>; 12978909e722SJerome Brunet #address-cells = <2>; 12988909e722SJerome Brunet #size-cells = <2>; 12998909e722SJerome Brunet ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 13008909e722SJerome Brunet 13018909e722SJerome Brunet clkc_audio: clock-controller@0 { 13028909e722SJerome Brunet compatible = "amlogic,axg-audio-clkc"; 13038909e722SJerome Brunet reg = <0x0 0x0 0x0 0xb4>; 13048909e722SJerome Brunet #clock-cells = <1>; 13058909e722SJerome Brunet 13068909e722SJerome Brunet clocks = <&clkc CLKID_AUDIO>, 13078909e722SJerome Brunet <&clkc CLKID_MPLL0>, 13088909e722SJerome Brunet <&clkc CLKID_MPLL1>, 13098909e722SJerome Brunet <&clkc CLKID_MPLL2>, 13108909e722SJerome Brunet <&clkc CLKID_MPLL3>, 13118909e722SJerome Brunet <&clkc CLKID_HIFI_PLL>, 13128909e722SJerome Brunet <&clkc CLKID_FCLK_DIV3>, 13138909e722SJerome Brunet <&clkc CLKID_FCLK_DIV4>, 13148909e722SJerome Brunet <&clkc CLKID_GP0_PLL>; 13158909e722SJerome Brunet clock-names = "pclk", 13168909e722SJerome Brunet "mst_in0", 13178909e722SJerome Brunet "mst_in1", 13188909e722SJerome Brunet "mst_in2", 13198909e722SJerome Brunet "mst_in3", 13208909e722SJerome Brunet "mst_in4", 13218909e722SJerome Brunet "mst_in5", 13228909e722SJerome Brunet "mst_in6", 13238909e722SJerome Brunet "mst_in7"; 13248909e722SJerome Brunet 13258909e722SJerome Brunet resets = <&reset RESET_AUDIO>; 13268909e722SJerome Brunet }; 132766d58a8fSJerome Brunet 1328f2b8f6a9SJerome Brunet toddr_a: audio-controller@100 { 1329f2b8f6a9SJerome Brunet compatible = "amlogic,axg-toddr"; 1330301b94d4SJerome Brunet reg = <0x0 0x100 0x0 0x2c>; 1331f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1332f2b8f6a9SJerome Brunet sound-name-prefix = "TODDR_A"; 1333f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1334f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1335f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_TODDR_A>; 1336be638075SJerome Brunet amlogic,fifo-depth = <512>; 1337f2b8f6a9SJerome Brunet status = "disabled"; 1338f2b8f6a9SJerome Brunet }; 1339f2b8f6a9SJerome Brunet 1340f2b8f6a9SJerome Brunet toddr_b: audio-controller@140 { 1341f2b8f6a9SJerome Brunet compatible = "amlogic,axg-toddr"; 1342301b94d4SJerome Brunet reg = <0x0 0x140 0x0 0x2c>; 1343f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1344f2b8f6a9SJerome Brunet sound-name-prefix = "TODDR_B"; 1345f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1346f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1347f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_TODDR_B>; 1348be638075SJerome Brunet amlogic,fifo-depth = <256>; 1349f2b8f6a9SJerome Brunet status = "disabled"; 1350f2b8f6a9SJerome Brunet }; 1351f2b8f6a9SJerome Brunet 1352f2b8f6a9SJerome Brunet toddr_c: audio-controller@180 { 1353f2b8f6a9SJerome Brunet compatible = "amlogic,axg-toddr"; 1354301b94d4SJerome Brunet reg = <0x0 0x180 0x0 0x2c>; 1355f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1356f2b8f6a9SJerome Brunet sound-name-prefix = "TODDR_C"; 1357f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1358f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1359f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_TODDR_C>; 1360be638075SJerome Brunet amlogic,fifo-depth = <256>; 1361f2b8f6a9SJerome Brunet status = "disabled"; 1362f2b8f6a9SJerome Brunet }; 1363f2b8f6a9SJerome Brunet 1364f2b8f6a9SJerome Brunet frddr_a: audio-controller@1c0 { 1365f2b8f6a9SJerome Brunet compatible = "amlogic,axg-frddr"; 1366301b94d4SJerome Brunet reg = <0x0 0x1c0 0x0 0x2c>; 1367f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1368f2b8f6a9SJerome Brunet sound-name-prefix = "FRDDR_A"; 1369f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1370f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1371f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_FRDDR_A>; 1372be638075SJerome Brunet amlogic,fifo-depth = <512>; 1373f2b8f6a9SJerome Brunet status = "disabled"; 1374f2b8f6a9SJerome Brunet }; 1375f2b8f6a9SJerome Brunet 1376f2b8f6a9SJerome Brunet frddr_b: audio-controller@200 { 1377f2b8f6a9SJerome Brunet compatible = "amlogic,axg-frddr"; 1378301b94d4SJerome Brunet reg = <0x0 0x200 0x0 0x2c>; 1379f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1380f2b8f6a9SJerome Brunet sound-name-prefix = "FRDDR_B"; 1381f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1382f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1383f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_FRDDR_B>; 1384be638075SJerome Brunet amlogic,fifo-depth = <256>; 1385f2b8f6a9SJerome Brunet status = "disabled"; 1386f2b8f6a9SJerome Brunet }; 1387f2b8f6a9SJerome Brunet 1388f2b8f6a9SJerome Brunet frddr_c: audio-controller@240 { 1389f2b8f6a9SJerome Brunet compatible = "amlogic,axg-frddr"; 1390301b94d4SJerome Brunet reg = <0x0 0x240 0x0 0x2c>; 1391f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1392f2b8f6a9SJerome Brunet sound-name-prefix = "FRDDR_C"; 1393f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1394f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1395f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_FRDDR_C>; 1396be638075SJerome Brunet amlogic,fifo-depth = <256>; 1397f2b8f6a9SJerome Brunet status = "disabled"; 1398f2b8f6a9SJerome Brunet }; 1399f2b8f6a9SJerome Brunet 140066d58a8fSJerome Brunet arb: reset-controller@280 { 140166d58a8fSJerome Brunet compatible = "amlogic,meson-axg-audio-arb"; 140266d58a8fSJerome Brunet reg = <0x0 0x280 0x0 0x4>; 140366d58a8fSJerome Brunet #reset-cells = <1>; 140466d58a8fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 140566d58a8fSJerome Brunet }; 1406f08c52deSJerome Brunet 1407bf8e4790SJerome Brunet tdmin_a: audio-controller@300 { 1408bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1409bf8e4790SJerome Brunet reg = <0x0 0x300 0x0 0x40>; 1410bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_A"; 1411bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1412bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1413bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1414bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1415bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1416bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1417bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1418bf8e4790SJerome Brunet status = "disabled"; 1419bf8e4790SJerome Brunet }; 1420bf8e4790SJerome Brunet 1421bf8e4790SJerome Brunet tdmin_b: audio-controller@340 { 1422bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1423bf8e4790SJerome Brunet reg = <0x0 0x340 0x0 0x40>; 1424bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_B"; 1425bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1426bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1427bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1428bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1429bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1430bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1431bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1432bf8e4790SJerome Brunet status = "disabled"; 1433bf8e4790SJerome Brunet }; 1434bf8e4790SJerome Brunet 1435bf8e4790SJerome Brunet tdmin_c: audio-controller@380 { 1436bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1437bf8e4790SJerome Brunet reg = <0x0 0x380 0x0 0x40>; 1438bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_C"; 1439bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1440bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1441bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1442bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1443bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1444bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1445bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1446bf8e4790SJerome Brunet status = "disabled"; 1447bf8e4790SJerome Brunet }; 1448bf8e4790SJerome Brunet 1449bf8e4790SJerome Brunet tdmin_lb: audio-controller@3c0 { 1450bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1451bf8e4790SJerome Brunet reg = <0x0 0x3c0 0x0 0x40>; 1452bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_LB"; 1453bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1454bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1455bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1456bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1457bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1458bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1459bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1460bf8e4790SJerome Brunet status = "disabled"; 1461bf8e4790SJerome Brunet }; 1462bf8e4790SJerome Brunet 14635e6a18acSJerome Brunet spdifin: audio-controller@400 { 14645e6a18acSJerome Brunet compatible = "amlogic,axg-spdifin"; 14655e6a18acSJerome Brunet reg = <0x0 0x400 0x0 0x30>; 14665e6a18acSJerome Brunet #sound-dai-cells = <0>; 14675e6a18acSJerome Brunet sound-name-prefix = "SPDIFIN"; 14685e6a18acSJerome Brunet interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 14695e6a18acSJerome Brunet clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 14705e6a18acSJerome Brunet <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 14715e6a18acSJerome Brunet clock-names = "pclk", "refclk"; 14725e6a18acSJerome Brunet status = "disabled"; 14735e6a18acSJerome Brunet }; 14745e6a18acSJerome Brunet 1475f08c52deSJerome Brunet spdifout: audio-controller@480 { 1476f08c52deSJerome Brunet compatible = "amlogic,axg-spdifout"; 1477f08c52deSJerome Brunet reg = <0x0 0x480 0x0 0x50>; 1478f08c52deSJerome Brunet #sound-dai-cells = <0>; 1479f08c52deSJerome Brunet sound-name-prefix = "SPDIFOUT"; 1480f08c52deSJerome Brunet clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1481f08c52deSJerome Brunet <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1482f08c52deSJerome Brunet clock-names = "pclk", "mclk"; 1483f08c52deSJerome Brunet status = "disabled"; 1484f08c52deSJerome Brunet }; 1485fd916739SJerome Brunet 1486fd916739SJerome Brunet tdmout_a: audio-controller@500 { 1487fd916739SJerome Brunet compatible = "amlogic,axg-tdmout"; 1488fd916739SJerome Brunet reg = <0x0 0x500 0x0 0x40>; 1489fd916739SJerome Brunet sound-name-prefix = "TDMOUT_A"; 1490fd916739SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1491fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1492fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1493fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1494fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1495fd916739SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1496fd916739SJerome Brunet "lrclk", "lrclk_sel"; 1497fd916739SJerome Brunet status = "disabled"; 1498fd916739SJerome Brunet }; 1499fd916739SJerome Brunet 1500fd916739SJerome Brunet tdmout_b: audio-controller@540 { 1501fd916739SJerome Brunet compatible = "amlogic,axg-tdmout"; 1502fd916739SJerome Brunet reg = <0x0 0x540 0x0 0x40>; 1503fd916739SJerome Brunet sound-name-prefix = "TDMOUT_B"; 1504fd916739SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1505fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1506fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1507fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1508fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1509fd916739SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1510fd916739SJerome Brunet "lrclk", "lrclk_sel"; 1511fd916739SJerome Brunet status = "disabled"; 1512fd916739SJerome Brunet }; 1513fd916739SJerome Brunet 1514fd916739SJerome Brunet tdmout_c: audio-controller@580 { 1515fd916739SJerome Brunet compatible = "amlogic,axg-tdmout"; 1516fd916739SJerome Brunet reg = <0x0 0x580 0x0 0x40>; 1517fd916739SJerome Brunet sound-name-prefix = "TDMOUT_C"; 1518fd916739SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1519fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1520fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1521fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1522fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1523fd916739SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1524fd916739SJerome Brunet "lrclk", "lrclk_sel"; 1525fd916739SJerome Brunet status = "disabled"; 1526fd916739SJerome Brunet }; 15278909e722SJerome Brunet }; 15288909e722SJerome Brunet 15290cb6c604SKevin Hilman aobus: bus@ff800000 { 15309d59b708SYixun Lan compatible = "simple-bus"; 15319d59b708SYixun Lan reg = <0x0 0xff800000 0x0 0x100000>; 15329d59b708SYixun Lan #address-cells = <2>; 15339d59b708SYixun Lan #size-cells = <2>; 15349d59b708SYixun Lan ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 15359d59b708SYixun Lan 1536e03421ecSQiufang Dai sysctrl_AO: sys-ctrl@0 { 1537445f2bdaSNeil Armstrong compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1538e03421ecSQiufang Dai reg = <0x0 0x0 0x0 0x100>; 1539e03421ecSQiufang Dai 1540e03421ecSQiufang Dai clkc_AO: clock-controller { 1541e03421ecSQiufang Dai compatible = "amlogic,meson-axg-aoclkc"; 1542e03421ecSQiufang Dai #clock-cells = <1>; 1543e03421ecSQiufang Dai #reset-cells = <1>; 154416361ff2SJerome Brunet clocks = <&xtal>, <&clkc CLKID_CLK81>; 154516361ff2SJerome Brunet clock-names = "xtal", "mpeg-clk"; 1546e03421ecSQiufang Dai }; 1547e03421ecSQiufang Dai }; 1548e03421ecSQiufang Dai 1549de05ded6SXingyu Chen pinctrl_aobus: pinctrl@14 { 1550de05ded6SXingyu Chen compatible = "amlogic,meson-axg-aobus-pinctrl"; 1551de05ded6SXingyu Chen #address-cells = <2>; 1552de05ded6SXingyu Chen #size-cells = <2>; 1553de05ded6SXingyu Chen ranges; 1554de05ded6SXingyu Chen 1555de05ded6SXingyu Chen gpio_ao: bank@14 { 1556de05ded6SXingyu Chen reg = <0x0 0x00014 0x0 0x8>, 1557de05ded6SXingyu Chen <0x0 0x0002c 0x0 0x4>, 1558de05ded6SXingyu Chen <0x0 0x00024 0x0 0x8>; 1559de05ded6SXingyu Chen reg-names = "mux", "pull", "gpio"; 1560de05ded6SXingyu Chen gpio-controller; 1561de05ded6SXingyu Chen #gpio-cells = <2>; 1562de05ded6SXingyu Chen gpio-ranges = <&pinctrl_aobus 0 0 15>; 1563de05ded6SXingyu Chen }; 15647bd46a79SYixun Lan 1565c054b6c2SJerome Brunet i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1566c054b6c2SJerome Brunet mux { 1567c054b6c2SJerome Brunet groups = "i2c_ao_sck_4"; 1568c054b6c2SJerome Brunet function = "i2c_ao"; 15691c5cc1c8SJerome Brunet bias-disable; 1570c054b6c2SJerome Brunet }; 1571c054b6c2SJerome Brunet }; 1572c054b6c2SJerome Brunet 1573c054b6c2SJerome Brunet i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1574c054b6c2SJerome Brunet mux { 1575c054b6c2SJerome Brunet groups = "i2c_ao_sck_8"; 1576c054b6c2SJerome Brunet function = "i2c_ao"; 15771c5cc1c8SJerome Brunet bias-disable; 1578c054b6c2SJerome Brunet }; 1579c054b6c2SJerome Brunet }; 1580c054b6c2SJerome Brunet 1581c054b6c2SJerome Brunet i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1582c054b6c2SJerome Brunet mux { 1583c054b6c2SJerome Brunet groups = "i2c_ao_sck_10"; 1584c054b6c2SJerome Brunet function = "i2c_ao"; 15851c5cc1c8SJerome Brunet bias-disable; 1586c054b6c2SJerome Brunet }; 1587c054b6c2SJerome Brunet }; 1588c054b6c2SJerome Brunet 1589c054b6c2SJerome Brunet i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1590c054b6c2SJerome Brunet mux { 1591c054b6c2SJerome Brunet groups = "i2c_ao_sda_5"; 1592c054b6c2SJerome Brunet function = "i2c_ao"; 15931c5cc1c8SJerome Brunet bias-disable; 1594c054b6c2SJerome Brunet }; 1595c054b6c2SJerome Brunet }; 1596c054b6c2SJerome Brunet 1597c054b6c2SJerome Brunet i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1598c054b6c2SJerome Brunet mux { 1599c054b6c2SJerome Brunet groups = "i2c_ao_sda_9"; 1600c054b6c2SJerome Brunet function = "i2c_ao"; 16011c5cc1c8SJerome Brunet bias-disable; 1602c054b6c2SJerome Brunet }; 1603c054b6c2SJerome Brunet }; 1604c054b6c2SJerome Brunet 1605c054b6c2SJerome Brunet i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1606c054b6c2SJerome Brunet mux { 1607c054b6c2SJerome Brunet groups = "i2c_ao_sda_11"; 1608c054b6c2SJerome Brunet function = "i2c_ao"; 16091c5cc1c8SJerome Brunet bias-disable; 1610c054b6c2SJerome Brunet }; 1611c054b6c2SJerome Brunet }; 1612c054b6c2SJerome Brunet 16137bd46a79SYixun Lan remote_input_ao_pins: remote_input_ao { 16147bd46a79SYixun Lan mux { 16157bd46a79SYixun Lan groups = "remote_input_ao"; 16167bd46a79SYixun Lan function = "remote_input_ao"; 16171c5cc1c8SJerome Brunet bias-disable; 16187bd46a79SYixun Lan }; 16197bd46a79SYixun Lan }; 16204eae66a6SYixun Lan 16214eae66a6SYixun Lan uart_ao_a_pins: uart_ao_a { 16224eae66a6SYixun Lan mux { 16234eae66a6SYixun Lan groups = "uart_ao_tx_a", 16244eae66a6SYixun Lan "uart_ao_rx_a"; 16254eae66a6SYixun Lan function = "uart_ao_a"; 16261c5cc1c8SJerome Brunet bias-disable; 16274eae66a6SYixun Lan }; 16284eae66a6SYixun Lan }; 16294eae66a6SYixun Lan 16304eae66a6SYixun Lan uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 16314eae66a6SYixun Lan mux { 16324eae66a6SYixun Lan groups = "uart_ao_cts_a", 16334eae66a6SYixun Lan "uart_ao_rts_a"; 16344eae66a6SYixun Lan function = "uart_ao_a"; 16351c5cc1c8SJerome Brunet bias-disable; 16364eae66a6SYixun Lan }; 16374eae66a6SYixun Lan }; 16384eae66a6SYixun Lan 16394eae66a6SYixun Lan uart_ao_b_pins: uart_ao_b { 16404eae66a6SYixun Lan mux { 16414eae66a6SYixun Lan groups = "uart_ao_tx_b", 16424eae66a6SYixun Lan "uart_ao_rx_b"; 16434eae66a6SYixun Lan function = "uart_ao_b"; 16441c5cc1c8SJerome Brunet bias-disable; 16454eae66a6SYixun Lan }; 16464eae66a6SYixun Lan }; 16474eae66a6SYixun Lan 16484eae66a6SYixun Lan uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 16494eae66a6SYixun Lan mux { 16504eae66a6SYixun Lan groups = "uart_ao_cts_b", 16514eae66a6SYixun Lan "uart_ao_rts_b"; 16524eae66a6SYixun Lan function = "uart_ao_b"; 16531c5cc1c8SJerome Brunet bias-disable; 16544eae66a6SYixun Lan }; 16554eae66a6SYixun Lan }; 1656de05ded6SXingyu Chen }; 1657de05ded6SXingyu Chen 1658a04c18cbSJerome Brunet sec_AO: ao-secure@140 { 1659a04c18cbSJerome Brunet compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1660a04c18cbSJerome Brunet reg = <0x0 0x140 0x0 0x140>; 1661a04c18cbSJerome Brunet amlogic,has-chip-id; 1662a04c18cbSJerome Brunet }; 1663a04c18cbSJerome Brunet 16644a81e5ddSJian Hu pwm_AO_cd: pwm@2000 { 1665b4ff05caSJerome Brunet compatible = "amlogic,meson-axg-ao-pwm"; 16664a81e5ddSJian Hu reg = <0x0 0x02000 0x0 0x20>; 16674a81e5ddSJian Hu #pwm-cells = <3>; 16684a81e5ddSJian Hu status = "disabled"; 16694a81e5ddSJian Hu }; 16704a81e5ddSJian Hu 16719d59b708SYixun Lan uart_AO: serial@3000 { 16729d59b708SYixun Lan compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 16739d59b708SYixun Lan reg = <0x0 0x3000 0x0 0x18>; 16749d59b708SYixun Lan interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 16759adda353SYixun Lan clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 16769d59b708SYixun Lan clock-names = "xtal", "pclk", "baud"; 16779d59b708SYixun Lan status = "disabled"; 16789d59b708SYixun Lan }; 16799d59b708SYixun Lan 16809d59b708SYixun Lan uart_AO_B: serial@4000 { 16819d59b708SYixun Lan compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 16829d59b708SYixun Lan reg = <0x0 0x4000 0x0 0x18>; 16839d59b708SYixun Lan interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 16849adda353SYixun Lan clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 16859d59b708SYixun Lan clock-names = "xtal", "pclk", "baud"; 16869d59b708SYixun Lan status = "disabled"; 16879d59b708SYixun Lan }; 16887bd46a79SYixun Lan 16898c0cf40fSJerome Brunet i2c_AO: i2c@5000 { 16908c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 16918c0cf40fSJerome Brunet reg = <0x0 0x05000 0x0 0x20>; 16928c0cf40fSJerome Brunet interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 16938c0cf40fSJerome Brunet clocks = <&clkc CLKID_AO_I2C>; 16948c0cf40fSJerome Brunet #address-cells = <1>; 16958c0cf40fSJerome Brunet #size-cells = <0>; 16968c0cf40fSJerome Brunet status = "disabled"; 16978c0cf40fSJerome Brunet }; 16988c0cf40fSJerome Brunet 16998c0cf40fSJerome Brunet pwm_AO_ab: pwm@7000 { 17008c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-ao-pwm"; 17018c0cf40fSJerome Brunet reg = <0x0 0x07000 0x0 0x20>; 17028c0cf40fSJerome Brunet #pwm-cells = <3>; 17038c0cf40fSJerome Brunet status = "disabled"; 17048c0cf40fSJerome Brunet }; 17058c0cf40fSJerome Brunet 17067bd46a79SYixun Lan ir: ir@8000 { 17077bd46a79SYixun Lan compatible = "amlogic,meson-gxbb-ir"; 17087bd46a79SYixun Lan reg = <0x0 0x8000 0x0 0x20>; 17097bd46a79SYixun Lan interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 17107bd46a79SYixun Lan status = "disabled"; 17117bd46a79SYixun Lan }; 1712a51b74eaSXingyu Chen 1713a51b74eaSXingyu Chen saradc: adc@9000 { 1714a51b74eaSXingyu Chen compatible = "amlogic,meson-axg-saradc", 1715a51b74eaSXingyu Chen "amlogic,meson-saradc"; 1716a51b74eaSXingyu Chen reg = <0x0 0x9000 0x0 0x38>; 1717a51b74eaSXingyu Chen #io-channel-cells = <1>; 1718a51b74eaSXingyu Chen interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1719a51b74eaSXingyu Chen clocks = <&xtal>, 1720a51b74eaSXingyu Chen <&clkc_AO CLKID_AO_SAR_ADC>, 1721a51b74eaSXingyu Chen <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1722a51b74eaSXingyu Chen <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1723a51b74eaSXingyu Chen clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1724a51b74eaSXingyu Chen status = "disabled"; 1725a51b74eaSXingyu Chen }; 17269d59b708SYixun Lan }; 17278c0cf40fSJerome Brunet 1728b03455aeSNeil Armstrong ge2d: ge2d@ff940000 { 1729b03455aeSNeil Armstrong compatible = "amlogic,axg-ge2d"; 1730b03455aeSNeil Armstrong reg = <0x0 0xff940000 0x0 0x10000>; 1731b03455aeSNeil Armstrong interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1732b03455aeSNeil Armstrong clocks = <&clkc CLKID_VAPB>; 1733b03455aeSNeil Armstrong resets = <&reset RESET_GE2D>; 1734b03455aeSNeil Armstrong }; 1735b03455aeSNeil Armstrong 17368c0cf40fSJerome Brunet gic: interrupt-controller@ffc01000 { 17378c0cf40fSJerome Brunet compatible = "arm,gic-400"; 17388c0cf40fSJerome Brunet reg = <0x0 0xffc01000 0 0x1000>, 17398c0cf40fSJerome Brunet <0x0 0xffc02000 0 0x2000>, 17408c0cf40fSJerome Brunet <0x0 0xffc04000 0 0x2000>, 17418c0cf40fSJerome Brunet <0x0 0xffc06000 0 0x2000>; 17428c0cf40fSJerome Brunet interrupt-controller; 17438c0cf40fSJerome Brunet interrupts = <GIC_PPI 9 17448c0cf40fSJerome Brunet (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 17458c0cf40fSJerome Brunet #interrupt-cells = <3>; 17468c0cf40fSJerome Brunet #address-cells = <0>; 17478c0cf40fSJerome Brunet }; 17488c0cf40fSJerome Brunet 17498c0cf40fSJerome Brunet cbus: bus@ffd00000 { 17508c0cf40fSJerome Brunet compatible = "simple-bus"; 17518c0cf40fSJerome Brunet reg = <0x0 0xffd00000 0x0 0x25000>; 17528c0cf40fSJerome Brunet #address-cells = <2>; 17538c0cf40fSJerome Brunet #size-cells = <2>; 17548c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 17558c0cf40fSJerome Brunet 17568c0cf40fSJerome Brunet reset: reset-controller@1004 { 17578c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-reset"; 17588c0cf40fSJerome Brunet reg = <0x0 0x01004 0x0 0x9c>; 17598c0cf40fSJerome Brunet #reset-cells = <1>; 17608c0cf40fSJerome Brunet }; 17618c0cf40fSJerome Brunet 17628c0cf40fSJerome Brunet gpio_intc: interrupt-controller@f080 { 1763cbddb02eSCarlo Caione compatible = "amlogic,meson-axg-gpio-intc", 1764cbddb02eSCarlo Caione "amlogic,meson-gpio-intc"; 17658c0cf40fSJerome Brunet reg = <0x0 0xf080 0x0 0x10>; 17668c0cf40fSJerome Brunet interrupt-controller; 17678c0cf40fSJerome Brunet #interrupt-cells = <2>; 17688c0cf40fSJerome Brunet amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 17698c0cf40fSJerome Brunet }; 17708c0cf40fSJerome Brunet 17716f31ba17SCarlo Caione watchdog@f0d0 { 17726f31ba17SCarlo Caione compatible = "amlogic,meson-gxbb-wdt"; 17736f31ba17SCarlo Caione reg = <0x0 0xf0d0 0x0 0x10>; 17746f31ba17SCarlo Caione clocks = <&xtal>; 17756f31ba17SCarlo Caione }; 17766f31ba17SCarlo Caione 17778c0cf40fSJerome Brunet pwm_ab: pwm@1b000 { 17788c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-ee-pwm"; 17798c0cf40fSJerome Brunet reg = <0x0 0x1b000 0x0 0x20>; 17808c0cf40fSJerome Brunet #pwm-cells = <3>; 17818c0cf40fSJerome Brunet status = "disabled"; 17828c0cf40fSJerome Brunet }; 17838c0cf40fSJerome Brunet 17848c0cf40fSJerome Brunet pwm_cd: pwm@1a000 { 17858c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-ee-pwm"; 17868c0cf40fSJerome Brunet reg = <0x0 0x1a000 0x0 0x20>; 17878c0cf40fSJerome Brunet #pwm-cells = <3>; 17888c0cf40fSJerome Brunet status = "disabled"; 17898c0cf40fSJerome Brunet }; 17908c0cf40fSJerome Brunet 17918c0cf40fSJerome Brunet spicc0: spi@13000 { 17928c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-spicc"; 17938c0cf40fSJerome Brunet reg = <0x0 0x13000 0x0 0x3c>; 17948c0cf40fSJerome Brunet interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 17958c0cf40fSJerome Brunet clocks = <&clkc CLKID_SPICC0>; 17968c0cf40fSJerome Brunet clock-names = "core"; 17978c0cf40fSJerome Brunet #address-cells = <1>; 17988c0cf40fSJerome Brunet #size-cells = <0>; 17998c0cf40fSJerome Brunet status = "disabled"; 18008c0cf40fSJerome Brunet }; 18018c0cf40fSJerome Brunet 18028c0cf40fSJerome Brunet spicc1: spi@15000 { 18038c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-spicc"; 18048c0cf40fSJerome Brunet reg = <0x0 0x15000 0x0 0x3c>; 18058c0cf40fSJerome Brunet interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 18068c0cf40fSJerome Brunet clocks = <&clkc CLKID_SPICC1>; 18078c0cf40fSJerome Brunet clock-names = "core"; 18088c0cf40fSJerome Brunet #address-cells = <1>; 18098c0cf40fSJerome Brunet #size-cells = <0>; 18108c0cf40fSJerome Brunet status = "disabled"; 18118c0cf40fSJerome Brunet }; 18128c0cf40fSJerome Brunet 1813fea888bdSJerome Brunet clk_msr: clock-measure@18000 { 1814fea888bdSJerome Brunet compatible = "amlogic,meson-axg-clk-measure"; 1815fea888bdSJerome Brunet reg = <0x0 0x18000 0x0 0x10>; 1816fea888bdSJerome Brunet }; 1817fea888bdSJerome Brunet 18188c0cf40fSJerome Brunet i2c3: i2c@1c000 { 18198c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 18208c0cf40fSJerome Brunet reg = <0x0 0x1c000 0x0 0x20>; 18218c0cf40fSJerome Brunet interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 18228c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 18238c0cf40fSJerome Brunet #address-cells = <1>; 18248c0cf40fSJerome Brunet #size-cells = <0>; 18258c0cf40fSJerome Brunet status = "disabled"; 18268c0cf40fSJerome Brunet }; 18278c0cf40fSJerome Brunet 18288c0cf40fSJerome Brunet i2c2: i2c@1d000 { 18298c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 18308c0cf40fSJerome Brunet reg = <0x0 0x1d000 0x0 0x20>; 18318c0cf40fSJerome Brunet interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 18328c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 18338c0cf40fSJerome Brunet #address-cells = <1>; 18348c0cf40fSJerome Brunet #size-cells = <0>; 18358c0cf40fSJerome Brunet status = "disabled"; 18368c0cf40fSJerome Brunet }; 18378c0cf40fSJerome Brunet 18388c0cf40fSJerome Brunet i2c1: i2c@1e000 { 18398c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 18408c0cf40fSJerome Brunet reg = <0x0 0x1e000 0x0 0x20>; 18418c0cf40fSJerome Brunet interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 18428c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 18438c0cf40fSJerome Brunet #address-cells = <1>; 18448c0cf40fSJerome Brunet #size-cells = <0>; 18458c0cf40fSJerome Brunet status = "disabled"; 18468c0cf40fSJerome Brunet }; 18478c0cf40fSJerome Brunet 18488c0cf40fSJerome Brunet i2c0: i2c@1f000 { 18498c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 18508c0cf40fSJerome Brunet reg = <0x0 0x1f000 0x0 0x20>; 18518c0cf40fSJerome Brunet interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 18528c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 18538c0cf40fSJerome Brunet #address-cells = <1>; 18548c0cf40fSJerome Brunet #size-cells = <0>; 18558c0cf40fSJerome Brunet status = "disabled"; 18568c0cf40fSJerome Brunet }; 18578c0cf40fSJerome Brunet 18588c0cf40fSJerome Brunet uart_B: serial@23000 { 18598c0cf40fSJerome Brunet compatible = "amlogic,meson-gx-uart"; 18608c0cf40fSJerome Brunet reg = <0x0 0x23000 0x0 0x18>; 18618c0cf40fSJerome Brunet interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 18628c0cf40fSJerome Brunet status = "disabled"; 18638c0cf40fSJerome Brunet clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 18648c0cf40fSJerome Brunet clock-names = "xtal", "pclk", "baud"; 18658c0cf40fSJerome Brunet }; 18668c0cf40fSJerome Brunet 18678c0cf40fSJerome Brunet uart_A: serial@24000 { 18688c0cf40fSJerome Brunet compatible = "amlogic,meson-gx-uart"; 18698c0cf40fSJerome Brunet reg = <0x0 0x24000 0x0 0x18>; 18708c0cf40fSJerome Brunet interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 18718c0cf40fSJerome Brunet status = "disabled"; 18728c0cf40fSJerome Brunet clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 18738c0cf40fSJerome Brunet clock-names = "xtal", "pclk", "baud"; 1874*a270a2b2SNeil Armstrong fifo-size = <128>; 18758c0cf40fSJerome Brunet }; 18768c0cf40fSJerome Brunet }; 18778c0cf40fSJerome Brunet 18788c0cf40fSJerome Brunet apb: bus@ffe00000 { 18798c0cf40fSJerome Brunet compatible = "simple-bus"; 18808c0cf40fSJerome Brunet reg = <0x0 0xffe00000 0x0 0x200000>; 18818c0cf40fSJerome Brunet #address-cells = <2>; 18828c0cf40fSJerome Brunet #size-cells = <2>; 18838c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 18848c0cf40fSJerome Brunet 18858c0cf40fSJerome Brunet sd_emmc_b: sd@5000 { 18868c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-mmc"; 18878c0cf40fSJerome Brunet reg = <0x0 0x5000 0x0 0x800>; 18888c0cf40fSJerome Brunet interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 18898c0cf40fSJerome Brunet status = "disabled"; 18908c0cf40fSJerome Brunet clocks = <&clkc CLKID_SD_EMMC_B>, 18918c0cf40fSJerome Brunet <&clkc CLKID_SD_EMMC_B_CLK0>, 18928c0cf40fSJerome Brunet <&clkc CLKID_FCLK_DIV2>; 18938c0cf40fSJerome Brunet clock-names = "core", "clkin0", "clkin1"; 18948c0cf40fSJerome Brunet resets = <&reset RESET_SD_EMMC_B>; 18958c0cf40fSJerome Brunet }; 18968c0cf40fSJerome Brunet 18978c0cf40fSJerome Brunet sd_emmc_c: mmc@7000 { 18988c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-mmc"; 18998c0cf40fSJerome Brunet reg = <0x0 0x7000 0x0 0x800>; 19008c0cf40fSJerome Brunet interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 19018c0cf40fSJerome Brunet status = "disabled"; 19028c0cf40fSJerome Brunet clocks = <&clkc CLKID_SD_EMMC_C>, 19038c0cf40fSJerome Brunet <&clkc CLKID_SD_EMMC_C_CLK0>, 19048c0cf40fSJerome Brunet <&clkc CLKID_FCLK_DIV2>; 19058c0cf40fSJerome Brunet clock-names = "core", "clkin0", "clkin1"; 19068c0cf40fSJerome Brunet resets = <&reset RESET_SD_EMMC_C>; 19078c0cf40fSJerome Brunet }; 19081b208babSNeil Armstrong 19091b208babSNeil Armstrong usb2_phy1: phy@9020 { 19101b208babSNeil Armstrong compatible = "amlogic,meson-gxl-usb2-phy"; 19111b208babSNeil Armstrong #phy-cells = <0>; 19121b208babSNeil Armstrong reg = <0x0 0x9020 0x0 0x20>; 19131b208babSNeil Armstrong clocks = <&clkc CLKID_USB>; 19141b208babSNeil Armstrong clock-names = "phy"; 19151b208babSNeil Armstrong resets = <&reset RESET_USB_OTG>; 19161b208babSNeil Armstrong reset-names = "phy"; 19171b208babSNeil Armstrong }; 19188c0cf40fSJerome Brunet }; 19198c0cf40fSJerome Brunet 19208c0cf40fSJerome Brunet sram: sram@fffc0000 { 19219ecded10SNeil Armstrong compatible = "mmio-sram"; 19228c0cf40fSJerome Brunet reg = <0x0 0xfffc0000 0x0 0x20000>; 19238c0cf40fSJerome Brunet #address-cells = <1>; 19248c0cf40fSJerome Brunet #size-cells = <1>; 19258c0cf40fSJerome Brunet ranges = <0 0x0 0xfffc0000 0x20000>; 19268c0cf40fSJerome Brunet 19279ecded10SNeil Armstrong cpu_scp_lpri: scp-sram@13000 { 19288c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-scp-shmem"; 19298c0cf40fSJerome Brunet reg = <0x13000 0x400>; 19308c0cf40fSJerome Brunet }; 19318c0cf40fSJerome Brunet 19329ecded10SNeil Armstrong cpu_scp_hpri: scp-sram@13400 { 19338c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-scp-shmem"; 19348c0cf40fSJerome Brunet reg = <0x13400 0x400>; 19358c0cf40fSJerome Brunet }; 19368c0cf40fSJerome Brunet }; 19378c0cf40fSJerome Brunet }; 19388c0cf40fSJerome Brunet 19398c0cf40fSJerome Brunet timer { 19408c0cf40fSJerome Brunet compatible = "arm,armv8-timer"; 19418c0cf40fSJerome Brunet interrupts = <GIC_PPI 13 19428c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 19438c0cf40fSJerome Brunet <GIC_PPI 14 19448c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 19458c0cf40fSJerome Brunet <GIC_PPI 11 19468c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 19478c0cf40fSJerome Brunet <GIC_PPI 10 19488c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 19498c0cf40fSJerome Brunet }; 19508c0cf40fSJerome Brunet 19518c0cf40fSJerome Brunet xtal: xtal-clk { 19528c0cf40fSJerome Brunet compatible = "fixed-clock"; 19538c0cf40fSJerome Brunet clock-frequency = <24000000>; 19548c0cf40fSJerome Brunet clock-output-names = "xtal"; 19558c0cf40fSJerome Brunet #clock-cells = <0>; 19569d59b708SYixun Lan }; 19579d59b708SYixun Lan}; 1958