1114abfe1SNeil Armstrong// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
29d59b708SYixun Lan/*
39d59b708SYixun Lan * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
49d59b708SYixun Lan */
59d59b708SYixun Lan
68c0cf40fSJerome Brunet#include <dt-bindings/clock/axg-aoclkc.h>
78909e722SJerome Brunet#include <dt-bindings/clock/axg-audio-clkc.h>
806b7a631SYixun Lan#include <dt-bindings/clock/axg-clkc.h>
98c0cf40fSJerome Brunet#include <dt-bindings/gpio/gpio.h>
10221cf34bSNan Li#include <dt-bindings/gpio/meson-axg-gpio.h>
118c0cf40fSJerome Brunet#include <dt-bindings/interrupt-controller/irq.h>
128c0cf40fSJerome Brunet#include <dt-bindings/interrupt-controller/arm-gic.h>
13f2b8f6a9SJerome Brunet#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
148c0cf40fSJerome Brunet#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
159d59b708SYixun Lan
169d59b708SYixun Lan/ {
179d59b708SYixun Lan	compatible = "amlogic,meson-axg";
189d59b708SYixun Lan
199d59b708SYixun Lan	interrupt-parent = <&gic>;
209d59b708SYixun Lan	#address-cells = <2>;
219d59b708SYixun Lan	#size-cells = <2>;
229d59b708SYixun Lan
238c0cf40fSJerome Brunet	tdmif_a: audio-controller@0 {
248c0cf40fSJerome Brunet		compatible = "amlogic,axg-tdm-iface";
258c0cf40fSJerome Brunet		#sound-dai-cells = <0>;
268c0cf40fSJerome Brunet		sound-name-prefix = "TDM_A";
278c0cf40fSJerome Brunet		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
288c0cf40fSJerome Brunet			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
298c0cf40fSJerome Brunet			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
308c0cf40fSJerome Brunet		clock-names = "mclk", "sclk", "lrclk";
318c0cf40fSJerome Brunet		status = "disabled";
329d59b708SYixun Lan	};
339d59b708SYixun Lan
348c0cf40fSJerome Brunet	tdmif_b: audio-controller@1 {
358c0cf40fSJerome Brunet		compatible = "amlogic,axg-tdm-iface";
368c0cf40fSJerome Brunet		#sound-dai-cells = <0>;
378c0cf40fSJerome Brunet		sound-name-prefix = "TDM_B";
388c0cf40fSJerome Brunet		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
398c0cf40fSJerome Brunet			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
408c0cf40fSJerome Brunet			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
418c0cf40fSJerome Brunet		clock-names = "mclk", "sclk", "lrclk";
428c0cf40fSJerome Brunet		status = "disabled";
439d59b708SYixun Lan	};
448c0cf40fSJerome Brunet
458c0cf40fSJerome Brunet	tdmif_c: audio-controller@2 {
468c0cf40fSJerome Brunet		compatible = "amlogic,axg-tdm-iface";
478c0cf40fSJerome Brunet		#sound-dai-cells = <0>;
488c0cf40fSJerome Brunet		sound-name-prefix = "TDM_C";
498c0cf40fSJerome Brunet		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
508c0cf40fSJerome Brunet			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
518c0cf40fSJerome Brunet			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
528c0cf40fSJerome Brunet		clock-names = "mclk", "sclk", "lrclk";
538c0cf40fSJerome Brunet		status = "disabled";
548c0cf40fSJerome Brunet	};
558c0cf40fSJerome Brunet
568c0cf40fSJerome Brunet	ao_alt_xtal: ao_alt_xtal-clk {
578c0cf40fSJerome Brunet		compatible = "fixed-clock";
588c0cf40fSJerome Brunet		clock-frequency = <32000000>;
598c0cf40fSJerome Brunet		clock-output-names = "ao_alt_xtal";
608c0cf40fSJerome Brunet		#clock-cells = <0>;
618c0cf40fSJerome Brunet	};
628c0cf40fSJerome Brunet
638c0cf40fSJerome Brunet	arm-pmu {
648c0cf40fSJerome Brunet		compatible = "arm,cortex-a53-pmu";
658c0cf40fSJerome Brunet		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
668c0cf40fSJerome Brunet			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
678c0cf40fSJerome Brunet			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
688c0cf40fSJerome Brunet			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
698c0cf40fSJerome Brunet		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
709d59b708SYixun Lan	};
719d59b708SYixun Lan
729d59b708SYixun Lan	cpus {
739d59b708SYixun Lan		#address-cells = <0x2>;
749d59b708SYixun Lan		#size-cells = <0x0>;
759d59b708SYixun Lan
769d59b708SYixun Lan		cpu0: cpu@0 {
779d59b708SYixun Lan			device_type = "cpu";
789d59b708SYixun Lan			compatible = "arm,cortex-a53", "arm,armv8";
799d59b708SYixun Lan			reg = <0x0 0x0>;
809d59b708SYixun Lan			enable-method = "psci";
819d59b708SYixun Lan			next-level-cache = <&l2>;
829d59b708SYixun Lan		};
839d59b708SYixun Lan
849d59b708SYixun Lan		cpu1: cpu@1 {
859d59b708SYixun Lan			device_type = "cpu";
869d59b708SYixun Lan			compatible = "arm,cortex-a53", "arm,armv8";
879d59b708SYixun Lan			reg = <0x0 0x1>;
889d59b708SYixun Lan			enable-method = "psci";
899d59b708SYixun Lan			next-level-cache = <&l2>;
909d59b708SYixun Lan		};
919d59b708SYixun Lan
929d59b708SYixun Lan		cpu2: cpu@2 {
939d59b708SYixun Lan			device_type = "cpu";
949d59b708SYixun Lan			compatible = "arm,cortex-a53", "arm,armv8";
959d59b708SYixun Lan			reg = <0x0 0x2>;
969d59b708SYixun Lan			enable-method = "psci";
979d59b708SYixun Lan			next-level-cache = <&l2>;
989d59b708SYixun Lan		};
999d59b708SYixun Lan
1009d59b708SYixun Lan		cpu3: cpu@3 {
1019d59b708SYixun Lan			device_type = "cpu";
1029d59b708SYixun Lan			compatible = "arm,cortex-a53", "arm,armv8";
1039d59b708SYixun Lan			reg = <0x0 0x3>;
1049d59b708SYixun Lan			enable-method = "psci";
1059d59b708SYixun Lan			next-level-cache = <&l2>;
1069d59b708SYixun Lan		};
1079d59b708SYixun Lan
1089d59b708SYixun Lan		l2: l2-cache0 {
1099d59b708SYixun Lan			compatible = "cache";
1109d59b708SYixun Lan		};
1119d59b708SYixun Lan	};
1129d59b708SYixun Lan
1139d59b708SYixun Lan	psci {
1149d59b708SYixun Lan		compatible = "arm,psci-1.0";
1159d59b708SYixun Lan		method = "smc";
1169d59b708SYixun Lan	};
1179d59b708SYixun Lan
1188c0cf40fSJerome Brunet	reserved-memory {
1198c0cf40fSJerome Brunet		#address-cells = <2>;
1208c0cf40fSJerome Brunet		#size-cells = <2>;
1218c0cf40fSJerome Brunet		ranges;
1228c0cf40fSJerome Brunet
1238c0cf40fSJerome Brunet		/* 16 MiB reserved for Hardware ROM Firmware */
1248c0cf40fSJerome Brunet		hwrom_reserved: hwrom@0 {
1258c0cf40fSJerome Brunet			reg = <0x0 0x0 0x0 0x1000000>;
1268c0cf40fSJerome Brunet			no-map;
12708307aabSJerome Brunet		};
12808307aabSJerome Brunet
1298c0cf40fSJerome Brunet		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
1308c0cf40fSJerome Brunet		secmon_reserved: secmon@5000000 {
1318c0cf40fSJerome Brunet			reg = <0x0 0x05000000 0x0 0x300000>;
1328c0cf40fSJerome Brunet			no-map;
13308307aabSJerome Brunet		};
1345e395e14SYixun Lan	};
1355e395e14SYixun Lan
1369d59b708SYixun Lan	soc {
1379d59b708SYixun Lan		compatible = "simple-bus";
1389d59b708SYixun Lan		#address-cells = <2>;
1399d59b708SYixun Lan		#size-cells = <2>;
1409d59b708SYixun Lan		ranges;
1419d59b708SYixun Lan
1428c0cf40fSJerome Brunet		ethmac: ethernet@ff3f0000 {
143eaf8f57cSNeil Armstrong			compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
1448c0cf40fSJerome Brunet			reg = <0x0 0xff3f0000 0x0 0x10000
1458c0cf40fSJerome Brunet			       0x0 0xff634540 0x0 0x8>;
1468c0cf40fSJerome Brunet			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
1478c0cf40fSJerome Brunet			interrupt-names = "macirq";
1488c0cf40fSJerome Brunet			clocks = <&clkc CLKID_ETH>,
1498c0cf40fSJerome Brunet				 <&clkc CLKID_FCLK_DIV2>,
1508c0cf40fSJerome Brunet				 <&clkc CLKID_MPLL2>;
1518c0cf40fSJerome Brunet			clock-names = "stmmaceth", "clkin0", "clkin1";
1528c0cf40fSJerome Brunet			status = "disabled";
1538c0cf40fSJerome Brunet		};
1548c0cf40fSJerome Brunet
155c362e4e0SJerome Brunet		pdm: audio-controller@ff632000 {
156c362e4e0SJerome Brunet			compatible = "amlogic,axg-pdm";
157c362e4e0SJerome Brunet			reg = <0x0 0xff632000 0x0 0x34>;
158c362e4e0SJerome Brunet			#sound-dai-cells = <0>;
159c362e4e0SJerome Brunet			sound-name-prefix = "PDM";
160c362e4e0SJerome Brunet			clocks = <&clkc_audio AUD_CLKID_PDM>,
161c362e4e0SJerome Brunet				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
162c362e4e0SJerome Brunet				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
163c362e4e0SJerome Brunet			clock-names = "pclk", "dclk", "sysclk";
164c362e4e0SJerome Brunet			status = "disabled";
165c362e4e0SJerome Brunet		};
166c362e4e0SJerome Brunet
1678c0cf40fSJerome Brunet		periphs: bus@ff634000 {
168221cf34bSNan Li			compatible = "simple-bus";
1698c0cf40fSJerome Brunet			reg = <0x0 0xff634000 0x0 0x2000>;
170221cf34bSNan Li			#address-cells = <2>;
171221cf34bSNan Li			#size-cells = <2>;
1728c0cf40fSJerome Brunet			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
173221cf34bSNan Li
1748c0cf40fSJerome Brunet			hwrng: rng@18 {
1758c0cf40fSJerome Brunet				compatible = "amlogic,meson-rng";
1768c0cf40fSJerome Brunet				reg = <0x0 0x18 0x0 0x4>;
1778c0cf40fSJerome Brunet				clocks = <&clkc CLKID_RNG0>;
1788c0cf40fSJerome Brunet				clock-names = "core";
179221cf34bSNan Li			};
180221cf34bSNan Li
1818c0cf40fSJerome Brunet			pinctrl_periphs: pinctrl@480 {
1828c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-periphs-pinctrl";
1838c0cf40fSJerome Brunet				#address-cells = <2>;
1848c0cf40fSJerome Brunet				#size-cells = <2>;
1858c0cf40fSJerome Brunet				ranges;
1868c0cf40fSJerome Brunet
1878c0cf40fSJerome Brunet				gpio: bank@480 {
1888c0cf40fSJerome Brunet					reg = <0x0 0x00480 0x0 0x40>,
1898c0cf40fSJerome Brunet					      <0x0 0x004e8 0x0 0x14>,
1908c0cf40fSJerome Brunet					      <0x0 0x00520 0x0 0x14>,
1918c0cf40fSJerome Brunet					      <0x0 0x00430 0x0 0x3c>;
1928c0cf40fSJerome Brunet					reg-names = "mux", "pull", "pull-enable", "gpio";
1938c0cf40fSJerome Brunet					gpio-controller;
1948c0cf40fSJerome Brunet					#gpio-cells = <2>;
1958c0cf40fSJerome Brunet					gpio-ranges = <&pinctrl_periphs 0 0 86>;
196221cf34bSNan Li				};
1978c0cf40fSJerome Brunet
1988c0cf40fSJerome Brunet				i2c0_pins: i2c0 {
1998c0cf40fSJerome Brunet					mux {
2008c0cf40fSJerome Brunet						groups = "i2c0_sck",
2018c0cf40fSJerome Brunet							 "i2c0_sda";
2028c0cf40fSJerome Brunet						function = "i2c0";
2038c0cf40fSJerome Brunet					};
2048c0cf40fSJerome Brunet				};
2058c0cf40fSJerome Brunet
2068c0cf40fSJerome Brunet				i2c1_x_pins: i2c1_x {
2078c0cf40fSJerome Brunet					mux {
2088c0cf40fSJerome Brunet						groups = "i2c1_sck_x",
2098c0cf40fSJerome Brunet							 "i2c1_sda_x";
2108c0cf40fSJerome Brunet						function = "i2c1";
2118c0cf40fSJerome Brunet					};
2128c0cf40fSJerome Brunet				};
2138c0cf40fSJerome Brunet
2148c0cf40fSJerome Brunet				i2c1_z_pins: i2c1_z {
2158c0cf40fSJerome Brunet					mux {
2168c0cf40fSJerome Brunet						groups = "i2c1_sck_z",
2178c0cf40fSJerome Brunet							 "i2c1_sda_z";
2188c0cf40fSJerome Brunet						function = "i2c1";
2198c0cf40fSJerome Brunet					};
2208c0cf40fSJerome Brunet				};
2218c0cf40fSJerome Brunet
2228c0cf40fSJerome Brunet				i2c2_a_pins: i2c2_a {
2238c0cf40fSJerome Brunet					mux {
2248c0cf40fSJerome Brunet						groups = "i2c2_sck_a",
2258c0cf40fSJerome Brunet							 "i2c2_sda_a";
2268c0cf40fSJerome Brunet						function = "i2c2";
2278c0cf40fSJerome Brunet					};
2288c0cf40fSJerome Brunet				};
2298c0cf40fSJerome Brunet
2308c0cf40fSJerome Brunet				i2c2_x_pins: i2c2_x {
2318c0cf40fSJerome Brunet					mux {
2328c0cf40fSJerome Brunet						groups = "i2c2_sck_x",
2338c0cf40fSJerome Brunet							 "i2c2_sda_x";
2348c0cf40fSJerome Brunet						function = "i2c2";
2358c0cf40fSJerome Brunet					};
2368c0cf40fSJerome Brunet				};
2378c0cf40fSJerome Brunet
2388c0cf40fSJerome Brunet				i2c3_a6_pins: i2c3_a6 {
2398c0cf40fSJerome Brunet					mux {
2408c0cf40fSJerome Brunet						groups = "i2c3_sda_a6",
2418c0cf40fSJerome Brunet							 "i2c3_sck_a7";
2428c0cf40fSJerome Brunet						function = "i2c3";
2438c0cf40fSJerome Brunet					};
2448c0cf40fSJerome Brunet				};
2458c0cf40fSJerome Brunet
2468c0cf40fSJerome Brunet				i2c3_a12_pins: i2c3_a12 {
2478c0cf40fSJerome Brunet					mux {
2488c0cf40fSJerome Brunet						groups = "i2c3_sda_a12",
2498c0cf40fSJerome Brunet							 "i2c3_sck_a13";
2508c0cf40fSJerome Brunet						function = "i2c3";
2518c0cf40fSJerome Brunet					};
2528c0cf40fSJerome Brunet				};
2538c0cf40fSJerome Brunet
2548c0cf40fSJerome Brunet				i2c3_a19_pins: i2c3_a19 {
2558c0cf40fSJerome Brunet					mux {
2568c0cf40fSJerome Brunet						groups = "i2c3_sda_a19",
2578c0cf40fSJerome Brunet							 "i2c3_sck_a20";
2588c0cf40fSJerome Brunet						function = "i2c3";
2598c0cf40fSJerome Brunet					};
2608c0cf40fSJerome Brunet				};
2618c0cf40fSJerome Brunet
2628c0cf40fSJerome Brunet				emmc_pins: emmc {
2638c0cf40fSJerome Brunet					mux {
2648c0cf40fSJerome Brunet						groups = "emmc_nand_d0",
2658c0cf40fSJerome Brunet							 "emmc_nand_d1",
2668c0cf40fSJerome Brunet							 "emmc_nand_d2",
2678c0cf40fSJerome Brunet							 "emmc_nand_d3",
2688c0cf40fSJerome Brunet							 "emmc_nand_d4",
2698c0cf40fSJerome Brunet							 "emmc_nand_d5",
2708c0cf40fSJerome Brunet							 "emmc_nand_d6",
2718c0cf40fSJerome Brunet							 "emmc_nand_d7",
2728c0cf40fSJerome Brunet							 "emmc_clk",
2738c0cf40fSJerome Brunet							 "emmc_cmd",
2748c0cf40fSJerome Brunet							 "emmc_ds";
2758c0cf40fSJerome Brunet						function = "emmc";
2768c0cf40fSJerome Brunet					};
2778c0cf40fSJerome Brunet				};
2788c0cf40fSJerome Brunet
2798c0cf40fSJerome Brunet				emmc_clk_gate_pins: emmc_clk_gate {
2808c0cf40fSJerome Brunet					mux {
2818c0cf40fSJerome Brunet						groups = "BOOT_8";
2828c0cf40fSJerome Brunet						function = "gpio_periphs";
2838c0cf40fSJerome Brunet					};
2848c0cf40fSJerome Brunet					cfg-pull-down {
2858c0cf40fSJerome Brunet						pins = "BOOT_8";
2868c0cf40fSJerome Brunet						bias-pull-down;
2878c0cf40fSJerome Brunet					};
2888c0cf40fSJerome Brunet				};
2898c0cf40fSJerome Brunet
2908c0cf40fSJerome Brunet				eth_rgmii_x_pins: eth-x-rgmii {
2918c0cf40fSJerome Brunet					mux {
2928c0cf40fSJerome Brunet						groups = "eth_mdio_x",
2938c0cf40fSJerome Brunet							 "eth_mdc_x",
2948c0cf40fSJerome Brunet							 "eth_rgmii_rx_clk_x",
2958c0cf40fSJerome Brunet							 "eth_rx_dv_x",
2968c0cf40fSJerome Brunet							 "eth_rxd0_x",
2978c0cf40fSJerome Brunet							 "eth_rxd1_x",
2988c0cf40fSJerome Brunet							 "eth_rxd2_rgmii",
2998c0cf40fSJerome Brunet							 "eth_rxd3_rgmii",
3008c0cf40fSJerome Brunet							 "eth_rgmii_tx_clk",
3018c0cf40fSJerome Brunet							 "eth_txen_x",
3028c0cf40fSJerome Brunet							 "eth_txd0_x",
3038c0cf40fSJerome Brunet							 "eth_txd1_x",
3048c0cf40fSJerome Brunet							 "eth_txd2_rgmii",
3058c0cf40fSJerome Brunet							 "eth_txd3_rgmii";
3068c0cf40fSJerome Brunet						function = "eth";
3078c0cf40fSJerome Brunet					};
3088c0cf40fSJerome Brunet				};
3098c0cf40fSJerome Brunet
3108c0cf40fSJerome Brunet				eth_rgmii_y_pins: eth-y-rgmii {
3118c0cf40fSJerome Brunet					mux {
3128c0cf40fSJerome Brunet						groups = "eth_mdio_y",
3138c0cf40fSJerome Brunet							 "eth_mdc_y",
3148c0cf40fSJerome Brunet							 "eth_rgmii_rx_clk_y",
3158c0cf40fSJerome Brunet							 "eth_rx_dv_y",
3168c0cf40fSJerome Brunet							 "eth_rxd0_y",
3178c0cf40fSJerome Brunet							 "eth_rxd1_y",
3188c0cf40fSJerome Brunet							 "eth_rxd2_rgmii",
3198c0cf40fSJerome Brunet							 "eth_rxd3_rgmii",
3208c0cf40fSJerome Brunet							 "eth_rgmii_tx_clk",
3218c0cf40fSJerome Brunet							 "eth_txen_y",
3228c0cf40fSJerome Brunet							 "eth_txd0_y",
3238c0cf40fSJerome Brunet							 "eth_txd1_y",
3248c0cf40fSJerome Brunet							 "eth_txd2_rgmii",
3258c0cf40fSJerome Brunet							 "eth_txd3_rgmii";
3268c0cf40fSJerome Brunet						function = "eth";
3278c0cf40fSJerome Brunet					};
3288c0cf40fSJerome Brunet				};
3298c0cf40fSJerome Brunet
3308c0cf40fSJerome Brunet				eth_rmii_x_pins: eth-x-rmii {
3318c0cf40fSJerome Brunet					mux {
3328c0cf40fSJerome Brunet						groups = "eth_mdio_x",
3338c0cf40fSJerome Brunet							 "eth_mdc_x",
3348c0cf40fSJerome Brunet							 "eth_rgmii_rx_clk_x",
3358c0cf40fSJerome Brunet							 "eth_rx_dv_x",
3368c0cf40fSJerome Brunet							 "eth_rxd0_x",
3378c0cf40fSJerome Brunet							 "eth_rxd1_x",
3388c0cf40fSJerome Brunet							 "eth_txen_x",
3398c0cf40fSJerome Brunet							 "eth_txd0_x",
3408c0cf40fSJerome Brunet							 "eth_txd1_x";
3418c0cf40fSJerome Brunet						function = "eth";
3428c0cf40fSJerome Brunet					};
3438c0cf40fSJerome Brunet				};
3448c0cf40fSJerome Brunet
3458c0cf40fSJerome Brunet				eth_rmii_y_pins: eth-y-rmii {
3468c0cf40fSJerome Brunet					mux {
3478c0cf40fSJerome Brunet						groups = "eth_mdio_y",
3488c0cf40fSJerome Brunet							 "eth_mdc_y",
3498c0cf40fSJerome Brunet							 "eth_rgmii_rx_clk_y",
3508c0cf40fSJerome Brunet							 "eth_rx_dv_y",
3518c0cf40fSJerome Brunet							 "eth_rxd0_y",
3528c0cf40fSJerome Brunet							 "eth_rxd1_y",
3538c0cf40fSJerome Brunet							 "eth_txen_y",
3548c0cf40fSJerome Brunet							 "eth_txd0_y",
3558c0cf40fSJerome Brunet							 "eth_txd1_y";
3568c0cf40fSJerome Brunet						function = "eth";
3578c0cf40fSJerome Brunet					};
3588c0cf40fSJerome Brunet				};
3598c0cf40fSJerome Brunet
3608c0cf40fSJerome Brunet				mclk_b_pins: mclk_b {
3618c0cf40fSJerome Brunet					mux {
3628c0cf40fSJerome Brunet						groups = "mclk_b";
3638c0cf40fSJerome Brunet						function = "mclk_b";
3648c0cf40fSJerome Brunet					};
3658c0cf40fSJerome Brunet				};
3668c0cf40fSJerome Brunet
3678c0cf40fSJerome Brunet				mclk_c_pins: mclk_c {
3688c0cf40fSJerome Brunet					mux {
3698c0cf40fSJerome Brunet						groups = "mclk_c";
3708c0cf40fSJerome Brunet						function = "mclk_c";
3718c0cf40fSJerome Brunet					};
3728c0cf40fSJerome Brunet				};
3738c0cf40fSJerome Brunet
3748c0cf40fSJerome Brunet				pdm_dclk_a14_pins: pdm_dclk_a14 {
3758c0cf40fSJerome Brunet					mux {
3768c0cf40fSJerome Brunet						groups = "pdm_dclk_a14";
3778c0cf40fSJerome Brunet						function = "pdm";
3788c0cf40fSJerome Brunet					};
3798c0cf40fSJerome Brunet				};
3808c0cf40fSJerome Brunet
3818c0cf40fSJerome Brunet				pdm_dclk_a19_pins: pdm_dclk_a19 {
3828c0cf40fSJerome Brunet					mux {
3838c0cf40fSJerome Brunet						groups = "pdm_dclk_a19";
3848c0cf40fSJerome Brunet						function = "pdm";
3858c0cf40fSJerome Brunet					};
3868c0cf40fSJerome Brunet				};
3878c0cf40fSJerome Brunet
3888c0cf40fSJerome Brunet				pdm_din0_pins: pdm_din0 {
3898c0cf40fSJerome Brunet					mux {
3908c0cf40fSJerome Brunet						groups = "pdm_din0";
3918c0cf40fSJerome Brunet						function = "pdm";
3928c0cf40fSJerome Brunet					};
3938c0cf40fSJerome Brunet				};
3948c0cf40fSJerome Brunet
3958c0cf40fSJerome Brunet				pdm_din1_pins: pdm_din1 {
3968c0cf40fSJerome Brunet					mux {
3978c0cf40fSJerome Brunet						groups = "pdm_din1";
3988c0cf40fSJerome Brunet						function = "pdm";
3998c0cf40fSJerome Brunet					};
4008c0cf40fSJerome Brunet				};
4018c0cf40fSJerome Brunet
4028c0cf40fSJerome Brunet				pdm_din2_pins: pdm_din2 {
4038c0cf40fSJerome Brunet					mux {
4048c0cf40fSJerome Brunet						groups = "pdm_din2";
4058c0cf40fSJerome Brunet						function = "pdm";
4068c0cf40fSJerome Brunet					};
4078c0cf40fSJerome Brunet				};
4088c0cf40fSJerome Brunet
4098c0cf40fSJerome Brunet				pdm_din3_pins: pdm_din3 {
4108c0cf40fSJerome Brunet					mux {
4118c0cf40fSJerome Brunet						groups = "pdm_din3";
4128c0cf40fSJerome Brunet						function = "pdm";
4138c0cf40fSJerome Brunet					};
4148c0cf40fSJerome Brunet				};
4158c0cf40fSJerome Brunet
4168c0cf40fSJerome Brunet				pwm_a_a_pins: pwm_a_a {
4178c0cf40fSJerome Brunet					mux {
4188c0cf40fSJerome Brunet						groups = "pwm_a_a";
4198c0cf40fSJerome Brunet						function = "pwm_a";
4208c0cf40fSJerome Brunet					};
4218c0cf40fSJerome Brunet				};
4228c0cf40fSJerome Brunet
4238c0cf40fSJerome Brunet				pwm_a_x18_pins: pwm_a_x18 {
4248c0cf40fSJerome Brunet					mux {
4258c0cf40fSJerome Brunet						groups = "pwm_a_x18";
4268c0cf40fSJerome Brunet						function = "pwm_a";
4278c0cf40fSJerome Brunet					};
4288c0cf40fSJerome Brunet				};
4298c0cf40fSJerome Brunet
4308c0cf40fSJerome Brunet				pwm_a_x20_pins: pwm_a_x20 {
4318c0cf40fSJerome Brunet					mux {
4328c0cf40fSJerome Brunet						groups = "pwm_a_x20";
4338c0cf40fSJerome Brunet						function = "pwm_a";
4348c0cf40fSJerome Brunet					};
4358c0cf40fSJerome Brunet				};
4368c0cf40fSJerome Brunet
4378c0cf40fSJerome Brunet				pwm_a_z_pins: pwm_a_z {
4388c0cf40fSJerome Brunet					mux {
4398c0cf40fSJerome Brunet						groups = "pwm_a_z";
4408c0cf40fSJerome Brunet						function = "pwm_a";
4418c0cf40fSJerome Brunet					};
4428c0cf40fSJerome Brunet				};
4438c0cf40fSJerome Brunet
4448c0cf40fSJerome Brunet				pwm_b_a_pins: pwm_b_a {
4458c0cf40fSJerome Brunet					mux {
4468c0cf40fSJerome Brunet						groups = "pwm_b_a";
4478c0cf40fSJerome Brunet						function = "pwm_b";
4488c0cf40fSJerome Brunet					};
4498c0cf40fSJerome Brunet				};
4508c0cf40fSJerome Brunet
4518c0cf40fSJerome Brunet				pwm_b_x_pins: pwm_b_x {
4528c0cf40fSJerome Brunet					mux {
4538c0cf40fSJerome Brunet						groups = "pwm_b_x";
4548c0cf40fSJerome Brunet						function = "pwm_b";
4558c0cf40fSJerome Brunet					};
4568c0cf40fSJerome Brunet				};
4578c0cf40fSJerome Brunet
4588c0cf40fSJerome Brunet				pwm_b_z_pins: pwm_b_z {
4598c0cf40fSJerome Brunet					mux {
4608c0cf40fSJerome Brunet						groups = "pwm_b_z";
4618c0cf40fSJerome Brunet						function = "pwm_b";
4628c0cf40fSJerome Brunet					};
4638c0cf40fSJerome Brunet				};
4648c0cf40fSJerome Brunet
4658c0cf40fSJerome Brunet				pwm_c_a_pins: pwm_c_a {
4668c0cf40fSJerome Brunet					mux {
4678c0cf40fSJerome Brunet						groups = "pwm_c_a";
4688c0cf40fSJerome Brunet						function = "pwm_c";
4698c0cf40fSJerome Brunet					};
4708c0cf40fSJerome Brunet				};
4718c0cf40fSJerome Brunet
4728c0cf40fSJerome Brunet				pwm_c_x10_pins: pwm_c_x10 {
4738c0cf40fSJerome Brunet					mux {
4748c0cf40fSJerome Brunet						groups = "pwm_c_x10";
4758c0cf40fSJerome Brunet						function = "pwm_c";
4768c0cf40fSJerome Brunet					};
4778c0cf40fSJerome Brunet				};
4788c0cf40fSJerome Brunet
4798c0cf40fSJerome Brunet				pwm_c_x17_pins: pwm_c_x17 {
4808c0cf40fSJerome Brunet					mux {
4818c0cf40fSJerome Brunet						groups = "pwm_c_x17";
4828c0cf40fSJerome Brunet						function = "pwm_c";
4838c0cf40fSJerome Brunet					};
4848c0cf40fSJerome Brunet				};
4858c0cf40fSJerome Brunet
4868c0cf40fSJerome Brunet				pwm_d_x11_pins: pwm_d_x11 {
4878c0cf40fSJerome Brunet					mux {
4888c0cf40fSJerome Brunet						groups = "pwm_d_x11";
4898c0cf40fSJerome Brunet						function = "pwm_d";
4908c0cf40fSJerome Brunet					};
4918c0cf40fSJerome Brunet				};
4928c0cf40fSJerome Brunet
4938c0cf40fSJerome Brunet				pwm_d_x16_pins: pwm_d_x16 {
4948c0cf40fSJerome Brunet					mux {
4958c0cf40fSJerome Brunet						groups = "pwm_d_x16";
4968c0cf40fSJerome Brunet						function = "pwm_d";
4978c0cf40fSJerome Brunet					};
4988c0cf40fSJerome Brunet				};
4998c0cf40fSJerome Brunet
5008c0cf40fSJerome Brunet				sdio_pins: sdio {
5018c0cf40fSJerome Brunet					mux {
5028c0cf40fSJerome Brunet						groups = "sdio_d0",
5038c0cf40fSJerome Brunet							 "sdio_d1",
5048c0cf40fSJerome Brunet							 "sdio_d2",
5058c0cf40fSJerome Brunet							 "sdio_d3",
5068c0cf40fSJerome Brunet							 "sdio_cmd",
5078c0cf40fSJerome Brunet							 "sdio_clk";
5088c0cf40fSJerome Brunet						function = "sdio";
5098c0cf40fSJerome Brunet					};
5108c0cf40fSJerome Brunet				};
5118c0cf40fSJerome Brunet
5128c0cf40fSJerome Brunet				sdio_clk_gate_pins: sdio_clk_gate {
5138c0cf40fSJerome Brunet					mux {
5148c0cf40fSJerome Brunet						groups = "GPIOX_4";
5158c0cf40fSJerome Brunet						function = "gpio_periphs";
5168c0cf40fSJerome Brunet					};
5178c0cf40fSJerome Brunet					cfg-pull-down {
5188c0cf40fSJerome Brunet						pins = "GPIOX_4";
5198c0cf40fSJerome Brunet						bias-pull-down;
5208c0cf40fSJerome Brunet					};
5218c0cf40fSJerome Brunet				};
5228c0cf40fSJerome Brunet
5238c0cf40fSJerome Brunet				spdif_in_z_pins: spdif_in_z {
5248c0cf40fSJerome Brunet					mux {
5258c0cf40fSJerome Brunet						groups = "spdif_in_z";
5268c0cf40fSJerome Brunet						function = "spdif_in";
5278c0cf40fSJerome Brunet					};
5288c0cf40fSJerome Brunet				};
5298c0cf40fSJerome Brunet
5308c0cf40fSJerome Brunet				spdif_in_a1_pins: spdif_in_a1 {
5318c0cf40fSJerome Brunet					mux {
5328c0cf40fSJerome Brunet						groups = "spdif_in_a1";
5338c0cf40fSJerome Brunet						function = "spdif_in";
5348c0cf40fSJerome Brunet					};
5358c0cf40fSJerome Brunet				};
5368c0cf40fSJerome Brunet
5378c0cf40fSJerome Brunet				spdif_in_a7_pins: spdif_in_a7 {
5388c0cf40fSJerome Brunet					mux {
5398c0cf40fSJerome Brunet						groups = "spdif_in_a7";
5408c0cf40fSJerome Brunet						function = "spdif_in";
5418c0cf40fSJerome Brunet					};
5428c0cf40fSJerome Brunet				};
5438c0cf40fSJerome Brunet
5448c0cf40fSJerome Brunet				spdif_in_a19_pins: spdif_in_a19 {
5458c0cf40fSJerome Brunet					mux {
5468c0cf40fSJerome Brunet						groups = "spdif_in_a19";
5478c0cf40fSJerome Brunet						function = "spdif_in";
5488c0cf40fSJerome Brunet					};
5498c0cf40fSJerome Brunet				};
5508c0cf40fSJerome Brunet
5518c0cf40fSJerome Brunet				spdif_in_a20_pins: spdif_in_a20 {
5528c0cf40fSJerome Brunet					mux {
5538c0cf40fSJerome Brunet						groups = "spdif_in_a20";
5548c0cf40fSJerome Brunet						function = "spdif_in";
5558c0cf40fSJerome Brunet					};
5568c0cf40fSJerome Brunet				};
5578c0cf40fSJerome Brunet
5588c0cf40fSJerome Brunet				spdif_out_a1_pins: spdif_out_a1 {
5598c0cf40fSJerome Brunet					mux {
5608c0cf40fSJerome Brunet						groups = "spdif_out_a1";
5618c0cf40fSJerome Brunet						function = "spdif_out";
5628c0cf40fSJerome Brunet					};
5638c0cf40fSJerome Brunet				};
5648c0cf40fSJerome Brunet
5658c0cf40fSJerome Brunet				spdif_out_a11_pins: spdif_out_a11 {
5668c0cf40fSJerome Brunet					mux {
5678c0cf40fSJerome Brunet						groups = "spdif_out_a11";
5688c0cf40fSJerome Brunet						function = "spdif_out";
5698c0cf40fSJerome Brunet					};
5708c0cf40fSJerome Brunet				};
5718c0cf40fSJerome Brunet
5728c0cf40fSJerome Brunet				spdif_out_a19_pins: spdif_out_a19 {
5738c0cf40fSJerome Brunet					mux {
5748c0cf40fSJerome Brunet						groups = "spdif_out_a19";
5758c0cf40fSJerome Brunet						function = "spdif_out";
5768c0cf40fSJerome Brunet					};
5778c0cf40fSJerome Brunet				};
5788c0cf40fSJerome Brunet
5798c0cf40fSJerome Brunet				spdif_out_a20_pins: spdif_out_a20 {
5808c0cf40fSJerome Brunet					mux {
5818c0cf40fSJerome Brunet						groups = "spdif_out_a20";
5828c0cf40fSJerome Brunet						function = "spdif_out";
5838c0cf40fSJerome Brunet					};
5848c0cf40fSJerome Brunet				};
5858c0cf40fSJerome Brunet
5868c0cf40fSJerome Brunet				spdif_out_z_pins: spdif_out_z {
5878c0cf40fSJerome Brunet					mux {
5888c0cf40fSJerome Brunet						groups = "spdif_out_z";
5898c0cf40fSJerome Brunet						function = "spdif_out";
5908c0cf40fSJerome Brunet					};
5918c0cf40fSJerome Brunet				};
5928c0cf40fSJerome Brunet
5938c0cf40fSJerome Brunet				spi0_pins: spi0 {
5948c0cf40fSJerome Brunet					mux {
5958c0cf40fSJerome Brunet						groups = "spi0_miso",
5968c0cf40fSJerome Brunet							 "spi0_mosi",
5978c0cf40fSJerome Brunet							 "spi0_clk";
5988c0cf40fSJerome Brunet						function = "spi0";
5998c0cf40fSJerome Brunet					};
6008c0cf40fSJerome Brunet				};
6018c0cf40fSJerome Brunet
6028c0cf40fSJerome Brunet				spi0_ss0_pins: spi0_ss0 {
6038c0cf40fSJerome Brunet					mux {
6048c0cf40fSJerome Brunet						groups = "spi0_ss0";
6058c0cf40fSJerome Brunet						function = "spi0";
6068c0cf40fSJerome Brunet					};
6078c0cf40fSJerome Brunet				};
6088c0cf40fSJerome Brunet
6098c0cf40fSJerome Brunet				spi0_ss1_pins: spi0_ss1 {
6108c0cf40fSJerome Brunet					mux {
6118c0cf40fSJerome Brunet						groups = "spi0_ss1";
6128c0cf40fSJerome Brunet						function = "spi0";
6138c0cf40fSJerome Brunet					};
6148c0cf40fSJerome Brunet				};
6158c0cf40fSJerome Brunet
6168c0cf40fSJerome Brunet				spi0_ss2_pins: spi0_ss2 {
6178c0cf40fSJerome Brunet					mux {
6188c0cf40fSJerome Brunet						groups = "spi0_ss2";
6198c0cf40fSJerome Brunet						function = "spi0";
6208c0cf40fSJerome Brunet					};
6218c0cf40fSJerome Brunet				};
6228c0cf40fSJerome Brunet
6238c0cf40fSJerome Brunet				spi1_a_pins: spi1_a {
6248c0cf40fSJerome Brunet					mux {
6258c0cf40fSJerome Brunet						groups = "spi1_miso_a",
6268c0cf40fSJerome Brunet							 "spi1_mosi_a",
6278c0cf40fSJerome Brunet							 "spi1_clk_a";
6288c0cf40fSJerome Brunet						function = "spi1";
6298c0cf40fSJerome Brunet					};
6308c0cf40fSJerome Brunet				};
6318c0cf40fSJerome Brunet
6328c0cf40fSJerome Brunet				spi1_ss0_a_pins: spi1_ss0_a {
6338c0cf40fSJerome Brunet					mux {
6348c0cf40fSJerome Brunet						groups = "spi1_ss0_a";
6358c0cf40fSJerome Brunet						function = "spi1";
6368c0cf40fSJerome Brunet					};
6378c0cf40fSJerome Brunet				};
6388c0cf40fSJerome Brunet
6398c0cf40fSJerome Brunet				spi1_ss1_pins: spi1_ss1 {
6408c0cf40fSJerome Brunet					mux {
6418c0cf40fSJerome Brunet						groups = "spi1_ss1";
6428c0cf40fSJerome Brunet						function = "spi1";
6438c0cf40fSJerome Brunet					};
6448c0cf40fSJerome Brunet				};
6458c0cf40fSJerome Brunet
6468c0cf40fSJerome Brunet				spi1_x_pins: spi1_x {
6478c0cf40fSJerome Brunet					mux {
6488c0cf40fSJerome Brunet						groups = "spi1_miso_x",
6498c0cf40fSJerome Brunet							 "spi1_mosi_x",
6508c0cf40fSJerome Brunet							 "spi1_clk_x";
6518c0cf40fSJerome Brunet						function = "spi1";
6528c0cf40fSJerome Brunet					};
6538c0cf40fSJerome Brunet				};
6548c0cf40fSJerome Brunet
6558c0cf40fSJerome Brunet				spi1_ss0_x_pins: spi1_ss0_x {
6568c0cf40fSJerome Brunet					mux {
6578c0cf40fSJerome Brunet						groups = "spi1_ss0_x";
6588c0cf40fSJerome Brunet						function = "spi1";
6598c0cf40fSJerome Brunet					};
6608c0cf40fSJerome Brunet				};
6618c0cf40fSJerome Brunet
6628c0cf40fSJerome Brunet				tdma_din0_pins: tdma_din0 {
6638c0cf40fSJerome Brunet					mux {
6648c0cf40fSJerome Brunet						groups = "tdma_din0";
6658c0cf40fSJerome Brunet						function = "tdma";
6668c0cf40fSJerome Brunet					};
6678c0cf40fSJerome Brunet				};
6688c0cf40fSJerome Brunet
6698c0cf40fSJerome Brunet				tdma_dout0_x14_pins: tdma_dout0_x14 {
6708c0cf40fSJerome Brunet					mux {
6718c0cf40fSJerome Brunet						groups = "tdma_dout0_x14";
6728c0cf40fSJerome Brunet						function = "tdma";
6738c0cf40fSJerome Brunet					};
6748c0cf40fSJerome Brunet				};
6758c0cf40fSJerome Brunet
6768c0cf40fSJerome Brunet				tdma_dout0_x15_pins: tdma_dout0_x15 {
6778c0cf40fSJerome Brunet					mux {
6788c0cf40fSJerome Brunet						groups = "tdma_dout0_x15";
6798c0cf40fSJerome Brunet						function = "tdma";
6808c0cf40fSJerome Brunet					};
6818c0cf40fSJerome Brunet				};
6828c0cf40fSJerome Brunet
6838c0cf40fSJerome Brunet				tdma_dout1_pins: tdma_dout1 {
6848c0cf40fSJerome Brunet					mux {
6858c0cf40fSJerome Brunet						groups = "tdma_dout1";
6868c0cf40fSJerome Brunet						function = "tdma";
6878c0cf40fSJerome Brunet					};
6888c0cf40fSJerome Brunet				};
6898c0cf40fSJerome Brunet
6908c0cf40fSJerome Brunet				tdma_din1_pins: tdma_din1 {
6918c0cf40fSJerome Brunet					mux {
6928c0cf40fSJerome Brunet						groups = "tdma_din1";
6938c0cf40fSJerome Brunet						function = "tdma";
6948c0cf40fSJerome Brunet					};
6958c0cf40fSJerome Brunet				};
6968c0cf40fSJerome Brunet
6978c0cf40fSJerome Brunet				tdma_fs_pins: tdma_fs {
6988c0cf40fSJerome Brunet					mux {
6998c0cf40fSJerome Brunet						groups = "tdma_fs";
7008c0cf40fSJerome Brunet						function = "tdma";
7018c0cf40fSJerome Brunet					};
7028c0cf40fSJerome Brunet				};
7038c0cf40fSJerome Brunet
7048c0cf40fSJerome Brunet				tdma_fs_slv_pins: tdma_fs_slv {
7058c0cf40fSJerome Brunet					mux {
7068c0cf40fSJerome Brunet						groups = "tdma_fs_slv";
7078c0cf40fSJerome Brunet						function = "tdma";
7088c0cf40fSJerome Brunet					};
7098c0cf40fSJerome Brunet				};
7108c0cf40fSJerome Brunet
7118c0cf40fSJerome Brunet				tdma_sclk_pins: tdma_sclk {
7128c0cf40fSJerome Brunet					mux {
7138c0cf40fSJerome Brunet						groups = "tdma_sclk";
7148c0cf40fSJerome Brunet						function = "tdma";
7158c0cf40fSJerome Brunet					};
7168c0cf40fSJerome Brunet				};
7178c0cf40fSJerome Brunet
7188c0cf40fSJerome Brunet				tdma_sclk_slv_pins: tdma_sclk_slv {
7198c0cf40fSJerome Brunet					mux {
7208c0cf40fSJerome Brunet						groups = "tdma_sclk_slv";
7218c0cf40fSJerome Brunet						function = "tdma";
7228c0cf40fSJerome Brunet					};
7238c0cf40fSJerome Brunet				};
7248c0cf40fSJerome Brunet
7258c0cf40fSJerome Brunet				tdmb_din0_pins: tdmb_din0 {
7268c0cf40fSJerome Brunet					mux {
7278c0cf40fSJerome Brunet						groups = "tdmb_din0";
7288c0cf40fSJerome Brunet						function = "tdmb";
7298c0cf40fSJerome Brunet					};
7308c0cf40fSJerome Brunet				};
7318c0cf40fSJerome Brunet
7328c0cf40fSJerome Brunet				tdmb_din1_pins: tdmb_din1 {
7338c0cf40fSJerome Brunet					mux {
7348c0cf40fSJerome Brunet						groups = "tdmb_din1";
7358c0cf40fSJerome Brunet						function = "tdmb";
7368c0cf40fSJerome Brunet					};
7378c0cf40fSJerome Brunet				};
7388c0cf40fSJerome Brunet
7398c0cf40fSJerome Brunet				tdmb_din2_pins: tdmb_din2 {
7408c0cf40fSJerome Brunet					mux {
7418c0cf40fSJerome Brunet						groups = "tdmb_din2";
7428c0cf40fSJerome Brunet						function = "tdmb";
7438c0cf40fSJerome Brunet					};
7448c0cf40fSJerome Brunet				};
7458c0cf40fSJerome Brunet
7468c0cf40fSJerome Brunet				tdmb_din3_pins: tdmb_din3 {
7478c0cf40fSJerome Brunet					mux {
7488c0cf40fSJerome Brunet						groups = "tdmb_din3";
7498c0cf40fSJerome Brunet						function = "tdmb";
7508c0cf40fSJerome Brunet					};
7518c0cf40fSJerome Brunet				};
7528c0cf40fSJerome Brunet
7538c0cf40fSJerome Brunet				tdmb_dout0_pins: tdmb_dout0 {
7548c0cf40fSJerome Brunet					mux {
7558c0cf40fSJerome Brunet						groups = "tdmb_dout0";
7568c0cf40fSJerome Brunet						function = "tdmb";
7578c0cf40fSJerome Brunet					};
7588c0cf40fSJerome Brunet				};
7598c0cf40fSJerome Brunet
7608c0cf40fSJerome Brunet				tdmb_dout1_pins: tdmb_dout1 {
7618c0cf40fSJerome Brunet					mux {
7628c0cf40fSJerome Brunet						groups = "tdmb_dout1";
7638c0cf40fSJerome Brunet						function = "tdmb";
7648c0cf40fSJerome Brunet					};
7658c0cf40fSJerome Brunet				};
7668c0cf40fSJerome Brunet
7678c0cf40fSJerome Brunet				tdmb_dout2_pins: tdmb_dout2 {
7688c0cf40fSJerome Brunet					mux {
7698c0cf40fSJerome Brunet						groups = "tdmb_dout2";
7708c0cf40fSJerome Brunet						function = "tdmb";
7718c0cf40fSJerome Brunet					};
7728c0cf40fSJerome Brunet				};
7738c0cf40fSJerome Brunet
7748c0cf40fSJerome Brunet				tdmb_dout3_pins: tdmb_dout3 {
7758c0cf40fSJerome Brunet					mux {
7768c0cf40fSJerome Brunet						groups = "tdmb_dout3";
7778c0cf40fSJerome Brunet						function = "tdmb";
7788c0cf40fSJerome Brunet					};
7798c0cf40fSJerome Brunet				};
7808c0cf40fSJerome Brunet
7818c0cf40fSJerome Brunet				tdmb_fs_pins: tdmb_fs {
7828c0cf40fSJerome Brunet					mux {
7838c0cf40fSJerome Brunet						groups = "tdmb_fs";
7848c0cf40fSJerome Brunet						function = "tdmb";
7858c0cf40fSJerome Brunet					};
7868c0cf40fSJerome Brunet				};
7878c0cf40fSJerome Brunet
7888c0cf40fSJerome Brunet				tdmb_fs_slv_pins: tdmb_fs_slv {
7898c0cf40fSJerome Brunet					mux {
7908c0cf40fSJerome Brunet						groups = "tdmb_fs_slv";
7918c0cf40fSJerome Brunet						function = "tdmb";
7928c0cf40fSJerome Brunet					};
7938c0cf40fSJerome Brunet				};
7948c0cf40fSJerome Brunet
7958c0cf40fSJerome Brunet				tdmb_sclk_pins: tdmb_sclk {
7968c0cf40fSJerome Brunet					mux {
7978c0cf40fSJerome Brunet						groups = "tdmb_sclk";
7988c0cf40fSJerome Brunet						function = "tdmb";
7998c0cf40fSJerome Brunet					};
8008c0cf40fSJerome Brunet				};
8018c0cf40fSJerome Brunet
8028c0cf40fSJerome Brunet				tdmb_sclk_slv_pins: tdmb_sclk_slv {
8038c0cf40fSJerome Brunet					mux {
8048c0cf40fSJerome Brunet						groups = "tdmb_sclk_slv";
8058c0cf40fSJerome Brunet						function = "tdmb";
8068c0cf40fSJerome Brunet					};
8078c0cf40fSJerome Brunet				};
8088c0cf40fSJerome Brunet
8098c0cf40fSJerome Brunet				tdmc_fs_pins: tdmc_fs {
8108c0cf40fSJerome Brunet					mux {
8118c0cf40fSJerome Brunet						groups = "tdmc_fs";
8128c0cf40fSJerome Brunet						function = "tdmc";
8138c0cf40fSJerome Brunet					};
8148c0cf40fSJerome Brunet				};
8158c0cf40fSJerome Brunet
8168c0cf40fSJerome Brunet				tdmc_fs_slv_pins: tdmc_fs_slv {
8178c0cf40fSJerome Brunet					mux {
8188c0cf40fSJerome Brunet						groups = "tdmc_fs_slv";
8198c0cf40fSJerome Brunet						function = "tdmc";
8208c0cf40fSJerome Brunet					};
8218c0cf40fSJerome Brunet				};
8228c0cf40fSJerome Brunet
8238c0cf40fSJerome Brunet				tdmc_sclk_pins: tdmc_sclk {
8248c0cf40fSJerome Brunet					mux {
8258c0cf40fSJerome Brunet						groups = "tdmc_sclk";
8268c0cf40fSJerome Brunet						function = "tdmc";
8278c0cf40fSJerome Brunet					};
8288c0cf40fSJerome Brunet				};
8298c0cf40fSJerome Brunet
8308c0cf40fSJerome Brunet				tdmc_sclk_slv_pins: tdmc_sclk_slv {
8318c0cf40fSJerome Brunet					mux {
8328c0cf40fSJerome Brunet						groups = "tdmc_sclk_slv";
8338c0cf40fSJerome Brunet						function = "tdmc";
8348c0cf40fSJerome Brunet					};
8358c0cf40fSJerome Brunet				};
8368c0cf40fSJerome Brunet
8378c0cf40fSJerome Brunet				tdmc_din0_pins: tdmc_din0 {
8388c0cf40fSJerome Brunet					mux {
8398c0cf40fSJerome Brunet						groups = "tdmc_din0";
8408c0cf40fSJerome Brunet						function = "tdmc";
8418c0cf40fSJerome Brunet					};
8428c0cf40fSJerome Brunet				};
8438c0cf40fSJerome Brunet
8448c0cf40fSJerome Brunet				tdmc_din1_pins: tdmc_din1 {
8458c0cf40fSJerome Brunet					mux {
8468c0cf40fSJerome Brunet						groups = "tdmc_din1";
8478c0cf40fSJerome Brunet						function = "tdmc";
8488c0cf40fSJerome Brunet					};
8498c0cf40fSJerome Brunet				};
8508c0cf40fSJerome Brunet
8518c0cf40fSJerome Brunet				tdmc_din2_pins: tdmc_din2 {
8528c0cf40fSJerome Brunet					mux {
8538c0cf40fSJerome Brunet						groups = "tdmc_din2";
8548c0cf40fSJerome Brunet						function = "tdmc";
8558c0cf40fSJerome Brunet					};
8568c0cf40fSJerome Brunet				};
8578c0cf40fSJerome Brunet
8588c0cf40fSJerome Brunet				tdmc_din3_pins: tdmc_din3 {
8598c0cf40fSJerome Brunet					mux {
8608c0cf40fSJerome Brunet						groups = "tdmc_din3";
8618c0cf40fSJerome Brunet						function = "tdmc";
8628c0cf40fSJerome Brunet					};
8638c0cf40fSJerome Brunet				};
8648c0cf40fSJerome Brunet
8658c0cf40fSJerome Brunet				tdmc_dout0_pins: tdmc_dout0 {
8668c0cf40fSJerome Brunet					mux {
8678c0cf40fSJerome Brunet						groups = "tdmc_dout0";
8688c0cf40fSJerome Brunet						function = "tdmc";
8698c0cf40fSJerome Brunet					};
8708c0cf40fSJerome Brunet				};
8718c0cf40fSJerome Brunet
8728c0cf40fSJerome Brunet				tdmc_dout1_pins: tdmc_dout1 {
8738c0cf40fSJerome Brunet					mux {
8748c0cf40fSJerome Brunet						groups = "tdmc_dout1";
8758c0cf40fSJerome Brunet						function = "tdmc";
8768c0cf40fSJerome Brunet					};
8778c0cf40fSJerome Brunet				};
8788c0cf40fSJerome Brunet
8798c0cf40fSJerome Brunet				tdmc_dout2_pins: tdmc_dout2 {
8808c0cf40fSJerome Brunet					mux {
8818c0cf40fSJerome Brunet						groups = "tdmc_dout2";
8828c0cf40fSJerome Brunet						function = "tdmc";
8838c0cf40fSJerome Brunet					};
8848c0cf40fSJerome Brunet				};
8858c0cf40fSJerome Brunet
8868c0cf40fSJerome Brunet				tdmc_dout3_pins: tdmc_dout3 {
8878c0cf40fSJerome Brunet					mux {
8888c0cf40fSJerome Brunet						groups = "tdmc_dout3";
8898c0cf40fSJerome Brunet						function = "tdmc";
8908c0cf40fSJerome Brunet					};
8918c0cf40fSJerome Brunet				};
8928c0cf40fSJerome Brunet
8938c0cf40fSJerome Brunet				uart_a_pins: uart_a {
8948c0cf40fSJerome Brunet					mux {
8958c0cf40fSJerome Brunet						groups = "uart_tx_a",
8968c0cf40fSJerome Brunet							 "uart_rx_a";
8978c0cf40fSJerome Brunet						function = "uart_a";
8988c0cf40fSJerome Brunet					};
8998c0cf40fSJerome Brunet				};
9008c0cf40fSJerome Brunet
9018c0cf40fSJerome Brunet				uart_a_cts_rts_pins: uart_a_cts_rts {
9028c0cf40fSJerome Brunet					mux {
9038c0cf40fSJerome Brunet						groups = "uart_cts_a",
9048c0cf40fSJerome Brunet							 "uart_rts_a";
9058c0cf40fSJerome Brunet						function = "uart_a";
9068c0cf40fSJerome Brunet					};
9078c0cf40fSJerome Brunet				};
9088c0cf40fSJerome Brunet
9098c0cf40fSJerome Brunet				uart_b_x_pins: uart_b_x {
9108c0cf40fSJerome Brunet					mux {
9118c0cf40fSJerome Brunet						groups = "uart_tx_b_x",
9128c0cf40fSJerome Brunet							 "uart_rx_b_x";
9138c0cf40fSJerome Brunet						function = "uart_b";
9148c0cf40fSJerome Brunet					};
9158c0cf40fSJerome Brunet				};
9168c0cf40fSJerome Brunet
9178c0cf40fSJerome Brunet				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
9188c0cf40fSJerome Brunet					mux {
9198c0cf40fSJerome Brunet						groups = "uart_cts_b_x",
9208c0cf40fSJerome Brunet							 "uart_rts_b_x";
9218c0cf40fSJerome Brunet						function = "uart_b";
9228c0cf40fSJerome Brunet					};
9238c0cf40fSJerome Brunet				};
9248c0cf40fSJerome Brunet
9258c0cf40fSJerome Brunet				uart_b_z_pins: uart_b_z {
9268c0cf40fSJerome Brunet					mux {
9278c0cf40fSJerome Brunet						groups = "uart_tx_b_z",
9288c0cf40fSJerome Brunet							 "uart_rx_b_z";
9298c0cf40fSJerome Brunet						function = "uart_b";
9308c0cf40fSJerome Brunet					};
9318c0cf40fSJerome Brunet				};
9328c0cf40fSJerome Brunet
9338c0cf40fSJerome Brunet				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
9348c0cf40fSJerome Brunet					mux {
9358c0cf40fSJerome Brunet						groups = "uart_cts_b_z",
9368c0cf40fSJerome Brunet							 "uart_rts_b_z";
9378c0cf40fSJerome Brunet						function = "uart_b";
9388c0cf40fSJerome Brunet					};
9398c0cf40fSJerome Brunet				};
9408c0cf40fSJerome Brunet
9418c0cf40fSJerome Brunet				uart_ao_b_z_pins: uart_ao_b_z {
9428c0cf40fSJerome Brunet					mux {
9438c0cf40fSJerome Brunet						groups = "uart_ao_tx_b_z",
9448c0cf40fSJerome Brunet							 "uart_ao_rx_b_z";
9458c0cf40fSJerome Brunet						function = "uart_ao_b_z";
9468c0cf40fSJerome Brunet					};
9478c0cf40fSJerome Brunet				};
9488c0cf40fSJerome Brunet
9498c0cf40fSJerome Brunet				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
9508c0cf40fSJerome Brunet					mux {
9518c0cf40fSJerome Brunet						groups = "uart_ao_cts_b_z",
9528c0cf40fSJerome Brunet							 "uart_ao_rts_b_z";
9538c0cf40fSJerome Brunet						function = "uart_ao_b_z";
9548c0cf40fSJerome Brunet					};
9558c0cf40fSJerome Brunet				};
9568c0cf40fSJerome Brunet			};
9578c0cf40fSJerome Brunet		};
9588c0cf40fSJerome Brunet
9598c0cf40fSJerome Brunet		hiubus: bus@ff63c000 {
9608c0cf40fSJerome Brunet			compatible = "simple-bus";
9618c0cf40fSJerome Brunet			reg = <0x0 0xff63c000 0x0 0x1c00>;
9628c0cf40fSJerome Brunet			#address-cells = <2>;
9638c0cf40fSJerome Brunet			#size-cells = <2>;
9648c0cf40fSJerome Brunet			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
9658c0cf40fSJerome Brunet
9668c0cf40fSJerome Brunet			sysctrl: system-controller@0 {
9678c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-hhi-sysctrl",
968445f2bdaSNeil Armstrong					     "simple-mfd", "syscon";
9698c0cf40fSJerome Brunet				reg = <0 0 0 0x400>;
9708c0cf40fSJerome Brunet
9718c0cf40fSJerome Brunet				clkc: clock-controller {
9728c0cf40fSJerome Brunet					compatible = "amlogic,axg-clkc";
9738c0cf40fSJerome Brunet					#clock-cells = <1>;
9748c0cf40fSJerome Brunet				};
9758c0cf40fSJerome Brunet			};
9768c0cf40fSJerome Brunet		};
9778c0cf40fSJerome Brunet
9788c0cf40fSJerome Brunet		mailbox: mailbox@ff63dc00 {
9798c0cf40fSJerome Brunet			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
9808c0cf40fSJerome Brunet			reg = <0 0xff63dc00 0 0x400>;
9818c0cf40fSJerome Brunet			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
9828c0cf40fSJerome Brunet				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
9838c0cf40fSJerome Brunet				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
9848c0cf40fSJerome Brunet			#mbox-cells = <1>;
985221cf34bSNan Li		};
986221cf34bSNan Li
9878909e722SJerome Brunet		audio: bus@ff642000 {
9888909e722SJerome Brunet			compatible = "simple-bus";
9898909e722SJerome Brunet			reg = <0x0 0xff642000 0x0 0x2000>;
9908909e722SJerome Brunet			#address-cells = <2>;
9918909e722SJerome Brunet			#size-cells = <2>;
9928909e722SJerome Brunet			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
9938909e722SJerome Brunet
9948909e722SJerome Brunet			clkc_audio: clock-controller@0 {
9958909e722SJerome Brunet				compatible = "amlogic,axg-audio-clkc";
9968909e722SJerome Brunet				reg = <0x0 0x0 0x0 0xb4>;
9978909e722SJerome Brunet				#clock-cells = <1>;
9988909e722SJerome Brunet
9998909e722SJerome Brunet				clocks = <&clkc CLKID_AUDIO>,
10008909e722SJerome Brunet					 <&clkc CLKID_MPLL0>,
10018909e722SJerome Brunet					 <&clkc CLKID_MPLL1>,
10028909e722SJerome Brunet					 <&clkc CLKID_MPLL2>,
10038909e722SJerome Brunet					 <&clkc CLKID_MPLL3>,
10048909e722SJerome Brunet					 <&clkc CLKID_HIFI_PLL>,
10058909e722SJerome Brunet					 <&clkc CLKID_FCLK_DIV3>,
10068909e722SJerome Brunet					 <&clkc CLKID_FCLK_DIV4>,
10078909e722SJerome Brunet					 <&clkc CLKID_GP0_PLL>;
10088909e722SJerome Brunet				clock-names = "pclk",
10098909e722SJerome Brunet					      "mst_in0",
10108909e722SJerome Brunet					      "mst_in1",
10118909e722SJerome Brunet					      "mst_in2",
10128909e722SJerome Brunet					      "mst_in3",
10138909e722SJerome Brunet					      "mst_in4",
10148909e722SJerome Brunet					      "mst_in5",
10158909e722SJerome Brunet					      "mst_in6",
10168909e722SJerome Brunet					      "mst_in7";
10178909e722SJerome Brunet
10188909e722SJerome Brunet				resets = <&reset RESET_AUDIO>;
10198909e722SJerome Brunet			};
102066d58a8fSJerome Brunet
1021f2b8f6a9SJerome Brunet			toddr_a: audio-controller@100 {
1022f2b8f6a9SJerome Brunet				compatible = "amlogic,axg-toddr";
1023f2b8f6a9SJerome Brunet				reg = <0x0 0x100 0x0 0x1c>;
1024f2b8f6a9SJerome Brunet				#sound-dai-cells = <0>;
1025f2b8f6a9SJerome Brunet				sound-name-prefix = "TODDR_A";
1026f2b8f6a9SJerome Brunet				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1027f2b8f6a9SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1028f2b8f6a9SJerome Brunet				resets = <&arb AXG_ARB_TODDR_A>;
1029f2b8f6a9SJerome Brunet				status = "disabled";
1030f2b8f6a9SJerome Brunet			};
1031f2b8f6a9SJerome Brunet
1032f2b8f6a9SJerome Brunet			toddr_b: audio-controller@140 {
1033f2b8f6a9SJerome Brunet				compatible = "amlogic,axg-toddr";
1034f2b8f6a9SJerome Brunet				reg = <0x0 0x140 0x0 0x1c>;
1035f2b8f6a9SJerome Brunet				#sound-dai-cells = <0>;
1036f2b8f6a9SJerome Brunet				sound-name-prefix = "TODDR_B";
1037f2b8f6a9SJerome Brunet				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1038f2b8f6a9SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1039f2b8f6a9SJerome Brunet				resets = <&arb AXG_ARB_TODDR_B>;
1040f2b8f6a9SJerome Brunet				status = "disabled";
1041f2b8f6a9SJerome Brunet			};
1042f2b8f6a9SJerome Brunet
1043f2b8f6a9SJerome Brunet			toddr_c: audio-controller@180 {
1044f2b8f6a9SJerome Brunet				compatible = "amlogic,axg-toddr";
1045f2b8f6a9SJerome Brunet				reg = <0x0 0x180 0x0 0x1c>;
1046f2b8f6a9SJerome Brunet				#sound-dai-cells = <0>;
1047f2b8f6a9SJerome Brunet				sound-name-prefix = "TODDR_C";
1048f2b8f6a9SJerome Brunet				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1049f2b8f6a9SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1050f2b8f6a9SJerome Brunet				resets = <&arb AXG_ARB_TODDR_C>;
1051f2b8f6a9SJerome Brunet				status = "disabled";
1052f2b8f6a9SJerome Brunet			};
1053f2b8f6a9SJerome Brunet
1054f2b8f6a9SJerome Brunet			frddr_a: audio-controller@1c0 {
1055f2b8f6a9SJerome Brunet				compatible = "amlogic,axg-frddr";
1056f2b8f6a9SJerome Brunet				reg = <0x0 0x1c0 0x0 0x1c>;
1057f2b8f6a9SJerome Brunet				#sound-dai-cells = <0>;
1058f2b8f6a9SJerome Brunet				sound-name-prefix = "FRDDR_A";
1059f2b8f6a9SJerome Brunet				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1060f2b8f6a9SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1061f2b8f6a9SJerome Brunet				resets = <&arb AXG_ARB_FRDDR_A>;
1062f2b8f6a9SJerome Brunet				status = "disabled";
1063f2b8f6a9SJerome Brunet			};
1064f2b8f6a9SJerome Brunet
1065f2b8f6a9SJerome Brunet			frddr_b: audio-controller@200 {
1066f2b8f6a9SJerome Brunet				compatible = "amlogic,axg-frddr";
1067f2b8f6a9SJerome Brunet				reg = <0x0 0x200 0x0 0x1c>;
1068f2b8f6a9SJerome Brunet				#sound-dai-cells = <0>;
1069f2b8f6a9SJerome Brunet				sound-name-prefix = "FRDDR_B";
1070f2b8f6a9SJerome Brunet				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1071f2b8f6a9SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1072f2b8f6a9SJerome Brunet				resets = <&arb AXG_ARB_FRDDR_B>;
1073f2b8f6a9SJerome Brunet				status = "disabled";
1074f2b8f6a9SJerome Brunet			};
1075f2b8f6a9SJerome Brunet
1076f2b8f6a9SJerome Brunet			frddr_c: audio-controller@240 {
1077f2b8f6a9SJerome Brunet				compatible = "amlogic,axg-frddr";
1078f2b8f6a9SJerome Brunet				reg = <0x0 0x240 0x0 0x1c>;
1079f2b8f6a9SJerome Brunet				#sound-dai-cells = <0>;
1080f2b8f6a9SJerome Brunet				sound-name-prefix = "FRDDR_C";
1081f2b8f6a9SJerome Brunet				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1082f2b8f6a9SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1083f2b8f6a9SJerome Brunet				resets = <&arb AXG_ARB_FRDDR_C>;
1084f2b8f6a9SJerome Brunet				status = "disabled";
1085f2b8f6a9SJerome Brunet			};
1086f2b8f6a9SJerome Brunet
108766d58a8fSJerome Brunet			arb: reset-controller@280 {
108866d58a8fSJerome Brunet				compatible = "amlogic,meson-axg-audio-arb";
108966d58a8fSJerome Brunet				reg = <0x0 0x280 0x0 0x4>;
109066d58a8fSJerome Brunet				#reset-cells = <1>;
109166d58a8fSJerome Brunet				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
109266d58a8fSJerome Brunet			};
1093f08c52deSJerome Brunet
1094bf8e4790SJerome Brunet			tdmin_a: audio-controller@300 {
1095bf8e4790SJerome Brunet				compatible = "amlogic,axg-tdmin";
1096bf8e4790SJerome Brunet				reg = <0x0 0x300 0x0 0x40>;
1097bf8e4790SJerome Brunet				sound-name-prefix = "TDMIN_A";
1098bf8e4790SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1099bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1100bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1101bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1102bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1103bf8e4790SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1104bf8e4790SJerome Brunet					      "lrclk", "lrclk_sel";
1105bf8e4790SJerome Brunet				status = "disabled";
1106bf8e4790SJerome Brunet			};
1107bf8e4790SJerome Brunet
1108bf8e4790SJerome Brunet			tdmin_b: audio-controller@340 {
1109bf8e4790SJerome Brunet				compatible = "amlogic,axg-tdmin";
1110bf8e4790SJerome Brunet				reg = <0x0 0x340 0x0 0x40>;
1111bf8e4790SJerome Brunet				sound-name-prefix = "TDMIN_B";
1112bf8e4790SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1113bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1114bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1115bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1116bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1117bf8e4790SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1118bf8e4790SJerome Brunet					      "lrclk", "lrclk_sel";
1119bf8e4790SJerome Brunet				status = "disabled";
1120bf8e4790SJerome Brunet			};
1121bf8e4790SJerome Brunet
1122bf8e4790SJerome Brunet			tdmin_c: audio-controller@380 {
1123bf8e4790SJerome Brunet				compatible = "amlogic,axg-tdmin";
1124bf8e4790SJerome Brunet				reg = <0x0 0x380 0x0 0x40>;
1125bf8e4790SJerome Brunet				sound-name-prefix = "TDMIN_C";
1126bf8e4790SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1127bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1128bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1129bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1130bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1131bf8e4790SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1132bf8e4790SJerome Brunet					      "lrclk", "lrclk_sel";
1133bf8e4790SJerome Brunet				status = "disabled";
1134bf8e4790SJerome Brunet			};
1135bf8e4790SJerome Brunet
1136bf8e4790SJerome Brunet			tdmin_lb: audio-controller@3c0 {
1137bf8e4790SJerome Brunet				compatible = "amlogic,axg-tdmin";
1138bf8e4790SJerome Brunet				reg = <0x0 0x3c0 0x0 0x40>;
1139bf8e4790SJerome Brunet				sound-name-prefix = "TDMIN_LB";
1140bf8e4790SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1141bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1142bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1143bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1144bf8e4790SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1145bf8e4790SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1146bf8e4790SJerome Brunet					      "lrclk", "lrclk_sel";
1147bf8e4790SJerome Brunet				status = "disabled";
1148bf8e4790SJerome Brunet			};
1149bf8e4790SJerome Brunet
1150f08c52deSJerome Brunet			spdifout: audio-controller@480 {
1151f08c52deSJerome Brunet				compatible = "amlogic,axg-spdifout";
1152f08c52deSJerome Brunet				reg = <0x0 0x480 0x0 0x50>;
1153f08c52deSJerome Brunet				#sound-dai-cells = <0>;
1154f08c52deSJerome Brunet				sound-name-prefix = "SPDIFOUT";
1155f08c52deSJerome Brunet				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1156f08c52deSJerome Brunet					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1157f08c52deSJerome Brunet				clock-names = "pclk", "mclk";
1158f08c52deSJerome Brunet				status = "disabled";
1159f08c52deSJerome Brunet			};
1160fd916739SJerome Brunet
1161fd916739SJerome Brunet			tdmout_a: audio-controller@500 {
1162fd916739SJerome Brunet				compatible = "amlogic,axg-tdmout";
1163fd916739SJerome Brunet				reg = <0x0 0x500 0x0 0x40>;
1164fd916739SJerome Brunet				sound-name-prefix = "TDMOUT_A";
1165fd916739SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1166fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1167fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1168fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1169fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1170fd916739SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1171fd916739SJerome Brunet					      "lrclk", "lrclk_sel";
1172fd916739SJerome Brunet				status = "disabled";
1173fd916739SJerome Brunet			};
1174fd916739SJerome Brunet
1175fd916739SJerome Brunet			tdmout_b: audio-controller@540 {
1176fd916739SJerome Brunet				compatible = "amlogic,axg-tdmout";
1177fd916739SJerome Brunet				reg = <0x0 0x540 0x0 0x40>;
1178fd916739SJerome Brunet				sound-name-prefix = "TDMOUT_B";
1179fd916739SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1180fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1181fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1182fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1183fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1184fd916739SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1185fd916739SJerome Brunet					      "lrclk", "lrclk_sel";
1186fd916739SJerome Brunet				status = "disabled";
1187fd916739SJerome Brunet			};
1188fd916739SJerome Brunet
1189fd916739SJerome Brunet			tdmout_c: audio-controller@580 {
1190fd916739SJerome Brunet				compatible = "amlogic,axg-tdmout";
1191fd916739SJerome Brunet				reg = <0x0 0x580 0x0 0x40>;
1192fd916739SJerome Brunet				sound-name-prefix = "TDMOUT_C";
1193fd916739SJerome Brunet				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1194fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1195fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1196fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1197fd916739SJerome Brunet					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1198fd916739SJerome Brunet				clock-names = "pclk", "sclk", "sclk_sel",
1199fd916739SJerome Brunet					      "lrclk", "lrclk_sel";
1200fd916739SJerome Brunet				status = "disabled";
1201fd916739SJerome Brunet			};
12028909e722SJerome Brunet		};
12038909e722SJerome Brunet
12040cb6c604SKevin Hilman		aobus: bus@ff800000 {
12059d59b708SYixun Lan			compatible = "simple-bus";
12069d59b708SYixun Lan			reg = <0x0 0xff800000 0x0 0x100000>;
12079d59b708SYixun Lan			#address-cells = <2>;
12089d59b708SYixun Lan			#size-cells = <2>;
12099d59b708SYixun Lan			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
12109d59b708SYixun Lan
1211e03421ecSQiufang Dai			sysctrl_AO: sys-ctrl@0 {
1212445f2bdaSNeil Armstrong				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1213e03421ecSQiufang Dai				reg =  <0x0 0x0 0x0 0x100>;
1214e03421ecSQiufang Dai
1215e03421ecSQiufang Dai				clkc_AO: clock-controller {
1216e03421ecSQiufang Dai					compatible = "amlogic,meson-axg-aoclkc";
1217e03421ecSQiufang Dai					#clock-cells = <1>;
1218e03421ecSQiufang Dai					#reset-cells = <1>;
1219e03421ecSQiufang Dai				};
1220e03421ecSQiufang Dai			};
1221e03421ecSQiufang Dai
1222de05ded6SXingyu Chen			pinctrl_aobus: pinctrl@14 {
1223de05ded6SXingyu Chen				compatible = "amlogic,meson-axg-aobus-pinctrl";
1224de05ded6SXingyu Chen				#address-cells = <2>;
1225de05ded6SXingyu Chen				#size-cells = <2>;
1226de05ded6SXingyu Chen				ranges;
1227de05ded6SXingyu Chen
1228de05ded6SXingyu Chen				gpio_ao: bank@14 {
1229de05ded6SXingyu Chen					reg = <0x0 0x00014 0x0 0x8>,
1230de05ded6SXingyu Chen					      <0x0 0x0002c 0x0 0x4>,
1231de05ded6SXingyu Chen					      <0x0 0x00024 0x0 0x8>;
1232de05ded6SXingyu Chen					reg-names = "mux", "pull", "gpio";
1233de05ded6SXingyu Chen					gpio-controller;
1234de05ded6SXingyu Chen					#gpio-cells = <2>;
1235de05ded6SXingyu Chen					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1236de05ded6SXingyu Chen				};
12377bd46a79SYixun Lan
1238c054b6c2SJerome Brunet				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1239c054b6c2SJerome Brunet					mux {
1240c054b6c2SJerome Brunet						groups = "i2c_ao_sck_4";
1241c054b6c2SJerome Brunet						function = "i2c_ao";
1242c054b6c2SJerome Brunet					};
1243c054b6c2SJerome Brunet				};
1244c054b6c2SJerome Brunet
1245c054b6c2SJerome Brunet				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1246c054b6c2SJerome Brunet					mux {
1247c054b6c2SJerome Brunet						groups = "i2c_ao_sck_8";
1248c054b6c2SJerome Brunet						function = "i2c_ao";
1249c054b6c2SJerome Brunet					};
1250c054b6c2SJerome Brunet				};
1251c054b6c2SJerome Brunet
1252c054b6c2SJerome Brunet				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1253c054b6c2SJerome Brunet					mux {
1254c054b6c2SJerome Brunet						groups = "i2c_ao_sck_10";
1255c054b6c2SJerome Brunet						function = "i2c_ao";
1256c054b6c2SJerome Brunet					};
1257c054b6c2SJerome Brunet				};
1258c054b6c2SJerome Brunet
1259c054b6c2SJerome Brunet				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1260c054b6c2SJerome Brunet					mux {
1261c054b6c2SJerome Brunet						groups = "i2c_ao_sda_5";
1262c054b6c2SJerome Brunet						function = "i2c_ao";
1263c054b6c2SJerome Brunet					};
1264c054b6c2SJerome Brunet				};
1265c054b6c2SJerome Brunet
1266c054b6c2SJerome Brunet				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1267c054b6c2SJerome Brunet					mux {
1268c054b6c2SJerome Brunet						groups = "i2c_ao_sda_9";
1269c054b6c2SJerome Brunet						function = "i2c_ao";
1270c054b6c2SJerome Brunet					};
1271c054b6c2SJerome Brunet				};
1272c054b6c2SJerome Brunet
1273c054b6c2SJerome Brunet				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1274c054b6c2SJerome Brunet					mux {
1275c054b6c2SJerome Brunet						groups = "i2c_ao_sda_11";
1276c054b6c2SJerome Brunet						function = "i2c_ao";
1277c054b6c2SJerome Brunet					};
1278c054b6c2SJerome Brunet				};
1279c054b6c2SJerome Brunet
12807bd46a79SYixun Lan				remote_input_ao_pins: remote_input_ao {
12817bd46a79SYixun Lan					mux {
12827bd46a79SYixun Lan						groups = "remote_input_ao";
12837bd46a79SYixun Lan						function = "remote_input_ao";
12847bd46a79SYixun Lan					};
12857bd46a79SYixun Lan				};
12864eae66a6SYixun Lan
12874eae66a6SYixun Lan				uart_ao_a_pins: uart_ao_a {
12884eae66a6SYixun Lan					mux {
12894eae66a6SYixun Lan						groups = "uart_ao_tx_a",
12904eae66a6SYixun Lan							 "uart_ao_rx_a";
12914eae66a6SYixun Lan						function = "uart_ao_a";
12924eae66a6SYixun Lan					};
12934eae66a6SYixun Lan				};
12944eae66a6SYixun Lan
12954eae66a6SYixun Lan				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
12964eae66a6SYixun Lan					mux {
12974eae66a6SYixun Lan						groups = "uart_ao_cts_a",
12984eae66a6SYixun Lan							 "uart_ao_rts_a";
12994eae66a6SYixun Lan						function = "uart_ao_a";
13004eae66a6SYixun Lan					};
13014eae66a6SYixun Lan				};
13024eae66a6SYixun Lan
13034eae66a6SYixun Lan				uart_ao_b_pins: uart_ao_b {
13044eae66a6SYixun Lan					mux {
13054eae66a6SYixun Lan						groups = "uart_ao_tx_b",
13064eae66a6SYixun Lan							 "uart_ao_rx_b";
13074eae66a6SYixun Lan						function = "uart_ao_b";
13084eae66a6SYixun Lan					};
13094eae66a6SYixun Lan				};
13104eae66a6SYixun Lan
13114eae66a6SYixun Lan				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
13124eae66a6SYixun Lan					mux {
13134eae66a6SYixun Lan						groups = "uart_ao_cts_b",
13144eae66a6SYixun Lan							 "uart_ao_rts_b";
13154eae66a6SYixun Lan						function = "uart_ao_b";
13164eae66a6SYixun Lan					};
13174eae66a6SYixun Lan				};
1318de05ded6SXingyu Chen			};
1319de05ded6SXingyu Chen
1320a04c18cbSJerome Brunet			sec_AO: ao-secure@140 {
1321a04c18cbSJerome Brunet				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1322a04c18cbSJerome Brunet				reg = <0x0 0x140 0x0 0x140>;
1323a04c18cbSJerome Brunet				amlogic,has-chip-id;
1324a04c18cbSJerome Brunet			};
1325a04c18cbSJerome Brunet
13264a81e5ddSJian Hu			pwm_AO_cd: pwm@2000 {
1327b4ff05caSJerome Brunet				compatible = "amlogic,meson-axg-ao-pwm";
13284a81e5ddSJian Hu				reg = <0x0 0x02000  0x0 0x20>;
13294a81e5ddSJian Hu				#pwm-cells = <3>;
13304a81e5ddSJian Hu				status = "disabled";
13314a81e5ddSJian Hu			};
13324a81e5ddSJian Hu
13339d59b708SYixun Lan			uart_AO: serial@3000 {
13349d59b708SYixun Lan				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
13359d59b708SYixun Lan				reg = <0x0 0x3000 0x0 0x18>;
13369d59b708SYixun Lan				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
13379adda353SYixun Lan				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
13389d59b708SYixun Lan				clock-names = "xtal", "pclk", "baud";
13399d59b708SYixun Lan				status = "disabled";
13409d59b708SYixun Lan			};
13419d59b708SYixun Lan
13429d59b708SYixun Lan			uart_AO_B: serial@4000 {
13439d59b708SYixun Lan				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
13449d59b708SYixun Lan				reg = <0x0 0x4000 0x0 0x18>;
13459d59b708SYixun Lan				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
13469adda353SYixun Lan				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
13479d59b708SYixun Lan				clock-names = "xtal", "pclk", "baud";
13489d59b708SYixun Lan				status = "disabled";
13499d59b708SYixun Lan			};
13507bd46a79SYixun Lan
13518c0cf40fSJerome Brunet			i2c_AO: i2c@5000 {
13528c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-i2c";
13538c0cf40fSJerome Brunet				reg = <0x0 0x05000 0x0 0x20>;
13548c0cf40fSJerome Brunet				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
13558c0cf40fSJerome Brunet				clocks = <&clkc CLKID_AO_I2C>;
13568c0cf40fSJerome Brunet				#address-cells = <1>;
13578c0cf40fSJerome Brunet				#size-cells = <0>;
13588c0cf40fSJerome Brunet				status = "disabled";
13598c0cf40fSJerome Brunet			};
13608c0cf40fSJerome Brunet
13618c0cf40fSJerome Brunet			pwm_AO_ab: pwm@7000 {
13628c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-ao-pwm";
13638c0cf40fSJerome Brunet				reg = <0x0 0x07000 0x0 0x20>;
13648c0cf40fSJerome Brunet				#pwm-cells = <3>;
13658c0cf40fSJerome Brunet				status = "disabled";
13668c0cf40fSJerome Brunet			};
13678c0cf40fSJerome Brunet
13687bd46a79SYixun Lan			ir: ir@8000 {
13697bd46a79SYixun Lan				compatible = "amlogic,meson-gxbb-ir";
13707bd46a79SYixun Lan				reg = <0x0 0x8000 0x0 0x20>;
13717bd46a79SYixun Lan				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
13727bd46a79SYixun Lan				status = "disabled";
13737bd46a79SYixun Lan			};
1374a51b74eaSXingyu Chen
1375a51b74eaSXingyu Chen			saradc: adc@9000 {
1376a51b74eaSXingyu Chen				compatible = "amlogic,meson-axg-saradc",
1377a51b74eaSXingyu Chen					"amlogic,meson-saradc";
1378a51b74eaSXingyu Chen				reg = <0x0 0x9000 0x0 0x38>;
1379a51b74eaSXingyu Chen				#io-channel-cells = <1>;
1380a51b74eaSXingyu Chen				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1381a51b74eaSXingyu Chen				clocks = <&xtal>,
1382a51b74eaSXingyu Chen					 <&clkc_AO CLKID_AO_SAR_ADC>,
1383a51b74eaSXingyu Chen					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1384a51b74eaSXingyu Chen					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1385a51b74eaSXingyu Chen				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1386a51b74eaSXingyu Chen				status = "disabled";
1387a51b74eaSXingyu Chen			};
13889d59b708SYixun Lan		};
13898c0cf40fSJerome Brunet
13908c0cf40fSJerome Brunet		gic: interrupt-controller@ffc01000 {
13918c0cf40fSJerome Brunet			compatible = "arm,gic-400";
13928c0cf40fSJerome Brunet			reg = <0x0 0xffc01000 0 0x1000>,
13938c0cf40fSJerome Brunet			      <0x0 0xffc02000 0 0x2000>,
13948c0cf40fSJerome Brunet			      <0x0 0xffc04000 0 0x2000>,
13958c0cf40fSJerome Brunet			      <0x0 0xffc06000 0 0x2000>;
13968c0cf40fSJerome Brunet			interrupt-controller;
13978c0cf40fSJerome Brunet			interrupts = <GIC_PPI 9
13988c0cf40fSJerome Brunet				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
13998c0cf40fSJerome Brunet			#interrupt-cells = <3>;
14008c0cf40fSJerome Brunet			#address-cells = <0>;
14018c0cf40fSJerome Brunet		};
14028c0cf40fSJerome Brunet
14038c0cf40fSJerome Brunet		cbus: bus@ffd00000 {
14048c0cf40fSJerome Brunet			compatible = "simple-bus";
14058c0cf40fSJerome Brunet			reg = <0x0 0xffd00000 0x0 0x25000>;
14068c0cf40fSJerome Brunet			#address-cells = <2>;
14078c0cf40fSJerome Brunet			#size-cells = <2>;
14088c0cf40fSJerome Brunet			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
14098c0cf40fSJerome Brunet
14108c0cf40fSJerome Brunet			reset: reset-controller@1004 {
14118c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-reset";
14128c0cf40fSJerome Brunet				reg = <0x0 0x01004 0x0 0x9c>;
14138c0cf40fSJerome Brunet				#reset-cells = <1>;
14148c0cf40fSJerome Brunet			};
14158c0cf40fSJerome Brunet
14168c0cf40fSJerome Brunet			gpio_intc: interrupt-controller@f080 {
14178c0cf40fSJerome Brunet				compatible = "amlogic,meson-gpio-intc";
14188c0cf40fSJerome Brunet				reg = <0x0 0xf080 0x0 0x10>;
14198c0cf40fSJerome Brunet				interrupt-controller;
14208c0cf40fSJerome Brunet				#interrupt-cells = <2>;
14218c0cf40fSJerome Brunet				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
14228c0cf40fSJerome Brunet				status = "disabled";
14238c0cf40fSJerome Brunet			};
14248c0cf40fSJerome Brunet
14258c0cf40fSJerome Brunet			pwm_ab: pwm@1b000 {
14268c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-ee-pwm";
14278c0cf40fSJerome Brunet				reg = <0x0 0x1b000 0x0 0x20>;
14288c0cf40fSJerome Brunet				#pwm-cells = <3>;
14298c0cf40fSJerome Brunet				status = "disabled";
14308c0cf40fSJerome Brunet			};
14318c0cf40fSJerome Brunet
14328c0cf40fSJerome Brunet			pwm_cd: pwm@1a000 {
14338c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-ee-pwm";
14348c0cf40fSJerome Brunet				reg = <0x0 0x1a000 0x0 0x20>;
14358c0cf40fSJerome Brunet				#pwm-cells = <3>;
14368c0cf40fSJerome Brunet				status = "disabled";
14378c0cf40fSJerome Brunet			};
14388c0cf40fSJerome Brunet
14398c0cf40fSJerome Brunet			spicc0: spi@13000 {
14408c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-spicc";
14418c0cf40fSJerome Brunet				reg = <0x0 0x13000 0x0 0x3c>;
14428c0cf40fSJerome Brunet				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
14438c0cf40fSJerome Brunet				clocks = <&clkc CLKID_SPICC0>;
14448c0cf40fSJerome Brunet				clock-names = "core";
14458c0cf40fSJerome Brunet				#address-cells = <1>;
14468c0cf40fSJerome Brunet				#size-cells = <0>;
14478c0cf40fSJerome Brunet				status = "disabled";
14488c0cf40fSJerome Brunet			};
14498c0cf40fSJerome Brunet
14508c0cf40fSJerome Brunet			spicc1: spi@15000 {
14518c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-spicc";
14528c0cf40fSJerome Brunet				reg = <0x0 0x15000 0x0 0x3c>;
14538c0cf40fSJerome Brunet				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
14548c0cf40fSJerome Brunet				clocks = <&clkc CLKID_SPICC1>;
14558c0cf40fSJerome Brunet				clock-names = "core";
14568c0cf40fSJerome Brunet				#address-cells = <1>;
14578c0cf40fSJerome Brunet				#size-cells = <0>;
14588c0cf40fSJerome Brunet				status = "disabled";
14598c0cf40fSJerome Brunet			};
14608c0cf40fSJerome Brunet
14618c0cf40fSJerome Brunet			i2c3: i2c@1c000 {
14628c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-i2c";
14638c0cf40fSJerome Brunet				reg = <0x0 0x1c000 0x0 0x20>;
14648c0cf40fSJerome Brunet				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
14658c0cf40fSJerome Brunet				clocks = <&clkc CLKID_I2C>;
14668c0cf40fSJerome Brunet				#address-cells = <1>;
14678c0cf40fSJerome Brunet				#size-cells = <0>;
14688c0cf40fSJerome Brunet				status = "disabled";
14698c0cf40fSJerome Brunet			};
14708c0cf40fSJerome Brunet
14718c0cf40fSJerome Brunet			i2c2: i2c@1d000 {
14728c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-i2c";
14738c0cf40fSJerome Brunet				reg = <0x0 0x1d000 0x0 0x20>;
14748c0cf40fSJerome Brunet				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
14758c0cf40fSJerome Brunet				clocks = <&clkc CLKID_I2C>;
14768c0cf40fSJerome Brunet				#address-cells = <1>;
14778c0cf40fSJerome Brunet				#size-cells = <0>;
14788c0cf40fSJerome Brunet				status = "disabled";
14798c0cf40fSJerome Brunet			};
14808c0cf40fSJerome Brunet
14818c0cf40fSJerome Brunet			i2c1: i2c@1e000 {
14828c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-i2c";
14838c0cf40fSJerome Brunet				reg = <0x0 0x1e000 0x0 0x20>;
14848c0cf40fSJerome Brunet				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
14858c0cf40fSJerome Brunet				clocks = <&clkc CLKID_I2C>;
14868c0cf40fSJerome Brunet				#address-cells = <1>;
14878c0cf40fSJerome Brunet				#size-cells = <0>;
14888c0cf40fSJerome Brunet				status = "disabled";
14898c0cf40fSJerome Brunet			};
14908c0cf40fSJerome Brunet
14918c0cf40fSJerome Brunet			i2c0: i2c@1f000 {
14928c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-i2c";
14938c0cf40fSJerome Brunet				reg = <0x0 0x1f000 0x0 0x20>;
14948c0cf40fSJerome Brunet				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
14958c0cf40fSJerome Brunet				clocks = <&clkc CLKID_I2C>;
14968c0cf40fSJerome Brunet				#address-cells = <1>;
14978c0cf40fSJerome Brunet				#size-cells = <0>;
14988c0cf40fSJerome Brunet				status = "disabled";
14998c0cf40fSJerome Brunet			};
15008c0cf40fSJerome Brunet
15018c0cf40fSJerome Brunet			uart_B: serial@23000 {
15028c0cf40fSJerome Brunet				compatible = "amlogic,meson-gx-uart";
15038c0cf40fSJerome Brunet				reg = <0x0 0x23000 0x0 0x18>;
15048c0cf40fSJerome Brunet				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
15058c0cf40fSJerome Brunet				status = "disabled";
15068c0cf40fSJerome Brunet				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
15078c0cf40fSJerome Brunet				clock-names = "xtal", "pclk", "baud";
15088c0cf40fSJerome Brunet			};
15098c0cf40fSJerome Brunet
15108c0cf40fSJerome Brunet			uart_A: serial@24000 {
15118c0cf40fSJerome Brunet				compatible = "amlogic,meson-gx-uart";
15128c0cf40fSJerome Brunet				reg = <0x0 0x24000 0x0 0x18>;
15138c0cf40fSJerome Brunet				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
15148c0cf40fSJerome Brunet				status = "disabled";
15158c0cf40fSJerome Brunet				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
15168c0cf40fSJerome Brunet				clock-names = "xtal", "pclk", "baud";
15178c0cf40fSJerome Brunet			};
15188c0cf40fSJerome Brunet		};
15198c0cf40fSJerome Brunet
15208c0cf40fSJerome Brunet		apb: bus@ffe00000 {
15218c0cf40fSJerome Brunet			compatible = "simple-bus";
15228c0cf40fSJerome Brunet			reg = <0x0 0xffe00000 0x0 0x200000>;
15238c0cf40fSJerome Brunet			#address-cells = <2>;
15248c0cf40fSJerome Brunet			#size-cells = <2>;
15258c0cf40fSJerome Brunet			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
15268c0cf40fSJerome Brunet
15278c0cf40fSJerome Brunet			sd_emmc_b: sd@5000 {
15288c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-mmc";
15298c0cf40fSJerome Brunet				reg = <0x0 0x5000 0x0 0x800>;
15308c0cf40fSJerome Brunet				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
15318c0cf40fSJerome Brunet				status = "disabled";
15328c0cf40fSJerome Brunet				clocks = <&clkc CLKID_SD_EMMC_B>,
15338c0cf40fSJerome Brunet					<&clkc CLKID_SD_EMMC_B_CLK0>,
15348c0cf40fSJerome Brunet					<&clkc CLKID_FCLK_DIV2>;
15358c0cf40fSJerome Brunet				clock-names = "core", "clkin0", "clkin1";
15368c0cf40fSJerome Brunet				resets = <&reset RESET_SD_EMMC_B>;
15378c0cf40fSJerome Brunet			};
15388c0cf40fSJerome Brunet
15398c0cf40fSJerome Brunet			sd_emmc_c: mmc@7000 {
15408c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-mmc";
15418c0cf40fSJerome Brunet				reg = <0x0 0x7000 0x0 0x800>;
15428c0cf40fSJerome Brunet				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
15438c0cf40fSJerome Brunet				status = "disabled";
15448c0cf40fSJerome Brunet				clocks = <&clkc CLKID_SD_EMMC_C>,
15458c0cf40fSJerome Brunet					<&clkc CLKID_SD_EMMC_C_CLK0>,
15468c0cf40fSJerome Brunet					<&clkc CLKID_FCLK_DIV2>;
15478c0cf40fSJerome Brunet				clock-names = "core", "clkin0", "clkin1";
15488c0cf40fSJerome Brunet				resets = <&reset RESET_SD_EMMC_C>;
15498c0cf40fSJerome Brunet			};
15508c0cf40fSJerome Brunet		};
15518c0cf40fSJerome Brunet
15528c0cf40fSJerome Brunet		sram: sram@fffc0000 {
15538c0cf40fSJerome Brunet			compatible = "amlogic,meson-axg-sram", "mmio-sram";
15548c0cf40fSJerome Brunet			reg = <0x0 0xfffc0000 0x0 0x20000>;
15558c0cf40fSJerome Brunet			#address-cells = <1>;
15568c0cf40fSJerome Brunet			#size-cells = <1>;
15578c0cf40fSJerome Brunet			ranges = <0 0x0 0xfffc0000 0x20000>;
15588c0cf40fSJerome Brunet
15598c0cf40fSJerome Brunet			cpu_scp_lpri: scp-shmem@0 {
15608c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-scp-shmem";
15618c0cf40fSJerome Brunet				reg = <0x13000 0x400>;
15628c0cf40fSJerome Brunet			};
15638c0cf40fSJerome Brunet
15648c0cf40fSJerome Brunet			cpu_scp_hpri: scp-shmem@200 {
15658c0cf40fSJerome Brunet				compatible = "amlogic,meson-axg-scp-shmem";
15668c0cf40fSJerome Brunet				reg = <0x13400 0x400>;
15678c0cf40fSJerome Brunet			};
15688c0cf40fSJerome Brunet		};
15698c0cf40fSJerome Brunet	};
15708c0cf40fSJerome Brunet
15718c0cf40fSJerome Brunet	timer {
15728c0cf40fSJerome Brunet		compatible = "arm,armv8-timer";
15738c0cf40fSJerome Brunet		interrupts = <GIC_PPI 13
15748c0cf40fSJerome Brunet			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
15758c0cf40fSJerome Brunet			     <GIC_PPI 14
15768c0cf40fSJerome Brunet			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
15778c0cf40fSJerome Brunet			     <GIC_PPI 11
15788c0cf40fSJerome Brunet			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
15798c0cf40fSJerome Brunet			     <GIC_PPI 10
15808c0cf40fSJerome Brunet			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
15818c0cf40fSJerome Brunet	};
15828c0cf40fSJerome Brunet
15838c0cf40fSJerome Brunet	xtal: xtal-clk {
15848c0cf40fSJerome Brunet		compatible = "fixed-clock";
15858c0cf40fSJerome Brunet		clock-frequency = <24000000>;
15868c0cf40fSJerome Brunet		clock-output-names = "xtal";
15878c0cf40fSJerome Brunet		#clock-cells = <0>;
15889d59b708SYixun Lan	};
15899d59b708SYixun Lan};
1590