1*4fef0565SLucas Tanure// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4fef0565SLucas Tanure/* 3*4fef0565SLucas Tanure * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4*4fef0565SLucas Tanure */ 5*4fef0565SLucas Tanure 6*4fef0565SLucas Tanure#include <dt-bindings/interrupt-controller/arm-gic.h> 7*4fef0565SLucas Tanure 8*4fef0565SLucas Tanure/ { 9*4fef0565SLucas Tanure interrupt-parent = <&gic>; 10*4fef0565SLucas Tanure #address-cells = <2>; 11*4fef0565SLucas Tanure #size-cells = <2>; 12*4fef0565SLucas Tanure 13*4fef0565SLucas Tanure cpus { 14*4fef0565SLucas Tanure #address-cells = <0x2>; 15*4fef0565SLucas Tanure #size-cells = <0x0>; 16*4fef0565SLucas Tanure 17*4fef0565SLucas Tanure cpu-map { 18*4fef0565SLucas Tanure cluster0 { 19*4fef0565SLucas Tanure core0 { 20*4fef0565SLucas Tanure cpu = <&cpu100>; 21*4fef0565SLucas Tanure }; 22*4fef0565SLucas Tanure core1 { 23*4fef0565SLucas Tanure cpu = <&cpu101>; 24*4fef0565SLucas Tanure }; 25*4fef0565SLucas Tanure core2 { 26*4fef0565SLucas Tanure cpu = <&cpu102>; 27*4fef0565SLucas Tanure }; 28*4fef0565SLucas Tanure core3 { 29*4fef0565SLucas Tanure cpu = <&cpu103>; 30*4fef0565SLucas Tanure }; 31*4fef0565SLucas Tanure }; 32*4fef0565SLucas Tanure 33*4fef0565SLucas Tanure cluster1 { 34*4fef0565SLucas Tanure core0 { 35*4fef0565SLucas Tanure cpu = <&cpu0>; 36*4fef0565SLucas Tanure }; 37*4fef0565SLucas Tanure core1 { 38*4fef0565SLucas Tanure cpu = <&cpu1>; 39*4fef0565SLucas Tanure }; 40*4fef0565SLucas Tanure core2 { 41*4fef0565SLucas Tanure cpu = <&cpu2>; 42*4fef0565SLucas Tanure }; 43*4fef0565SLucas Tanure core3 { 44*4fef0565SLucas Tanure cpu = <&cpu3>; 45*4fef0565SLucas Tanure }; 46*4fef0565SLucas Tanure }; 47*4fef0565SLucas Tanure }; 48*4fef0565SLucas Tanure 49*4fef0565SLucas Tanure cpu100: cpu@100 { 50*4fef0565SLucas Tanure device_type = "cpu"; 51*4fef0565SLucas Tanure compatible = "arm,cortex-a53"; 52*4fef0565SLucas Tanure reg = <0x0 0x100>; 53*4fef0565SLucas Tanure enable-method = "psci"; 54*4fef0565SLucas Tanure }; 55*4fef0565SLucas Tanure 56*4fef0565SLucas Tanure cpu101: cpu@101{ 57*4fef0565SLucas Tanure device_type = "cpu"; 58*4fef0565SLucas Tanure compatible = "arm,cortex-a53"; 59*4fef0565SLucas Tanure reg = <0x0 0x101>; 60*4fef0565SLucas Tanure enable-method = "psci"; 61*4fef0565SLucas Tanure }; 62*4fef0565SLucas Tanure 63*4fef0565SLucas Tanure cpu102: cpu@102 { 64*4fef0565SLucas Tanure device_type = "cpu"; 65*4fef0565SLucas Tanure compatible = "arm,cortex-a53"; 66*4fef0565SLucas Tanure reg = <0x0 0x102>; 67*4fef0565SLucas Tanure enable-method = "psci"; 68*4fef0565SLucas Tanure }; 69*4fef0565SLucas Tanure 70*4fef0565SLucas Tanure cpu103: cpu@103 { 71*4fef0565SLucas Tanure device_type = "cpu"; 72*4fef0565SLucas Tanure compatible = "arm,cortex-a53"; 73*4fef0565SLucas Tanure reg = <0x0 0x103>; 74*4fef0565SLucas Tanure enable-method = "psci"; 75*4fef0565SLucas Tanure }; 76*4fef0565SLucas Tanure 77*4fef0565SLucas Tanure cpu0: cpu@0 { 78*4fef0565SLucas Tanure device_type = "cpu"; 79*4fef0565SLucas Tanure compatible = "arm,cortex-a73"; 80*4fef0565SLucas Tanure reg = <0x0 0x0>; 81*4fef0565SLucas Tanure enable-method = "psci"; 82*4fef0565SLucas Tanure }; 83*4fef0565SLucas Tanure 84*4fef0565SLucas Tanure cpu1: cpu@1 { 85*4fef0565SLucas Tanure device_type = "cpu"; 86*4fef0565SLucas Tanure compatible = "arm,cortex-a73"; 87*4fef0565SLucas Tanure reg = <0x0 0x1>; 88*4fef0565SLucas Tanure enable-method = "psci"; 89*4fef0565SLucas Tanure }; 90*4fef0565SLucas Tanure 91*4fef0565SLucas Tanure cpu2: cpu@2 { 92*4fef0565SLucas Tanure device_type = "cpu"; 93*4fef0565SLucas Tanure compatible = "arm,cortex-a73"; 94*4fef0565SLucas Tanure reg = <0x0 0x2>; 95*4fef0565SLucas Tanure enable-method = "psci"; 96*4fef0565SLucas Tanure }; 97*4fef0565SLucas Tanure 98*4fef0565SLucas Tanure cpu3: cpu@3 { 99*4fef0565SLucas Tanure device_type = "cpu"; 100*4fef0565SLucas Tanure compatible = "arm,cortex-a73"; 101*4fef0565SLucas Tanure reg = <0x0 0x3>; 102*4fef0565SLucas Tanure enable-method = "psci"; 103*4fef0565SLucas Tanure }; 104*4fef0565SLucas Tanure }; 105*4fef0565SLucas Tanure 106*4fef0565SLucas Tanure timer { 107*4fef0565SLucas Tanure compatible = "arm,armv8-timer"; 108*4fef0565SLucas Tanure interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 109*4fef0565SLucas Tanure <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 110*4fef0565SLucas Tanure <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 111*4fef0565SLucas Tanure <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 112*4fef0565SLucas Tanure }; 113*4fef0565SLucas Tanure 114*4fef0565SLucas Tanure psci { 115*4fef0565SLucas Tanure compatible = "arm,psci-1.0"; 116*4fef0565SLucas Tanure method = "smc"; 117*4fef0565SLucas Tanure }; 118*4fef0565SLucas Tanure 119*4fef0565SLucas Tanure sm: secure-monitor { 120*4fef0565SLucas Tanure compatible = "amlogic,meson-gxbb-sm"; 121*4fef0565SLucas Tanure }; 122*4fef0565SLucas Tanure 123*4fef0565SLucas Tanure soc { 124*4fef0565SLucas Tanure compatible = "simple-bus"; 125*4fef0565SLucas Tanure #address-cells = <2>; 126*4fef0565SLucas Tanure #size-cells = <2>; 127*4fef0565SLucas Tanure ranges; 128*4fef0565SLucas Tanure 129*4fef0565SLucas Tanure gic: interrupt-controller@fff01000 { 130*4fef0565SLucas Tanure compatible = "arm,gic-400"; 131*4fef0565SLucas Tanure #interrupt-cells = <3>; 132*4fef0565SLucas Tanure #address-cells = <0>; 133*4fef0565SLucas Tanure interrupt-controller; 134*4fef0565SLucas Tanure reg = <0x0 0xfff01000 0 0x1000>, 135*4fef0565SLucas Tanure <0x0 0xfff02000 0 0x0100>; 136*4fef0565SLucas Tanure interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 137*4fef0565SLucas Tanure }; 138*4fef0565SLucas Tanure 139*4fef0565SLucas Tanure apb4: bus@fe000000 { 140*4fef0565SLucas Tanure compatible = "simple-bus"; 141*4fef0565SLucas Tanure reg = <0x0 0xfe000000 0x0 0x480000>; 142*4fef0565SLucas Tanure #address-cells = <2>; 143*4fef0565SLucas Tanure #size-cells = <2>; 144*4fef0565SLucas Tanure ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 145*4fef0565SLucas Tanure 146*4fef0565SLucas Tanure uart_a: serial@78000 { 147*4fef0565SLucas Tanure compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; 148*4fef0565SLucas Tanure reg = <0x0 0x78000 0x0 0x18>; 149*4fef0565SLucas Tanure interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 150*4fef0565SLucas Tanure status = "disabled"; 151*4fef0565SLucas Tanure }; 152*4fef0565SLucas Tanure }; 153*4fef0565SLucas Tanure 154*4fef0565SLucas Tanure }; 155*4fef0565SLucas Tanure}; 156