102310be6SXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
202310be6SXianwei Zhao/*
302310be6SXianwei Zhao * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
402310be6SXianwei Zhao */
502310be6SXianwei Zhao
602310be6SXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h>
702310be6SXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h>
802310be6SXianwei Zhao#include <dt-bindings/gpio/gpio.h>
902310be6SXianwei Zhao
1002310be6SXianwei Zhao/ {
1102310be6SXianwei Zhao	cpus {
1202310be6SXianwei Zhao		#address-cells = <2>;
1302310be6SXianwei Zhao		#size-cells = <0>;
1402310be6SXianwei Zhao
1502310be6SXianwei Zhao		cpu0: cpu@0 {
1602310be6SXianwei Zhao			device_type = "cpu";
1702310be6SXianwei Zhao			compatible = "arm,cortex-a35";
1802310be6SXianwei Zhao			reg = <0x0 0x0>;
1902310be6SXianwei Zhao			enable-method = "psci";
2002310be6SXianwei Zhao		};
2102310be6SXianwei Zhao
2202310be6SXianwei Zhao		cpu1: cpu@1 {
2302310be6SXianwei Zhao			device_type = "cpu";
2402310be6SXianwei Zhao			compatible = "arm,cortex-a35";
2502310be6SXianwei Zhao			reg = <0x0 0x1>;
2602310be6SXianwei Zhao			enable-method = "psci";
2702310be6SXianwei Zhao		};
2802310be6SXianwei Zhao	};
2902310be6SXianwei Zhao
3002310be6SXianwei Zhao	timer {
3102310be6SXianwei Zhao		compatible = "arm,armv8-timer";
3202310be6SXianwei Zhao		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3302310be6SXianwei Zhao			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3402310be6SXianwei Zhao			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3502310be6SXianwei Zhao			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3602310be6SXianwei Zhao	};
3702310be6SXianwei Zhao
3802310be6SXianwei Zhao	psci {
3902310be6SXianwei Zhao		compatible = "arm,psci-1.0";
4002310be6SXianwei Zhao		method = "smc";
4102310be6SXianwei Zhao	};
4202310be6SXianwei Zhao
4302310be6SXianwei Zhao	xtal: xtal-clk {
4402310be6SXianwei Zhao		compatible = "fixed-clock";
4502310be6SXianwei Zhao		clock-frequency = <24000000>;
4602310be6SXianwei Zhao		clock-output-names = "xtal";
4702310be6SXianwei Zhao		#clock-cells = <0>;
4802310be6SXianwei Zhao	};
4902310be6SXianwei Zhao
5002310be6SXianwei Zhao	soc {
5102310be6SXianwei Zhao		compatible = "simple-bus";
5202310be6SXianwei Zhao		#address-cells = <2>;
5302310be6SXianwei Zhao		#size-cells = <2>;
5402310be6SXianwei Zhao		ranges;
5502310be6SXianwei Zhao
5602310be6SXianwei Zhao		gic: interrupt-controller@fff01000 {
5702310be6SXianwei Zhao			compatible = "arm,gic-400";
5802310be6SXianwei Zhao			#interrupt-cells = <3>;
5902310be6SXianwei Zhao			#address-cells = <0>;
6002310be6SXianwei Zhao			interrupt-controller;
6102310be6SXianwei Zhao			reg = <0x0 0xfff01000 0 0x1000>,
6202310be6SXianwei Zhao			      <0x0 0xfff02000 0 0x2000>,
6302310be6SXianwei Zhao			      <0x0 0xfff04000 0 0x2000>,
6402310be6SXianwei Zhao			      <0x0 0xfff06000 0 0x2000>;
6502310be6SXianwei Zhao			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
6602310be6SXianwei Zhao		};
6702310be6SXianwei Zhao
6802310be6SXianwei Zhao		apb4: bus@fe000000 {
6902310be6SXianwei Zhao			compatible = "simple-bus";
7002310be6SXianwei Zhao			reg = <0x0 0xfe000000 0x0 0x480000>;
7102310be6SXianwei Zhao			#address-cells = <2>;
7202310be6SXianwei Zhao			#size-cells = <2>;
7302310be6SXianwei Zhao			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
7402310be6SXianwei Zhao
75*cac34b2bSHuqiang Qin			periphs_pinctrl: pinctrl@4000 {
76*cac34b2bSHuqiang Qin				compatible = "amlogic,c3-periphs-pinctrl";
77*cac34b2bSHuqiang Qin				#address-cells = <2>;
78*cac34b2bSHuqiang Qin				#size-cells = <2>;
79*cac34b2bSHuqiang Qin				ranges;
80*cac34b2bSHuqiang Qin
81*cac34b2bSHuqiang Qin				gpio: bank@4000 {
82*cac34b2bSHuqiang Qin					reg = <0x0 0x4000 0x0 0x004c>,
83*cac34b2bSHuqiang Qin					      <0x0 0x4100 0x0 0x01de>;
84*cac34b2bSHuqiang Qin					reg-names = "mux", "gpio";
85*cac34b2bSHuqiang Qin					gpio-controller;
86*cac34b2bSHuqiang Qin					#gpio-cells = <2>;
87*cac34b2bSHuqiang Qin					gpio-ranges = <&periphs_pinctrl 0 0 55>;
88*cac34b2bSHuqiang Qin				};
89*cac34b2bSHuqiang Qin			};
90*cac34b2bSHuqiang Qin
91*cac34b2bSHuqiang Qin			gpio_intc: interrupt-controller@4080 {
92*cac34b2bSHuqiang Qin				compatible = "amlogic,meson-gpio-intc",
93*cac34b2bSHuqiang Qin					     "amlogic,c3-gpio-intc";
94*cac34b2bSHuqiang Qin				reg = <0x0 0x4080 0x0 0x0020>;
95*cac34b2bSHuqiang Qin				interrupt-controller;
96*cac34b2bSHuqiang Qin				#interrupt-cells = <2>;
97*cac34b2bSHuqiang Qin				amlogic,channel-interrupts =
98*cac34b2bSHuqiang Qin					<10 11 12 13 14 15 16 17 18 19 20 21>;
99*cac34b2bSHuqiang Qin			};
100*cac34b2bSHuqiang Qin
10102310be6SXianwei Zhao			uart_b: serial@7a000 {
10202310be6SXianwei Zhao				compatible = "amlogic,meson-s4-uart",
10302310be6SXianwei Zhao					   "amlogic,meson-ao-uart";
10402310be6SXianwei Zhao				reg = <0x0 0x7a000 0x0 0x18>;
10502310be6SXianwei Zhao				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
10602310be6SXianwei Zhao				status = "disabled";
10702310be6SXianwei Zhao				clocks = <&xtal>, <&xtal>, <&xtal>;
10802310be6SXianwei Zhao				clock-names = "xtal", "pclk", "baud";
10902310be6SXianwei Zhao			};
11002310be6SXianwei Zhao
11102310be6SXianwei Zhao		};
11202310be6SXianwei Zhao	};
11302310be6SXianwei Zhao};
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