1*02310be6SXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*02310be6SXianwei Zhao/* 3*02310be6SXianwei Zhao * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4*02310be6SXianwei Zhao */ 5*02310be6SXianwei Zhao 6*02310be6SXianwei Zhao#include <dt-bindings/interrupt-controller/irq.h> 7*02310be6SXianwei Zhao#include <dt-bindings/interrupt-controller/arm-gic.h> 8*02310be6SXianwei Zhao#include <dt-bindings/gpio/gpio.h> 9*02310be6SXianwei Zhao 10*02310be6SXianwei Zhao/ { 11*02310be6SXianwei Zhao cpus { 12*02310be6SXianwei Zhao #address-cells = <2>; 13*02310be6SXianwei Zhao #size-cells = <0>; 14*02310be6SXianwei Zhao 15*02310be6SXianwei Zhao cpu0: cpu@0 { 16*02310be6SXianwei Zhao device_type = "cpu"; 17*02310be6SXianwei Zhao compatible = "arm,cortex-a35"; 18*02310be6SXianwei Zhao reg = <0x0 0x0>; 19*02310be6SXianwei Zhao enable-method = "psci"; 20*02310be6SXianwei Zhao }; 21*02310be6SXianwei Zhao 22*02310be6SXianwei Zhao cpu1: cpu@1 { 23*02310be6SXianwei Zhao device_type = "cpu"; 24*02310be6SXianwei Zhao compatible = "arm,cortex-a35"; 25*02310be6SXianwei Zhao reg = <0x0 0x1>; 26*02310be6SXianwei Zhao enable-method = "psci"; 27*02310be6SXianwei Zhao }; 28*02310be6SXianwei Zhao }; 29*02310be6SXianwei Zhao 30*02310be6SXianwei Zhao timer { 31*02310be6SXianwei Zhao compatible = "arm,armv8-timer"; 32*02310be6SXianwei Zhao interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 33*02310be6SXianwei Zhao <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 34*02310be6SXianwei Zhao <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 35*02310be6SXianwei Zhao <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 36*02310be6SXianwei Zhao }; 37*02310be6SXianwei Zhao 38*02310be6SXianwei Zhao psci { 39*02310be6SXianwei Zhao compatible = "arm,psci-1.0"; 40*02310be6SXianwei Zhao method = "smc"; 41*02310be6SXianwei Zhao }; 42*02310be6SXianwei Zhao 43*02310be6SXianwei Zhao xtal: xtal-clk { 44*02310be6SXianwei Zhao compatible = "fixed-clock"; 45*02310be6SXianwei Zhao clock-frequency = <24000000>; 46*02310be6SXianwei Zhao clock-output-names = "xtal"; 47*02310be6SXianwei Zhao #clock-cells = <0>; 48*02310be6SXianwei Zhao }; 49*02310be6SXianwei Zhao 50*02310be6SXianwei Zhao soc { 51*02310be6SXianwei Zhao compatible = "simple-bus"; 52*02310be6SXianwei Zhao #address-cells = <2>; 53*02310be6SXianwei Zhao #size-cells = <2>; 54*02310be6SXianwei Zhao ranges; 55*02310be6SXianwei Zhao 56*02310be6SXianwei Zhao gic: interrupt-controller@fff01000 { 57*02310be6SXianwei Zhao compatible = "arm,gic-400"; 58*02310be6SXianwei Zhao #interrupt-cells = <3>; 59*02310be6SXianwei Zhao #address-cells = <0>; 60*02310be6SXianwei Zhao interrupt-controller; 61*02310be6SXianwei Zhao reg = <0x0 0xfff01000 0 0x1000>, 62*02310be6SXianwei Zhao <0x0 0xfff02000 0 0x2000>, 63*02310be6SXianwei Zhao <0x0 0xfff04000 0 0x2000>, 64*02310be6SXianwei Zhao <0x0 0xfff06000 0 0x2000>; 65*02310be6SXianwei Zhao interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 66*02310be6SXianwei Zhao }; 67*02310be6SXianwei Zhao 68*02310be6SXianwei Zhao apb4: bus@fe000000 { 69*02310be6SXianwei Zhao compatible = "simple-bus"; 70*02310be6SXianwei Zhao reg = <0x0 0xfe000000 0x0 0x480000>; 71*02310be6SXianwei Zhao #address-cells = <2>; 72*02310be6SXianwei Zhao #size-cells = <2>; 73*02310be6SXianwei Zhao ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 74*02310be6SXianwei Zhao 75*02310be6SXianwei Zhao uart_b: serial@7a000 { 76*02310be6SXianwei Zhao compatible = "amlogic,meson-s4-uart", 77*02310be6SXianwei Zhao "amlogic,meson-ao-uart"; 78*02310be6SXianwei Zhao reg = <0x0 0x7a000 0x0 0x18>; 79*02310be6SXianwei Zhao interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 80*02310be6SXianwei Zhao status = "disabled"; 81*02310be6SXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 82*02310be6SXianwei Zhao clock-names = "xtal", "pclk", "baud"; 83*02310be6SXianwei Zhao }; 84*02310be6SXianwei Zhao 85*02310be6SXianwei Zhao }; 86*02310be6SXianwei Zhao }; 87*02310be6SXianwei Zhao}; 88