1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/pinctrl/sun4i-a10.h> 47 48/ { 49 interrupt-parent = <&gic>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0>; 61 enable-method = "psci"; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 device_type = "cpu"; 67 reg = <1>; 68 enable-method = "psci"; 69 }; 70 71 cpu2: cpu@2 { 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 device_type = "cpu"; 74 reg = <2>; 75 enable-method = "psci"; 76 }; 77 78 cpu3: cpu@3 { 79 compatible = "arm,cortex-a53", "arm,armv8"; 80 device_type = "cpu"; 81 reg = <3>; 82 enable-method = "psci"; 83 }; 84 }; 85 86 osc24M: osc24M_clk { 87 #clock-cells = <0>; 88 compatible = "fixed-clock"; 89 clock-frequency = <24000000>; 90 clock-output-names = "osc24M"; 91 }; 92 93 osc32k: osc32k_clk { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 clock-output-names = "osc32k"; 98 }; 99 100 psci { 101 compatible = "arm,psci-0.2"; 102 method = "smc"; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupts = <GIC_PPI 13 108 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 14 110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 111 <GIC_PPI 11 112 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 10 114 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 115 }; 116 117 soc { 118 compatible = "simple-bus"; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges; 122 123 ccu: clock@01c20000 { 124 compatible = "allwinner,sun50i-a64-ccu"; 125 reg = <0x01c20000 0x400>; 126 clocks = <&osc24M>, <&osc32k>; 127 clock-names = "hosc", "losc"; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 pio: pinctrl@1c20800 { 133 compatible = "allwinner,sun50i-a64-pinctrl"; 134 reg = <0x01c20800 0x400>; 135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&ccu 58>; 139 gpio-controller; 140 #gpio-cells = <3>; 141 interrupt-controller; 142 #interrupt-cells = <3>; 143 144 i2c1_pins: i2c1_pins { 145 pins = "PH2", "PH3"; 146 function = "i2c1"; 147 }; 148 149 uart0_pins_a: uart0@0 { 150 pins = "PB8", "PB9"; 151 function = "uart0"; 152 }; 153 }; 154 155 uart0: serial@1c28000 { 156 compatible = "snps,dw-apb-uart"; 157 reg = <0x01c28000 0x400>; 158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 159 reg-shift = <2>; 160 reg-io-width = <4>; 161 clocks = <&ccu 67>; 162 resets = <&ccu 46>; 163 status = "disabled"; 164 }; 165 166 uart1: serial@1c28400 { 167 compatible = "snps,dw-apb-uart"; 168 reg = <0x01c28400 0x400>; 169 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 170 reg-shift = <2>; 171 reg-io-width = <4>; 172 clocks = <&ccu 68>; 173 resets = <&ccu 47>; 174 status = "disabled"; 175 }; 176 177 uart2: serial@1c28800 { 178 compatible = "snps,dw-apb-uart"; 179 reg = <0x01c28800 0x400>; 180 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 clocks = <&ccu 69>; 184 resets = <&ccu 48>; 185 status = "disabled"; 186 }; 187 188 uart3: serial@1c28c00 { 189 compatible = "snps,dw-apb-uart"; 190 reg = <0x01c28c00 0x400>; 191 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 192 reg-shift = <2>; 193 reg-io-width = <4>; 194 clocks = <&ccu 70>; 195 resets = <&ccu 49>; 196 status = "disabled"; 197 }; 198 199 uart4: serial@1c29000 { 200 compatible = "snps,dw-apb-uart"; 201 reg = <0x01c29000 0x400>; 202 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 203 reg-shift = <2>; 204 reg-io-width = <4>; 205 clocks = <&ccu 71>; 206 resets = <&ccu 50>; 207 status = "disabled"; 208 }; 209 210 i2c0: i2c@1c2ac00 { 211 compatible = "allwinner,sun6i-a31-i2c"; 212 reg = <0x01c2ac00 0x400>; 213 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&ccu 63>; 215 resets = <&ccu 42>; 216 status = "disabled"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 }; 220 221 i2c1: i2c@1c2b000 { 222 compatible = "allwinner,sun6i-a31-i2c"; 223 reg = <0x01c2b000 0x400>; 224 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&ccu 64>; 226 resets = <&ccu 43>; 227 status = "disabled"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 i2c2: i2c@1c2b400 { 233 compatible = "allwinner,sun6i-a31-i2c"; 234 reg = <0x01c2b400 0x400>; 235 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&ccu 65>; 237 resets = <&ccu 44>; 238 status = "disabled"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 }; 242 243 gic: interrupt-controller@1c81000 { 244 compatible = "arm,gic-400"; 245 reg = <0x01c81000 0x1000>, 246 <0x01c82000 0x2000>, 247 <0x01c84000 0x2000>, 248 <0x01c86000 0x2000>; 249 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 250 interrupt-controller; 251 #interrupt-cells = <3>; 252 }; 253 254 rtc: rtc@1f00000 { 255 compatible = "allwinner,sun6i-a31-rtc"; 256 reg = <0x01f00000 0x54>; 257 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 259 }; 260 }; 261}; 262