1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-r-ccu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/sun50i-a64-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/reset/sun8i-r-ccu.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 chosen { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 simplefb_lcd: framebuffer-lcd { 26 compatible = "allwinner,simple-framebuffer", 27 "simple-framebuffer"; 28 allwinner,pipeline = "mixer0-lcd0"; 29 clocks = <&ccu CLK_TCON0>, 30 <&display_clocks CLK_MIXER0>; 31 status = "disabled"; 32 }; 33 34 simplefb_hdmi: framebuffer-hdmi { 35 compatible = "allwinner,simple-framebuffer", 36 "simple-framebuffer"; 37 allwinner,pipeline = "mixer1-lcd1-hdmi"; 38 clocks = <&display_clocks CLK_MIXER1>, 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40 status = "disabled"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 reg = <0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2>; 54 clocks = <&ccu 21>; 55 clock-names = "cpu"; 56 }; 57 58 cpu1: cpu@1 { 59 compatible = "arm,cortex-a53"; 60 device_type = "cpu"; 61 reg = <1>; 62 enable-method = "psci"; 63 next-level-cache = <&L2>; 64 clocks = <&ccu 21>; 65 clock-names = "cpu"; 66 }; 67 68 cpu2: cpu@2 { 69 compatible = "arm,cortex-a53"; 70 device_type = "cpu"; 71 reg = <2>; 72 enable-method = "psci"; 73 next-level-cache = <&L2>; 74 clocks = <&ccu 21>; 75 clock-names = "cpu"; 76 }; 77 78 cpu3: cpu@3 { 79 compatible = "arm,cortex-a53"; 80 device_type = "cpu"; 81 reg = <3>; 82 enable-method = "psci"; 83 next-level-cache = <&L2>; 84 clocks = <&ccu 21>; 85 clock-names = "cpu"; 86 }; 87 88 L2: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 }; 92 }; 93 94 de: display-engine { 95 compatible = "allwinner,sun50i-a64-display-engine"; 96 allwinner,pipelines = <&mixer0>, 97 <&mixer1>; 98 status = "disabled"; 99 }; 100 101 osc24M: osc24M_clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 clock-frequency = <24000000>; 105 clock-output-names = "osc24M"; 106 }; 107 108 osc32k: osc32k_clk { 109 #clock-cells = <0>; 110 compatible = "fixed-clock"; 111 clock-frequency = <32768>; 112 clock-output-names = "ext-osc32k"; 113 }; 114 115 pmu { 116 compatible = "arm,cortex-a53-pmu"; 117 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 122 }; 123 124 psci { 125 compatible = "arm,psci-0.2"; 126 method = "smc"; 127 }; 128 129 sound: sound { 130 compatible = "simple-audio-card"; 131 simple-audio-card,name = "sun50i-a64-audio"; 132 simple-audio-card,format = "i2s"; 133 simple-audio-card,frame-master = <&cpudai>; 134 simple-audio-card,bitclock-master = <&cpudai>; 135 simple-audio-card,mclk-fs = <128>; 136 simple-audio-card,aux-devs = <&codec_analog>; 137 simple-audio-card,routing = 138 "Left DAC", "AIF1 Slot 0 Left", 139 "Right DAC", "AIF1 Slot 0 Right", 140 "AIF1 Slot 0 Left ADC", "Left ADC", 141 "AIF1 Slot 0 Right ADC", "Right ADC"; 142 status = "disabled"; 143 144 cpudai: simple-audio-card,cpu { 145 sound-dai = <&dai>; 146 }; 147 148 link_codec: simple-audio-card,codec { 149 sound-dai = <&codec>; 150 }; 151 }; 152 153 sound_spdif { 154 compatible = "simple-audio-card"; 155 simple-audio-card,name = "On-board SPDIF"; 156 157 simple-audio-card,cpu { 158 sound-dai = <&spdif>; 159 }; 160 161 simple-audio-card,codec { 162 sound-dai = <&spdif_out>; 163 }; 164 }; 165 166 spdif_out: spdif-out { 167 #sound-dai-cells = <0>; 168 compatible = "linux,spdif-dit"; 169 }; 170 171 timer { 172 compatible = "arm,armv8-timer"; 173 allwinner,erratum-unknown1; 174 interrupts = <GIC_PPI 13 175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 14 177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 178 <GIC_PPI 11 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 180 <GIC_PPI 10 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 182 }; 183 184 thermal-zones { 185 cpu_thermal: cpu0-thermal { 186 /* milliseconds */ 187 polling-delay-passive = <0>; 188 polling-delay = <0>; 189 thermal-sensors = <&ths 0>; 190 }; 191 192 gpu0_thermal: gpu0-thermal { 193 /* milliseconds */ 194 polling-delay-passive = <0>; 195 polling-delay = <0>; 196 thermal-sensors = <&ths 1>; 197 }; 198 199 gpu1_thermal: gpu1-thermal { 200 /* milliseconds */ 201 polling-delay-passive = <0>; 202 polling-delay = <0>; 203 thermal-sensors = <&ths 2>; 204 }; 205 }; 206 207 soc { 208 compatible = "simple-bus"; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges; 212 213 bus@1000000 { 214 compatible = "allwinner,sun50i-a64-de2"; 215 reg = <0x1000000 0x400000>; 216 allwinner,sram = <&de2_sram 1>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 ranges = <0 0x1000000 0x400000>; 220 221 display_clocks: clock@0 { 222 compatible = "allwinner,sun50i-a64-de2-clk"; 223 reg = <0x0 0x100000>; 224 clocks = <&ccu CLK_BUS_DE>, 225 <&ccu CLK_DE>; 226 clock-names = "bus", 227 "mod"; 228 resets = <&ccu RST_BUS_DE>; 229 #clock-cells = <1>; 230 #reset-cells = <1>; 231 }; 232 233 mixer0: mixer@100000 { 234 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 235 reg = <0x100000 0x100000>; 236 clocks = <&display_clocks CLK_BUS_MIXER0>, 237 <&display_clocks CLK_MIXER0>; 238 clock-names = "bus", 239 "mod"; 240 resets = <&display_clocks RST_MIXER0>; 241 242 ports { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 mixer0_out: port@1 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 reg = <1>; 250 251 mixer0_out_tcon0: endpoint@0 { 252 reg = <0>; 253 remote-endpoint = <&tcon0_in_mixer0>; 254 }; 255 256 mixer0_out_tcon1: endpoint@1 { 257 reg = <1>; 258 remote-endpoint = <&tcon1_in_mixer0>; 259 }; 260 }; 261 }; 262 }; 263 264 mixer1: mixer@200000 { 265 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 266 reg = <0x200000 0x100000>; 267 clocks = <&display_clocks CLK_BUS_MIXER1>, 268 <&display_clocks CLK_MIXER1>; 269 clock-names = "bus", 270 "mod"; 271 resets = <&display_clocks RST_MIXER1>; 272 273 ports { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 277 mixer1_out: port@1 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <1>; 281 282 mixer1_out_tcon0: endpoint@0 { 283 reg = <0>; 284 remote-endpoint = <&tcon0_in_mixer1>; 285 }; 286 287 mixer1_out_tcon1: endpoint@1 { 288 reg = <1>; 289 remote-endpoint = <&tcon1_in_mixer1>; 290 }; 291 }; 292 }; 293 }; 294 }; 295 296 syscon: syscon@1c00000 { 297 compatible = "allwinner,sun50i-a64-system-control"; 298 reg = <0x01c00000 0x1000>; 299 #address-cells = <1>; 300 #size-cells = <1>; 301 ranges; 302 303 sram_c: sram@18000 { 304 compatible = "mmio-sram"; 305 reg = <0x00018000 0x28000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges = <0 0x00018000 0x28000>; 309 310 de2_sram: sram-section@0 { 311 compatible = "allwinner,sun50i-a64-sram-c"; 312 reg = <0x0000 0x28000>; 313 }; 314 }; 315 316 sram_c1: sram@1d00000 { 317 compatible = "mmio-sram"; 318 reg = <0x01d00000 0x40000>; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 ranges = <0 0x01d00000 0x40000>; 322 323 ve_sram: sram-section@0 { 324 compatible = "allwinner,sun50i-a64-sram-c1", 325 "allwinner,sun4i-a10-sram-c1"; 326 reg = <0x000000 0x40000>; 327 }; 328 }; 329 }; 330 331 dma: dma-controller@1c02000 { 332 compatible = "allwinner,sun50i-a64-dma"; 333 reg = <0x01c02000 0x1000>; 334 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&ccu CLK_BUS_DMA>; 336 dma-channels = <8>; 337 dma-requests = <27>; 338 resets = <&ccu RST_BUS_DMA>; 339 #dma-cells = <1>; 340 }; 341 342 tcon0: lcd-controller@1c0c000 { 343 compatible = "allwinner,sun50i-a64-tcon-lcd", 344 "allwinner,sun8i-a83t-tcon-lcd"; 345 reg = <0x01c0c000 0x1000>; 346 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 348 clock-names = "ahb", "tcon-ch0"; 349 clock-output-names = "tcon-pixel-clock"; 350 #clock-cells = <0>; 351 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 352 reset-names = "lcd", "lvds"; 353 354 ports { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 358 tcon0_in: port@0 { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 reg = <0>; 362 363 tcon0_in_mixer0: endpoint@0 { 364 reg = <0>; 365 remote-endpoint = <&mixer0_out_tcon0>; 366 }; 367 368 tcon0_in_mixer1: endpoint@1 { 369 reg = <1>; 370 remote-endpoint = <&mixer1_out_tcon0>; 371 }; 372 }; 373 374 tcon0_out: port@1 { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <1>; 378 379 tcon0_out_dsi: endpoint@1 { 380 reg = <1>; 381 remote-endpoint = <&dsi_in_tcon0>; 382 allwinner,tcon-channel = <1>; 383 }; 384 }; 385 }; 386 }; 387 388 tcon1: lcd-controller@1c0d000 { 389 compatible = "allwinner,sun50i-a64-tcon-tv", 390 "allwinner,sun8i-a83t-tcon-tv"; 391 reg = <0x01c0d000 0x1000>; 392 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 394 clock-names = "ahb", "tcon-ch1"; 395 resets = <&ccu RST_BUS_TCON1>; 396 reset-names = "lcd"; 397 398 ports { 399 #address-cells = <1>; 400 #size-cells = <0>; 401 402 tcon1_in: port@0 { 403 #address-cells = <1>; 404 #size-cells = <0>; 405 reg = <0>; 406 407 tcon1_in_mixer0: endpoint@0 { 408 reg = <0>; 409 remote-endpoint = <&mixer0_out_tcon1>; 410 }; 411 412 tcon1_in_mixer1: endpoint@1 { 413 reg = <1>; 414 remote-endpoint = <&mixer1_out_tcon1>; 415 }; 416 }; 417 418 tcon1_out: port@1 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 reg = <1>; 422 423 tcon1_out_hdmi: endpoint@1 { 424 reg = <1>; 425 remote-endpoint = <&hdmi_in_tcon1>; 426 }; 427 }; 428 }; 429 }; 430 431 video-codec@1c0e000 { 432 compatible = "allwinner,sun50i-a64-video-engine"; 433 reg = <0x01c0e000 0x1000>; 434 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 435 <&ccu CLK_DRAM_VE>; 436 clock-names = "ahb", "mod", "ram"; 437 resets = <&ccu RST_BUS_VE>; 438 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 439 allwinner,sram = <&ve_sram 1>; 440 }; 441 442 mmc0: mmc@1c0f000 { 443 compatible = "allwinner,sun50i-a64-mmc"; 444 reg = <0x01c0f000 0x1000>; 445 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 446 clock-names = "ahb", "mmc"; 447 resets = <&ccu RST_BUS_MMC0>; 448 reset-names = "ahb"; 449 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 450 max-frequency = <150000000>; 451 status = "disabled"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 }; 455 456 mmc1: mmc@1c10000 { 457 compatible = "allwinner,sun50i-a64-mmc"; 458 reg = <0x01c10000 0x1000>; 459 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 460 clock-names = "ahb", "mmc"; 461 resets = <&ccu RST_BUS_MMC1>; 462 reset-names = "ahb"; 463 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 464 max-frequency = <150000000>; 465 status = "disabled"; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 }; 469 470 mmc2: mmc@1c11000 { 471 compatible = "allwinner,sun50i-a64-emmc"; 472 reg = <0x01c11000 0x1000>; 473 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 474 clock-names = "ahb", "mmc"; 475 resets = <&ccu RST_BUS_MMC2>; 476 reset-names = "ahb"; 477 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 478 max-frequency = <200000000>; 479 status = "disabled"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 }; 483 484 sid: eeprom@1c14000 { 485 compatible = "allwinner,sun50i-a64-sid"; 486 reg = <0x1c14000 0x400>; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 490 ths_calibration: thermal-sensor-calibration@34 { 491 reg = <0x34 0x8>; 492 }; 493 }; 494 495 crypto: crypto@1c15000 { 496 compatible = "allwinner,sun50i-a64-crypto"; 497 reg = <0x01c15000 0x1000>; 498 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 500 clock-names = "bus", "mod"; 501 resets = <&ccu RST_BUS_CE>; 502 }; 503 504 usb_otg: usb@1c19000 { 505 compatible = "allwinner,sun8i-a33-musb"; 506 reg = <0x01c19000 0x0400>; 507 clocks = <&ccu CLK_BUS_OTG>; 508 resets = <&ccu RST_BUS_OTG>; 509 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 510 interrupt-names = "mc"; 511 phys = <&usbphy 0>; 512 phy-names = "usb"; 513 extcon = <&usbphy 0>; 514 dr_mode = "otg"; 515 status = "disabled"; 516 }; 517 518 usbphy: phy@1c19400 { 519 compatible = "allwinner,sun50i-a64-usb-phy"; 520 reg = <0x01c19400 0x14>, 521 <0x01c1a800 0x4>, 522 <0x01c1b800 0x4>; 523 reg-names = "phy_ctrl", 524 "pmu0", 525 "pmu1"; 526 clocks = <&ccu CLK_USB_PHY0>, 527 <&ccu CLK_USB_PHY1>; 528 clock-names = "usb0_phy", 529 "usb1_phy"; 530 resets = <&ccu RST_USB_PHY0>, 531 <&ccu RST_USB_PHY1>; 532 reset-names = "usb0_reset", 533 "usb1_reset"; 534 status = "disabled"; 535 #phy-cells = <1>; 536 }; 537 538 ehci0: usb@1c1a000 { 539 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 540 reg = <0x01c1a000 0x100>; 541 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&ccu CLK_BUS_OHCI0>, 543 <&ccu CLK_BUS_EHCI0>, 544 <&ccu CLK_USB_OHCI0>; 545 resets = <&ccu RST_BUS_OHCI0>, 546 <&ccu RST_BUS_EHCI0>; 547 status = "disabled"; 548 }; 549 550 ohci0: usb@1c1a400 { 551 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 552 reg = <0x01c1a400 0x100>; 553 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&ccu CLK_BUS_OHCI0>, 555 <&ccu CLK_USB_OHCI0>; 556 resets = <&ccu RST_BUS_OHCI0>; 557 status = "disabled"; 558 }; 559 560 ehci1: usb@1c1b000 { 561 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 562 reg = <0x01c1b000 0x100>; 563 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_BUS_OHCI1>, 565 <&ccu CLK_BUS_EHCI1>, 566 <&ccu CLK_USB_OHCI1>; 567 resets = <&ccu RST_BUS_OHCI1>, 568 <&ccu RST_BUS_EHCI1>; 569 phys = <&usbphy 1>; 570 phy-names = "usb"; 571 status = "disabled"; 572 }; 573 574 ohci1: usb@1c1b400 { 575 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 576 reg = <0x01c1b400 0x100>; 577 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&ccu CLK_BUS_OHCI1>, 579 <&ccu CLK_USB_OHCI1>; 580 resets = <&ccu RST_BUS_OHCI1>; 581 phys = <&usbphy 1>; 582 phy-names = "usb"; 583 status = "disabled"; 584 }; 585 586 ccu: clock@1c20000 { 587 compatible = "allwinner,sun50i-a64-ccu"; 588 reg = <0x01c20000 0x400>; 589 clocks = <&osc24M>, <&rtc 0>; 590 clock-names = "hosc", "losc"; 591 #clock-cells = <1>; 592 #reset-cells = <1>; 593 }; 594 595 pio: pinctrl@1c20800 { 596 compatible = "allwinner,sun50i-a64-pinctrl"; 597 reg = <0x01c20800 0x400>; 598 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 602 clock-names = "apb", "hosc", "losc"; 603 gpio-controller; 604 #gpio-cells = <3>; 605 interrupt-controller; 606 #interrupt-cells = <3>; 607 608 csi_pins: csi-pins { 609 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 610 "PE7", "PE8", "PE9", "PE10", "PE11"; 611 function = "csi"; 612 }; 613 614 /omit-if-no-ref/ 615 csi_mclk_pin: csi-mclk-pin { 616 pins = "PE1"; 617 function = "csi"; 618 }; 619 620 i2c0_pins: i2c0-pins { 621 pins = "PH0", "PH1"; 622 function = "i2c0"; 623 }; 624 625 i2c1_pins: i2c1-pins { 626 pins = "PH2", "PH3"; 627 function = "i2c1"; 628 }; 629 630 /omit-if-no-ref/ 631 lcd_rgb666_pins: lcd-rgb666-pins { 632 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 633 "PD5", "PD6", "PD7", "PD8", "PD9", 634 "PD10", "PD11", "PD12", "PD13", 635 "PD14", "PD15", "PD16", "PD17", 636 "PD18", "PD19", "PD20", "PD21"; 637 function = "lcd0"; 638 }; 639 640 mmc0_pins: mmc0-pins { 641 pins = "PF0", "PF1", "PF2", "PF3", 642 "PF4", "PF5"; 643 function = "mmc0"; 644 drive-strength = <30>; 645 bias-pull-up; 646 }; 647 648 mmc1_pins: mmc1-pins { 649 pins = "PG0", "PG1", "PG2", "PG3", 650 "PG4", "PG5"; 651 function = "mmc1"; 652 drive-strength = <30>; 653 bias-pull-up; 654 }; 655 656 mmc2_pins: mmc2-pins { 657 pins = "PC5", "PC6", "PC8", "PC9", 658 "PC10","PC11", "PC12", "PC13", 659 "PC14", "PC15", "PC16"; 660 function = "mmc2"; 661 drive-strength = <30>; 662 bias-pull-up; 663 }; 664 665 mmc2_ds_pin: mmc2-ds-pin { 666 pins = "PC1"; 667 function = "mmc2"; 668 drive-strength = <30>; 669 bias-pull-up; 670 }; 671 672 pwm_pin: pwm-pin { 673 pins = "PD22"; 674 function = "pwm"; 675 }; 676 677 rmii_pins: rmii-pins { 678 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 679 "PD18", "PD19", "PD20", "PD22", "PD23"; 680 function = "emac"; 681 drive-strength = <40>; 682 }; 683 684 rgmii_pins: rgmii-pins { 685 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 686 "PD13", "PD15", "PD16", "PD17", "PD18", 687 "PD19", "PD20", "PD21", "PD22", "PD23"; 688 function = "emac"; 689 drive-strength = <40>; 690 }; 691 692 spdif_tx_pin: spdif-tx-pin { 693 pins = "PH8"; 694 function = "spdif"; 695 }; 696 697 spi0_pins: spi0-pins { 698 pins = "PC0", "PC1", "PC2", "PC3"; 699 function = "spi0"; 700 }; 701 702 spi1_pins: spi1-pins { 703 pins = "PD0", "PD1", "PD2", "PD3"; 704 function = "spi1"; 705 }; 706 707 uart0_pb_pins: uart0-pb-pins { 708 pins = "PB8", "PB9"; 709 function = "uart0"; 710 }; 711 712 uart1_pins: uart1-pins { 713 pins = "PG6", "PG7"; 714 function = "uart1"; 715 }; 716 717 uart1_rts_cts_pins: uart1-rts-cts-pins { 718 pins = "PG8", "PG9"; 719 function = "uart1"; 720 }; 721 722 uart2_pins: uart2-pins { 723 pins = "PB0", "PB1"; 724 function = "uart2"; 725 }; 726 727 uart3_pins: uart3-pins { 728 pins = "PD0", "PD1"; 729 function = "uart3"; 730 }; 731 732 uart4_pins: uart4-pins { 733 pins = "PD2", "PD3"; 734 function = "uart4"; 735 }; 736 737 uart4_rts_cts_pins: uart4-rts-cts-pins { 738 pins = "PD4", "PD5"; 739 function = "uart4"; 740 }; 741 }; 742 743 spdif: spdif@1c21000 { 744 #sound-dai-cells = <0>; 745 compatible = "allwinner,sun50i-a64-spdif", 746 "allwinner,sun8i-h3-spdif"; 747 reg = <0x01c21000 0x400>; 748 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 750 resets = <&ccu RST_BUS_SPDIF>; 751 clock-names = "apb", "spdif"; 752 dmas = <&dma 2>; 753 dma-names = "tx"; 754 pinctrl-names = "default"; 755 pinctrl-0 = <&spdif_tx_pin>; 756 status = "disabled"; 757 }; 758 759 lradc: lradc@1c21800 { 760 compatible = "allwinner,sun50i-a64-lradc", 761 "allwinner,sun8i-a83t-r-lradc"; 762 reg = <0x01c21800 0x400>; 763 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 764 status = "disabled"; 765 }; 766 767 i2s0: i2s@1c22000 { 768 #sound-dai-cells = <0>; 769 compatible = "allwinner,sun50i-a64-i2s", 770 "allwinner,sun8i-h3-i2s"; 771 reg = <0x01c22000 0x400>; 772 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 774 clock-names = "apb", "mod"; 775 resets = <&ccu RST_BUS_I2S0>; 776 dma-names = "rx", "tx"; 777 dmas = <&dma 3>, <&dma 3>; 778 status = "disabled"; 779 }; 780 781 i2s1: i2s@1c22400 { 782 #sound-dai-cells = <0>; 783 compatible = "allwinner,sun50i-a64-i2s", 784 "allwinner,sun8i-h3-i2s"; 785 reg = <0x01c22400 0x400>; 786 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 788 clock-names = "apb", "mod"; 789 resets = <&ccu RST_BUS_I2S1>; 790 dma-names = "rx", "tx"; 791 dmas = <&dma 4>, <&dma 4>; 792 status = "disabled"; 793 }; 794 795 dai: dai@1c22c00 { 796 #sound-dai-cells = <0>; 797 compatible = "allwinner,sun50i-a64-codec-i2s"; 798 reg = <0x01c22c00 0x200>; 799 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 801 clock-names = "apb", "mod"; 802 resets = <&ccu RST_BUS_CODEC>; 803 dmas = <&dma 15>, <&dma 15>; 804 dma-names = "rx", "tx"; 805 status = "disabled"; 806 }; 807 808 codec: codec@1c22e00 { 809 #sound-dai-cells = <0>; 810 compatible = "allwinner,sun8i-a33-codec"; 811 reg = <0x01c22e00 0x600>; 812 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 814 clock-names = "bus", "mod"; 815 status = "disabled"; 816 }; 817 818 ths: thermal-sensor@1c25000 { 819 compatible = "allwinner,sun50i-a64-ths"; 820 reg = <0x01c25000 0x100>; 821 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 822 clock-names = "bus", "mod"; 823 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 824 resets = <&ccu RST_BUS_THS>; 825 nvmem-cells = <&ths_calibration>; 826 nvmem-cell-names = "calibration"; 827 #thermal-sensor-cells = <1>; 828 }; 829 830 uart0: serial@1c28000 { 831 compatible = "snps,dw-apb-uart"; 832 reg = <0x01c28000 0x400>; 833 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 834 reg-shift = <2>; 835 reg-io-width = <4>; 836 clocks = <&ccu CLK_BUS_UART0>; 837 resets = <&ccu RST_BUS_UART0>; 838 status = "disabled"; 839 }; 840 841 uart1: serial@1c28400 { 842 compatible = "snps,dw-apb-uart"; 843 reg = <0x01c28400 0x400>; 844 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 845 reg-shift = <2>; 846 reg-io-width = <4>; 847 clocks = <&ccu CLK_BUS_UART1>; 848 resets = <&ccu RST_BUS_UART1>; 849 status = "disabled"; 850 }; 851 852 uart2: serial@1c28800 { 853 compatible = "snps,dw-apb-uart"; 854 reg = <0x01c28800 0x400>; 855 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 856 reg-shift = <2>; 857 reg-io-width = <4>; 858 clocks = <&ccu CLK_BUS_UART2>; 859 resets = <&ccu RST_BUS_UART2>; 860 status = "disabled"; 861 }; 862 863 uart3: serial@1c28c00 { 864 compatible = "snps,dw-apb-uart"; 865 reg = <0x01c28c00 0x400>; 866 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 867 reg-shift = <2>; 868 reg-io-width = <4>; 869 clocks = <&ccu CLK_BUS_UART3>; 870 resets = <&ccu RST_BUS_UART3>; 871 status = "disabled"; 872 }; 873 874 uart4: serial@1c29000 { 875 compatible = "snps,dw-apb-uart"; 876 reg = <0x01c29000 0x400>; 877 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 878 reg-shift = <2>; 879 reg-io-width = <4>; 880 clocks = <&ccu CLK_BUS_UART4>; 881 resets = <&ccu RST_BUS_UART4>; 882 status = "disabled"; 883 }; 884 885 i2c0: i2c@1c2ac00 { 886 compatible = "allwinner,sun6i-a31-i2c"; 887 reg = <0x01c2ac00 0x400>; 888 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&ccu CLK_BUS_I2C0>; 890 resets = <&ccu RST_BUS_I2C0>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&i2c0_pins>; 893 status = "disabled"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 }; 897 898 i2c1: i2c@1c2b000 { 899 compatible = "allwinner,sun6i-a31-i2c"; 900 reg = <0x01c2b000 0x400>; 901 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&ccu CLK_BUS_I2C1>; 903 resets = <&ccu RST_BUS_I2C1>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&i2c1_pins>; 906 status = "disabled"; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 }; 910 911 i2c2: i2c@1c2b400 { 912 compatible = "allwinner,sun6i-a31-i2c"; 913 reg = <0x01c2b400 0x400>; 914 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&ccu CLK_BUS_I2C2>; 916 resets = <&ccu RST_BUS_I2C2>; 917 status = "disabled"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 }; 921 922 923 spi0: spi@1c68000 { 924 compatible = "allwinner,sun8i-h3-spi"; 925 reg = <0x01c68000 0x1000>; 926 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 928 clock-names = "ahb", "mod"; 929 dmas = <&dma 23>, <&dma 23>; 930 dma-names = "rx", "tx"; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&spi0_pins>; 933 resets = <&ccu RST_BUS_SPI0>; 934 status = "disabled"; 935 num-cs = <1>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 }; 939 940 spi1: spi@1c69000 { 941 compatible = "allwinner,sun8i-h3-spi"; 942 reg = <0x01c69000 0x1000>; 943 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 945 clock-names = "ahb", "mod"; 946 dmas = <&dma 24>, <&dma 24>; 947 dma-names = "rx", "tx"; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&spi1_pins>; 950 resets = <&ccu RST_BUS_SPI1>; 951 status = "disabled"; 952 num-cs = <1>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 }; 956 957 emac: ethernet@1c30000 { 958 compatible = "allwinner,sun50i-a64-emac"; 959 syscon = <&syscon>; 960 reg = <0x01c30000 0x10000>; 961 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 962 interrupt-names = "macirq"; 963 resets = <&ccu RST_BUS_EMAC>; 964 reset-names = "stmmaceth"; 965 clocks = <&ccu CLK_BUS_EMAC>; 966 clock-names = "stmmaceth"; 967 status = "disabled"; 968 969 mdio: mdio { 970 compatible = "snps,dwmac-mdio"; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 }; 974 }; 975 976 mali: gpu@1c40000 { 977 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 978 reg = <0x01c40000 0x10000>; 979 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 986 interrupt-names = "gp", 987 "gpmmu", 988 "pp0", 989 "ppmmu0", 990 "pp1", 991 "ppmmu1", 992 "pmu"; 993 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 994 clock-names = "bus", "core"; 995 resets = <&ccu RST_BUS_GPU>; 996 }; 997 998 gic: interrupt-controller@1c81000 { 999 compatible = "arm,gic-400"; 1000 reg = <0x01c81000 0x1000>, 1001 <0x01c82000 0x2000>, 1002 <0x01c84000 0x2000>, 1003 <0x01c86000 0x2000>; 1004 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1005 interrupt-controller; 1006 #interrupt-cells = <3>; 1007 }; 1008 1009 pwm: pwm@1c21400 { 1010 compatible = "allwinner,sun50i-a64-pwm", 1011 "allwinner,sun5i-a13-pwm"; 1012 reg = <0x01c21400 0x400>; 1013 clocks = <&osc24M>; 1014 pinctrl-names = "default"; 1015 pinctrl-0 = <&pwm_pin>; 1016 #pwm-cells = <3>; 1017 status = "disabled"; 1018 }; 1019 1020 csi: csi@1cb0000 { 1021 compatible = "allwinner,sun50i-a64-csi"; 1022 reg = <0x01cb0000 0x1000>; 1023 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&ccu CLK_BUS_CSI>, 1025 <&ccu CLK_CSI_SCLK>, 1026 <&ccu CLK_DRAM_CSI>; 1027 clock-names = "bus", "mod", "ram"; 1028 resets = <&ccu RST_BUS_CSI>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&csi_pins>; 1031 status = "disabled"; 1032 }; 1033 1034 dsi: dsi@1ca0000 { 1035 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1036 reg = <0x01ca0000 0x1000>; 1037 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1039 resets = <&ccu RST_BUS_MIPI_DSI>; 1040 phys = <&dphy>; 1041 phy-names = "dphy"; 1042 status = "disabled"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 1046 port { 1047 dsi_in_tcon0: endpoint { 1048 remote-endpoint = <&tcon0_out_dsi>; 1049 }; 1050 }; 1051 }; 1052 1053 dphy: d-phy@1ca1000 { 1054 compatible = "allwinner,sun50i-a64-mipi-dphy", 1055 "allwinner,sun6i-a31-mipi-dphy"; 1056 reg = <0x01ca1000 0x1000>; 1057 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1058 <&ccu CLK_DSI_DPHY>; 1059 clock-names = "bus", "mod"; 1060 resets = <&ccu RST_BUS_MIPI_DSI>; 1061 status = "disabled"; 1062 #phy-cells = <0>; 1063 }; 1064 1065 hdmi: hdmi@1ee0000 { 1066 compatible = "allwinner,sun50i-a64-dw-hdmi", 1067 "allwinner,sun8i-a83t-dw-hdmi"; 1068 reg = <0x01ee0000 0x10000>; 1069 reg-io-width = <1>; 1070 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1072 <&ccu CLK_HDMI>; 1073 clock-names = "iahb", "isfr", "tmds"; 1074 resets = <&ccu RST_BUS_HDMI1>; 1075 reset-names = "ctrl"; 1076 phys = <&hdmi_phy>; 1077 phy-names = "phy"; 1078 status = "disabled"; 1079 1080 ports { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 hdmi_in: port@0 { 1085 reg = <0>; 1086 1087 hdmi_in_tcon1: endpoint { 1088 remote-endpoint = <&tcon1_out_hdmi>; 1089 }; 1090 }; 1091 1092 hdmi_out: port@1 { 1093 reg = <1>; 1094 }; 1095 }; 1096 }; 1097 1098 hdmi_phy: hdmi-phy@1ef0000 { 1099 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1100 reg = <0x01ef0000 0x10000>; 1101 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1102 <&ccu CLK_PLL_VIDEO0>; 1103 clock-names = "bus", "mod", "pll-0"; 1104 resets = <&ccu RST_BUS_HDMI0>; 1105 reset-names = "phy"; 1106 #phy-cells = <0>; 1107 }; 1108 1109 rtc: rtc@1f00000 { 1110 compatible = "allwinner,sun50i-a64-rtc", 1111 "allwinner,sun8i-h3-rtc"; 1112 reg = <0x01f00000 0x400>; 1113 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1115 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1116 clocks = <&osc32k>; 1117 #clock-cells = <1>; 1118 }; 1119 1120 r_intc: interrupt-controller@1f00c00 { 1121 compatible = "allwinner,sun50i-a64-r-intc", 1122 "allwinner,sun6i-a31-r-intc"; 1123 interrupt-controller; 1124 #interrupt-cells = <2>; 1125 reg = <0x01f00c00 0x400>; 1126 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1127 }; 1128 1129 r_ccu: clock@1f01400 { 1130 compatible = "allwinner,sun50i-a64-r-ccu"; 1131 reg = <0x01f01400 0x100>; 1132 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1133 <&ccu CLK_PLL_PERIPH0>; 1134 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1135 #clock-cells = <1>; 1136 #reset-cells = <1>; 1137 }; 1138 1139 codec_analog: codec-analog@1f015c0 { 1140 compatible = "allwinner,sun50i-a64-codec-analog"; 1141 reg = <0x01f015c0 0x4>; 1142 status = "disabled"; 1143 }; 1144 1145 r_i2c: i2c@1f02400 { 1146 compatible = "allwinner,sun50i-a64-i2c", 1147 "allwinner,sun6i-a31-i2c"; 1148 reg = <0x01f02400 0x400>; 1149 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&r_ccu CLK_APB0_I2C>; 1151 resets = <&r_ccu RST_APB0_I2C>; 1152 status = "disabled"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 }; 1156 1157 r_ir: ir@1f02000 { 1158 compatible = "allwinner,sun50i-a64-ir", 1159 "allwinner,sun6i-a31-ir"; 1160 reg = <0x01f02000 0x400>; 1161 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1162 clock-names = "apb", "ir"; 1163 resets = <&r_ccu RST_APB0_IR>; 1164 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&r_ir_rx_pin>; 1167 status = "disabled"; 1168 }; 1169 1170 r_pwm: pwm@1f03800 { 1171 compatible = "allwinner,sun50i-a64-pwm", 1172 "allwinner,sun5i-a13-pwm"; 1173 reg = <0x01f03800 0x400>; 1174 clocks = <&osc24M>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&r_pwm_pin>; 1177 #pwm-cells = <3>; 1178 status = "disabled"; 1179 }; 1180 1181 r_pio: pinctrl@1f02c00 { 1182 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1183 reg = <0x01f02c00 0x400>; 1184 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1186 clock-names = "apb", "hosc", "losc"; 1187 gpio-controller; 1188 #gpio-cells = <3>; 1189 interrupt-controller; 1190 #interrupt-cells = <3>; 1191 1192 r_i2c_pl89_pins: r-i2c-pl89-pins { 1193 pins = "PL8", "PL9"; 1194 function = "s_i2c"; 1195 }; 1196 1197 r_ir_rx_pin: r-ir-rx-pin { 1198 pins = "PL11"; 1199 function = "s_cir_rx"; 1200 }; 1201 1202 r_pwm_pin: r-pwm-pin { 1203 pins = "PL10"; 1204 function = "s_pwm"; 1205 }; 1206 1207 r_rsb_pins: r-rsb-pins { 1208 pins = "PL0", "PL1"; 1209 function = "s_rsb"; 1210 }; 1211 }; 1212 1213 r_rsb: rsb@1f03400 { 1214 compatible = "allwinner,sun8i-a23-rsb"; 1215 reg = <0x01f03400 0x400>; 1216 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&r_ccu 6>; 1218 clock-frequency = <3000000>; 1219 resets = <&r_ccu 2>; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&r_rsb_pins>; 1222 status = "disabled"; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 }; 1226 1227 wdt0: watchdog@1c20ca0 { 1228 compatible = "allwinner,sun50i-a64-wdt", 1229 "allwinner,sun6i-a31-wdt"; 1230 reg = <0x01c20ca0 0x20>; 1231 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&osc24M>; 1233 }; 1234 }; 1235}; 1236