1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 psci { 146 compatible = "arm,psci-0.2"; 147 method = "smc"; 148 }; 149 150 sound: sound { 151 compatible = "simple-audio-card"; 152 simple-audio-card,name = "sun50i-a64-audio"; 153 simple-audio-card,format = "i2s"; 154 simple-audio-card,frame-master = <&cpudai>; 155 simple-audio-card,bitclock-master = <&cpudai>; 156 simple-audio-card,mclk-fs = <128>; 157 simple-audio-card,aux-devs = <&codec_analog>; 158 simple-audio-card,routing = 159 "Left DAC", "AIF1 Slot 0 Left", 160 "Right DAC", "AIF1 Slot 0 Right", 161 "AIF1 Slot 0 Left ADC", "Left ADC", 162 "AIF1 Slot 0 Right ADC", "Right ADC"; 163 status = "disabled"; 164 165 cpudai: simple-audio-card,cpu { 166 sound-dai = <&dai>; 167 }; 168 169 link_codec: simple-audio-card,codec { 170 sound-dai = <&codec>; 171 }; 172 }; 173 174 sound_spdif { 175 compatible = "simple-audio-card"; 176 simple-audio-card,name = "On-board SPDIF"; 177 178 simple-audio-card,cpu { 179 sound-dai = <&spdif>; 180 }; 181 182 simple-audio-card,codec { 183 sound-dai = <&spdif_out>; 184 }; 185 }; 186 187 spdif_out: spdif-out { 188 #sound-dai-cells = <0>; 189 compatible = "linux,spdif-dit"; 190 }; 191 192 timer { 193 compatible = "arm,armv8-timer"; 194 allwinner,erratum-unknown1; 195 interrupts = <GIC_PPI 13 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 197 <GIC_PPI 14 198 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 199 <GIC_PPI 11 200 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 201 <GIC_PPI 10 202 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 }; 204 205 soc { 206 compatible = "simple-bus"; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges; 210 211 bus@1000000 { 212 compatible = "allwinner,sun50i-a64-de2"; 213 reg = <0x1000000 0x400000>; 214 allwinner,sram = <&de2_sram 1>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0 0x1000000 0x400000>; 218 219 display_clocks: clock@0 { 220 compatible = "allwinner,sun50i-a64-de2-clk"; 221 reg = <0x0 0x100000>; 222 clocks = <&ccu CLK_BUS_DE>, 223 <&ccu CLK_DE>; 224 clock-names = "bus", 225 "mod"; 226 resets = <&ccu RST_BUS_DE>; 227 #clock-cells = <1>; 228 #reset-cells = <1>; 229 }; 230 231 mixer0: mixer@100000 { 232 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 233 reg = <0x100000 0x100000>; 234 clocks = <&display_clocks CLK_BUS_MIXER0>, 235 <&display_clocks CLK_MIXER0>; 236 clock-names = "bus", 237 "mod"; 238 resets = <&display_clocks RST_MIXER0>; 239 240 ports { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 mixer0_out: port@1 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 reg = <1>; 248 249 mixer0_out_tcon0: endpoint@0 { 250 reg = <0>; 251 remote-endpoint = <&tcon0_in_mixer0>; 252 }; 253 254 mixer0_out_tcon1: endpoint@1 { 255 reg = <1>; 256 remote-endpoint = <&tcon1_in_mixer0>; 257 }; 258 }; 259 }; 260 }; 261 262 mixer1: mixer@200000 { 263 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 264 reg = <0x200000 0x100000>; 265 clocks = <&display_clocks CLK_BUS_MIXER1>, 266 <&display_clocks CLK_MIXER1>; 267 clock-names = "bus", 268 "mod"; 269 resets = <&display_clocks RST_MIXER1>; 270 271 ports { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 mixer1_out: port@1 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <1>; 279 280 mixer1_out_tcon0: endpoint@0 { 281 reg = <0>; 282 remote-endpoint = <&tcon0_in_mixer1>; 283 }; 284 285 mixer1_out_tcon1: endpoint@1 { 286 reg = <1>; 287 remote-endpoint = <&tcon1_in_mixer1>; 288 }; 289 }; 290 }; 291 }; 292 }; 293 294 syscon: syscon@1c00000 { 295 compatible = "allwinner,sun50i-a64-system-control"; 296 reg = <0x01c00000 0x1000>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 ranges; 300 301 sram_c: sram@18000 { 302 compatible = "mmio-sram"; 303 reg = <0x00018000 0x28000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges = <0 0x00018000 0x28000>; 307 308 de2_sram: sram-section@0 { 309 compatible = "allwinner,sun50i-a64-sram-c"; 310 reg = <0x0000 0x28000>; 311 }; 312 }; 313 314 sram_c1: sram@1d00000 { 315 compatible = "mmio-sram"; 316 reg = <0x01d00000 0x40000>; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges = <0 0x01d00000 0x40000>; 320 321 ve_sram: sram-section@0 { 322 compatible = "allwinner,sun50i-a64-sram-c1", 323 "allwinner,sun4i-a10-sram-c1"; 324 reg = <0x000000 0x40000>; 325 }; 326 }; 327 }; 328 329 dma: dma-controller@1c02000 { 330 compatible = "allwinner,sun50i-a64-dma"; 331 reg = <0x01c02000 0x1000>; 332 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_DMA>; 334 dma-channels = <8>; 335 dma-requests = <27>; 336 resets = <&ccu RST_BUS_DMA>; 337 #dma-cells = <1>; 338 }; 339 340 tcon0: lcd-controller@1c0c000 { 341 compatible = "allwinner,sun50i-a64-tcon-lcd", 342 "allwinner,sun8i-a83t-tcon-lcd"; 343 reg = <0x01c0c000 0x1000>; 344 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 346 clock-names = "ahb", "tcon-ch0"; 347 clock-output-names = "tcon-pixel-clock"; 348 #clock-cells = <0>; 349 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 350 reset-names = "lcd", "lvds"; 351 352 ports { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 356 tcon0_in: port@0 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 reg = <0>; 360 361 tcon0_in_mixer0: endpoint@0 { 362 reg = <0>; 363 remote-endpoint = <&mixer0_out_tcon0>; 364 }; 365 366 tcon0_in_mixer1: endpoint@1 { 367 reg = <1>; 368 remote-endpoint = <&mixer1_out_tcon0>; 369 }; 370 }; 371 372 tcon0_out: port@1 { 373 #address-cells = <1>; 374 #size-cells = <0>; 375 reg = <1>; 376 }; 377 }; 378 }; 379 380 tcon1: lcd-controller@1c0d000 { 381 compatible = "allwinner,sun50i-a64-tcon-tv", 382 "allwinner,sun8i-a83t-tcon-tv"; 383 reg = <0x01c0d000 0x1000>; 384 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 386 clock-names = "ahb", "tcon-ch1"; 387 resets = <&ccu RST_BUS_TCON1>; 388 reset-names = "lcd"; 389 390 ports { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 tcon1_in: port@0 { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 reg = <0>; 398 399 tcon1_in_mixer0: endpoint@0 { 400 reg = <0>; 401 remote-endpoint = <&mixer0_out_tcon1>; 402 }; 403 404 tcon1_in_mixer1: endpoint@1 { 405 reg = <1>; 406 remote-endpoint = <&mixer1_out_tcon1>; 407 }; 408 }; 409 410 tcon1_out: port@1 { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <1>; 414 415 tcon1_out_hdmi: endpoint@1 { 416 reg = <1>; 417 remote-endpoint = <&hdmi_in_tcon1>; 418 }; 419 }; 420 }; 421 }; 422 423 video-codec@1c0e000 { 424 compatible = "allwinner,sun50i-a64-video-engine"; 425 reg = <0x01c0e000 0x1000>; 426 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 427 <&ccu CLK_DRAM_VE>; 428 clock-names = "ahb", "mod", "ram"; 429 resets = <&ccu RST_BUS_VE>; 430 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 431 allwinner,sram = <&ve_sram 1>; 432 }; 433 434 mmc0: mmc@1c0f000 { 435 compatible = "allwinner,sun50i-a64-mmc"; 436 reg = <0x01c0f000 0x1000>; 437 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 438 clock-names = "ahb", "mmc"; 439 resets = <&ccu RST_BUS_MMC0>; 440 reset-names = "ahb"; 441 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 442 max-frequency = <150000000>; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 mmc1: mmc@1c10000 { 449 compatible = "allwinner,sun50i-a64-mmc"; 450 reg = <0x01c10000 0x1000>; 451 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 452 clock-names = "ahb", "mmc"; 453 resets = <&ccu RST_BUS_MMC1>; 454 reset-names = "ahb"; 455 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 456 max-frequency = <150000000>; 457 status = "disabled"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 }; 461 462 mmc2: mmc@1c11000 { 463 compatible = "allwinner,sun50i-a64-emmc"; 464 reg = <0x01c11000 0x1000>; 465 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 466 clock-names = "ahb", "mmc"; 467 resets = <&ccu RST_BUS_MMC2>; 468 reset-names = "ahb"; 469 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 470 max-frequency = <200000000>; 471 status = "disabled"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 }; 475 476 sid: eeprom@1c14000 { 477 compatible = "allwinner,sun50i-a64-sid"; 478 reg = <0x1c14000 0x400>; 479 }; 480 481 usb_otg: usb@1c19000 { 482 compatible = "allwinner,sun8i-a33-musb"; 483 reg = <0x01c19000 0x0400>; 484 clocks = <&ccu CLK_BUS_OTG>; 485 resets = <&ccu RST_BUS_OTG>; 486 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "mc"; 488 phys = <&usbphy 0>; 489 phy-names = "usb"; 490 extcon = <&usbphy 0>; 491 dr_mode = "otg"; 492 status = "disabled"; 493 }; 494 495 usbphy: phy@1c19400 { 496 compatible = "allwinner,sun50i-a64-usb-phy"; 497 reg = <0x01c19400 0x14>, 498 <0x01c1a800 0x4>, 499 <0x01c1b800 0x4>; 500 reg-names = "phy_ctrl", 501 "pmu0", 502 "pmu1"; 503 clocks = <&ccu CLK_USB_PHY0>, 504 <&ccu CLK_USB_PHY1>; 505 clock-names = "usb0_phy", 506 "usb1_phy"; 507 resets = <&ccu RST_USB_PHY0>, 508 <&ccu RST_USB_PHY1>; 509 reset-names = "usb0_reset", 510 "usb1_reset"; 511 status = "disabled"; 512 #phy-cells = <1>; 513 }; 514 515 ehci0: usb@1c1a000 { 516 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 517 reg = <0x01c1a000 0x100>; 518 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&ccu CLK_BUS_OHCI0>, 520 <&ccu CLK_BUS_EHCI0>, 521 <&ccu CLK_USB_OHCI0>; 522 resets = <&ccu RST_BUS_OHCI0>, 523 <&ccu RST_BUS_EHCI0>; 524 status = "disabled"; 525 }; 526 527 ohci0: usb@1c1a400 { 528 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 529 reg = <0x01c1a400 0x100>; 530 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&ccu CLK_BUS_OHCI0>, 532 <&ccu CLK_USB_OHCI0>; 533 resets = <&ccu RST_BUS_OHCI0>; 534 status = "disabled"; 535 }; 536 537 ehci1: usb@1c1b000 { 538 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 539 reg = <0x01c1b000 0x100>; 540 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&ccu CLK_BUS_OHCI1>, 542 <&ccu CLK_BUS_EHCI1>, 543 <&ccu CLK_USB_OHCI1>; 544 resets = <&ccu RST_BUS_OHCI1>, 545 <&ccu RST_BUS_EHCI1>; 546 phys = <&usbphy 1>; 547 status = "disabled"; 548 }; 549 550 ohci1: usb@1c1b400 { 551 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 552 reg = <0x01c1b400 0x100>; 553 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&ccu CLK_BUS_OHCI1>, 555 <&ccu CLK_USB_OHCI1>; 556 resets = <&ccu RST_BUS_OHCI1>; 557 phys = <&usbphy 1>; 558 status = "disabled"; 559 }; 560 561 ccu: clock@1c20000 { 562 compatible = "allwinner,sun50i-a64-ccu"; 563 reg = <0x01c20000 0x400>; 564 clocks = <&osc24M>, <&rtc 0>; 565 clock-names = "hosc", "losc"; 566 #clock-cells = <1>; 567 #reset-cells = <1>; 568 }; 569 570 pio: pinctrl@1c20800 { 571 compatible = "allwinner,sun50i-a64-pinctrl"; 572 reg = <0x01c20800 0x400>; 573 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 577 clock-names = "apb", "hosc", "losc"; 578 gpio-controller; 579 #gpio-cells = <3>; 580 interrupt-controller; 581 #interrupt-cells = <3>; 582 583 csi_pins: csi-pins { 584 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 585 "PE7", "PE8", "PE9", "PE10", "PE11"; 586 function = "csi"; 587 }; 588 589 /omit-if-no-ref/ 590 csi_mclk_pin: csi-mclk-pin { 591 pins = "PE1"; 592 function = "csi"; 593 }; 594 595 i2c0_pins: i2c0-pins { 596 pins = "PH0", "PH1"; 597 function = "i2c0"; 598 }; 599 600 i2c1_pins: i2c1-pins { 601 pins = "PH2", "PH3"; 602 function = "i2c1"; 603 }; 604 605 /omit-if-no-ref/ 606 lcd_rgb666_pins: lcd-rgb666-pins { 607 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 608 "PD5", "PD6", "PD7", "PD8", "PD9", 609 "PD10", "PD11", "PD12", "PD13", 610 "PD14", "PD15", "PD16", "PD17", 611 "PD18", "PD19", "PD20", "PD21"; 612 function = "lcd0"; 613 }; 614 615 mmc0_pins: mmc0-pins { 616 pins = "PF0", "PF1", "PF2", "PF3", 617 "PF4", "PF5"; 618 function = "mmc0"; 619 drive-strength = <30>; 620 bias-pull-up; 621 }; 622 623 mmc1_pins: mmc1-pins { 624 pins = "PG0", "PG1", "PG2", "PG3", 625 "PG4", "PG5"; 626 function = "mmc1"; 627 drive-strength = <30>; 628 bias-pull-up; 629 }; 630 631 mmc2_pins: mmc2-pins { 632 pins = "PC5", "PC6", "PC8", "PC9", 633 "PC10","PC11", "PC12", "PC13", 634 "PC14", "PC15", "PC16"; 635 function = "mmc2"; 636 drive-strength = <30>; 637 bias-pull-up; 638 }; 639 640 mmc2_ds_pin: mmc2-ds-pin { 641 pins = "PC1"; 642 function = "mmc2"; 643 drive-strength = <30>; 644 bias-pull-up; 645 }; 646 647 pwm_pin: pwm-pin { 648 pins = "PD22"; 649 function = "pwm"; 650 }; 651 652 rmii_pins: rmii-pins { 653 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 654 "PD18", "PD19", "PD20", "PD22", "PD23"; 655 function = "emac"; 656 drive-strength = <40>; 657 }; 658 659 rgmii_pins: rgmii-pins { 660 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 661 "PD13", "PD15", "PD16", "PD17", "PD18", 662 "PD19", "PD20", "PD21", "PD22", "PD23"; 663 function = "emac"; 664 drive-strength = <40>; 665 }; 666 667 spdif_tx_pin: spdif-tx-pin { 668 pins = "PH8"; 669 function = "spdif"; 670 }; 671 672 spi0_pins: spi0-pins { 673 pins = "PC0", "PC1", "PC2", "PC3"; 674 function = "spi0"; 675 }; 676 677 spi1_pins: spi1-pins { 678 pins = "PD0", "PD1", "PD2", "PD3"; 679 function = "spi1"; 680 }; 681 682 uart0_pb_pins: uart0-pb-pins { 683 pins = "PB8", "PB9"; 684 function = "uart0"; 685 }; 686 687 uart1_pins: uart1-pins { 688 pins = "PG6", "PG7"; 689 function = "uart1"; 690 }; 691 692 uart1_rts_cts_pins: uart1-rts-cts-pins { 693 pins = "PG8", "PG9"; 694 function = "uart1"; 695 }; 696 697 uart2_pins: uart2-pins { 698 pins = "PB0", "PB1"; 699 function = "uart2"; 700 }; 701 702 uart3_pins: uart3-pins { 703 pins = "PD0", "PD1"; 704 function = "uart3"; 705 }; 706 707 uart4_pins: uart4-pins { 708 pins = "PD2", "PD3"; 709 function = "uart4"; 710 }; 711 712 uart4_rts_cts_pins: uart4-rts-cts-pins { 713 pins = "PD4", "PD5"; 714 function = "uart4"; 715 }; 716 }; 717 718 spdif: spdif@1c21000 { 719 #sound-dai-cells = <0>; 720 compatible = "allwinner,sun50i-a64-spdif", 721 "allwinner,sun8i-h3-spdif"; 722 reg = <0x01c21000 0x400>; 723 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 725 resets = <&ccu RST_BUS_SPDIF>; 726 clock-names = "apb", "spdif"; 727 dmas = <&dma 2>; 728 dma-names = "tx"; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&spdif_tx_pin>; 731 status = "disabled"; 732 }; 733 734 lradc: lradc@1c21800 { 735 compatible = "allwinner,sun50i-a64-lradc", 736 "allwinner,sun8i-a83t-r-lradc"; 737 reg = <0x01c21800 0x400>; 738 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 739 status = "disabled"; 740 }; 741 742 i2s0: i2s@1c22000 { 743 #sound-dai-cells = <0>; 744 compatible = "allwinner,sun50i-a64-i2s", 745 "allwinner,sun8i-h3-i2s"; 746 reg = <0x01c22000 0x400>; 747 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 749 clock-names = "apb", "mod"; 750 resets = <&ccu RST_BUS_I2S0>; 751 dma-names = "rx", "tx"; 752 dmas = <&dma 3>, <&dma 3>; 753 status = "disabled"; 754 }; 755 756 i2s1: i2s@1c22400 { 757 #sound-dai-cells = <0>; 758 compatible = "allwinner,sun50i-a64-i2s", 759 "allwinner,sun8i-h3-i2s"; 760 reg = <0x01c22400 0x400>; 761 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 763 clock-names = "apb", "mod"; 764 resets = <&ccu RST_BUS_I2S1>; 765 dma-names = "rx", "tx"; 766 dmas = <&dma 4>, <&dma 4>; 767 status = "disabled"; 768 }; 769 770 dai: dai@1c22c00 { 771 #sound-dai-cells = <0>; 772 compatible = "allwinner,sun50i-a64-codec-i2s"; 773 reg = <0x01c22c00 0x200>; 774 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 776 clock-names = "apb", "mod"; 777 resets = <&ccu RST_BUS_CODEC>; 778 dmas = <&dma 15>, <&dma 15>; 779 dma-names = "rx", "tx"; 780 status = "disabled"; 781 }; 782 783 codec: codec@1c22e00 { 784 #sound-dai-cells = <0>; 785 compatible = "allwinner,sun8i-a33-codec"; 786 reg = <0x01c22e00 0x600>; 787 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 789 clock-names = "bus", "mod"; 790 status = "disabled"; 791 }; 792 793 uart0: serial@1c28000 { 794 compatible = "snps,dw-apb-uart"; 795 reg = <0x01c28000 0x400>; 796 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 797 reg-shift = <2>; 798 reg-io-width = <4>; 799 clocks = <&ccu CLK_BUS_UART0>; 800 resets = <&ccu RST_BUS_UART0>; 801 status = "disabled"; 802 }; 803 804 uart1: serial@1c28400 { 805 compatible = "snps,dw-apb-uart"; 806 reg = <0x01c28400 0x400>; 807 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 808 reg-shift = <2>; 809 reg-io-width = <4>; 810 clocks = <&ccu CLK_BUS_UART1>; 811 resets = <&ccu RST_BUS_UART1>; 812 status = "disabled"; 813 }; 814 815 uart2: serial@1c28800 { 816 compatible = "snps,dw-apb-uart"; 817 reg = <0x01c28800 0x400>; 818 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 819 reg-shift = <2>; 820 reg-io-width = <4>; 821 clocks = <&ccu CLK_BUS_UART2>; 822 resets = <&ccu RST_BUS_UART2>; 823 status = "disabled"; 824 }; 825 826 uart3: serial@1c28c00 { 827 compatible = "snps,dw-apb-uart"; 828 reg = <0x01c28c00 0x400>; 829 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 830 reg-shift = <2>; 831 reg-io-width = <4>; 832 clocks = <&ccu CLK_BUS_UART3>; 833 resets = <&ccu RST_BUS_UART3>; 834 status = "disabled"; 835 }; 836 837 uart4: serial@1c29000 { 838 compatible = "snps,dw-apb-uart"; 839 reg = <0x01c29000 0x400>; 840 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 841 reg-shift = <2>; 842 reg-io-width = <4>; 843 clocks = <&ccu CLK_BUS_UART4>; 844 resets = <&ccu RST_BUS_UART4>; 845 status = "disabled"; 846 }; 847 848 i2c0: i2c@1c2ac00 { 849 compatible = "allwinner,sun6i-a31-i2c"; 850 reg = <0x01c2ac00 0x400>; 851 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&ccu CLK_BUS_I2C0>; 853 resets = <&ccu RST_BUS_I2C0>; 854 pinctrl-names = "default"; 855 pinctrl-0 = <&i2c0_pins>; 856 status = "disabled"; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 }; 860 861 i2c1: i2c@1c2b000 { 862 compatible = "allwinner,sun6i-a31-i2c"; 863 reg = <0x01c2b000 0x400>; 864 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&ccu CLK_BUS_I2C1>; 866 resets = <&ccu RST_BUS_I2C1>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&i2c1_pins>; 869 status = "disabled"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 }; 873 874 i2c2: i2c@1c2b400 { 875 compatible = "allwinner,sun6i-a31-i2c"; 876 reg = <0x01c2b400 0x400>; 877 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&ccu CLK_BUS_I2C2>; 879 resets = <&ccu RST_BUS_I2C2>; 880 status = "disabled"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 }; 884 885 886 spi0: spi@1c68000 { 887 compatible = "allwinner,sun8i-h3-spi"; 888 reg = <0x01c68000 0x1000>; 889 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 891 clock-names = "ahb", "mod"; 892 dmas = <&dma 23>, <&dma 23>; 893 dma-names = "rx", "tx"; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&spi0_pins>; 896 resets = <&ccu RST_BUS_SPI0>; 897 status = "disabled"; 898 num-cs = <1>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 }; 902 903 spi1: spi@1c69000 { 904 compatible = "allwinner,sun8i-h3-spi"; 905 reg = <0x01c69000 0x1000>; 906 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 908 clock-names = "ahb", "mod"; 909 dmas = <&dma 24>, <&dma 24>; 910 dma-names = "rx", "tx"; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&spi1_pins>; 913 resets = <&ccu RST_BUS_SPI1>; 914 status = "disabled"; 915 num-cs = <1>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 }; 919 920 emac: ethernet@1c30000 { 921 compatible = "allwinner,sun50i-a64-emac"; 922 syscon = <&syscon>; 923 reg = <0x01c30000 0x10000>; 924 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "macirq"; 926 resets = <&ccu RST_BUS_EMAC>; 927 reset-names = "stmmaceth"; 928 clocks = <&ccu CLK_BUS_EMAC>; 929 clock-names = "stmmaceth"; 930 status = "disabled"; 931 932 mdio: mdio { 933 compatible = "snps,dwmac-mdio"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 }; 937 }; 938 939 mali: gpu@1c40000 { 940 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 941 reg = <0x01c40000 0x10000>; 942 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "gp", 950 "gpmmu", 951 "pp0", 952 "ppmmu0", 953 "pp1", 954 "ppmmu1", 955 "pmu"; 956 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 957 clock-names = "bus", "core"; 958 resets = <&ccu RST_BUS_GPU>; 959 }; 960 961 gic: interrupt-controller@1c81000 { 962 compatible = "arm,gic-400"; 963 reg = <0x01c81000 0x1000>, 964 <0x01c82000 0x2000>, 965 <0x01c84000 0x2000>, 966 <0x01c86000 0x2000>; 967 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 968 interrupt-controller; 969 #interrupt-cells = <3>; 970 }; 971 972 pwm: pwm@1c21400 { 973 compatible = "allwinner,sun50i-a64-pwm", 974 "allwinner,sun5i-a13-pwm"; 975 reg = <0x01c21400 0x400>; 976 clocks = <&osc24M>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&pwm_pin>; 979 #pwm-cells = <3>; 980 status = "disabled"; 981 }; 982 983 csi: csi@1cb0000 { 984 compatible = "allwinner,sun50i-a64-csi"; 985 reg = <0x01cb0000 0x1000>; 986 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&ccu CLK_BUS_CSI>, 988 <&ccu CLK_CSI_SCLK>, 989 <&ccu CLK_DRAM_CSI>; 990 clock-names = "bus", "mod", "ram"; 991 resets = <&ccu RST_BUS_CSI>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&csi_pins>; 994 status = "disabled"; 995 }; 996 997 hdmi: hdmi@1ee0000 { 998 compatible = "allwinner,sun50i-a64-dw-hdmi", 999 "allwinner,sun8i-a83t-dw-hdmi"; 1000 reg = <0x01ee0000 0x10000>; 1001 reg-io-width = <1>; 1002 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1004 <&ccu CLK_HDMI>; 1005 clock-names = "iahb", "isfr", "tmds"; 1006 resets = <&ccu RST_BUS_HDMI1>; 1007 reset-names = "ctrl"; 1008 phys = <&hdmi_phy>; 1009 phy-names = "phy"; 1010 status = "disabled"; 1011 1012 ports { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 1016 hdmi_in: port@0 { 1017 reg = <0>; 1018 1019 hdmi_in_tcon1: endpoint { 1020 remote-endpoint = <&tcon1_out_hdmi>; 1021 }; 1022 }; 1023 1024 hdmi_out: port@1 { 1025 reg = <1>; 1026 }; 1027 }; 1028 }; 1029 1030 hdmi_phy: hdmi-phy@1ef0000 { 1031 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1032 reg = <0x01ef0000 0x10000>; 1033 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1034 <&ccu 7>; 1035 clock-names = "bus", "mod", "pll-0"; 1036 resets = <&ccu RST_BUS_HDMI0>; 1037 reset-names = "phy"; 1038 #phy-cells = <0>; 1039 }; 1040 1041 rtc: rtc@1f00000 { 1042 compatible = "allwinner,sun50i-a64-rtc", 1043 "allwinner,sun8i-h3-rtc"; 1044 reg = <0x01f00000 0x400>; 1045 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1047 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1048 clocks = <&osc32k>; 1049 #clock-cells = <1>; 1050 }; 1051 1052 r_intc: interrupt-controller@1f00c00 { 1053 compatible = "allwinner,sun50i-a64-r-intc", 1054 "allwinner,sun6i-a31-r-intc"; 1055 interrupt-controller; 1056 #interrupt-cells = <2>; 1057 reg = <0x01f00c00 0x400>; 1058 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1059 }; 1060 1061 r_ccu: clock@1f01400 { 1062 compatible = "allwinner,sun50i-a64-r-ccu"; 1063 reg = <0x01f01400 0x100>; 1064 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1065 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1066 #clock-cells = <1>; 1067 #reset-cells = <1>; 1068 }; 1069 1070 codec_analog: codec-analog@1f015c0 { 1071 compatible = "allwinner,sun50i-a64-codec-analog"; 1072 reg = <0x01f015c0 0x4>; 1073 status = "disabled"; 1074 }; 1075 1076 r_i2c: i2c@1f02400 { 1077 compatible = "allwinner,sun50i-a64-i2c", 1078 "allwinner,sun6i-a31-i2c"; 1079 reg = <0x01f02400 0x400>; 1080 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&r_ccu CLK_APB0_I2C>; 1082 resets = <&r_ccu RST_APB0_I2C>; 1083 status = "disabled"; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 }; 1087 1088 r_ir: ir@1f02000 { 1089 compatible = "allwinner,sun50i-a64-ir", 1090 "allwinner,sun6i-a31-ir"; 1091 reg = <0x01f02000 0x400>; 1092 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1093 clock-names = "apb", "ir"; 1094 resets = <&r_ccu RST_APB0_IR>; 1095 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&r_ir_rx_pin>; 1098 status = "disabled"; 1099 }; 1100 1101 r_pwm: pwm@1f03800 { 1102 compatible = "allwinner,sun50i-a64-pwm", 1103 "allwinner,sun5i-a13-pwm"; 1104 reg = <0x01f03800 0x400>; 1105 clocks = <&osc24M>; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&r_pwm_pin>; 1108 #pwm-cells = <3>; 1109 status = "disabled"; 1110 }; 1111 1112 r_pio: pinctrl@1f02c00 { 1113 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1114 reg = <0x01f02c00 0x400>; 1115 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1117 clock-names = "apb", "hosc", "losc"; 1118 gpio-controller; 1119 #gpio-cells = <3>; 1120 interrupt-controller; 1121 #interrupt-cells = <3>; 1122 1123 r_i2c_pl89_pins: r-i2c-pl89-pins { 1124 pins = "PL8", "PL9"; 1125 function = "s_i2c"; 1126 }; 1127 1128 r_ir_rx_pin: r-ir-rx-pin { 1129 pins = "PL11"; 1130 function = "s_cir_rx"; 1131 }; 1132 1133 r_pwm_pin: r-pwm-pin { 1134 pins = "PL10"; 1135 function = "s_pwm"; 1136 }; 1137 1138 r_rsb_pins: r-rsb-pins { 1139 pins = "PL0", "PL1"; 1140 function = "s_rsb"; 1141 }; 1142 }; 1143 1144 r_rsb: rsb@1f03400 { 1145 compatible = "allwinner,sun8i-a23-rsb"; 1146 reg = <0x01f03400 0x400>; 1147 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&r_ccu 6>; 1149 clock-frequency = <3000000>; 1150 resets = <&r_ccu 2>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&r_rsb_pins>; 1153 status = "disabled"; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 }; 1157 1158 wdt0: watchdog@1c20ca0 { 1159 compatible = "allwinner,sun50i-a64-wdt", 1160 "allwinner,sun6i-a31-wdt"; 1161 reg = <0x01c20ca0 0x20>; 1162 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&osc24M>; 1164 }; 1165 }; 1166}; 1167