1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 145 iosc: internal-osc-clk { 146 #clock-cells = <0>; 147 compatible = "fixed-clock"; 148 clock-frequency = <16000000>; 149 clock-accuracy = <300000000>; 150 clock-output-names = "iosc"; 151 }; 152 153 psci { 154 compatible = "arm,psci-0.2"; 155 method = "smc"; 156 }; 157 158 sound: sound { 159 compatible = "simple-audio-card"; 160 simple-audio-card,name = "sun50i-a64-audio"; 161 simple-audio-card,format = "i2s"; 162 simple-audio-card,frame-master = <&cpudai>; 163 simple-audio-card,bitclock-master = <&cpudai>; 164 simple-audio-card,mclk-fs = <128>; 165 simple-audio-card,aux-devs = <&codec_analog>; 166 simple-audio-card,routing = 167 "Left DAC", "AIF1 Slot 0 Left", 168 "Right DAC", "AIF1 Slot 0 Right", 169 "AIF1 Slot 0 Left ADC", "Left ADC", 170 "AIF1 Slot 0 Right ADC", "Right ADC"; 171 status = "disabled"; 172 173 cpudai: simple-audio-card,cpu { 174 sound-dai = <&dai>; 175 }; 176 177 link_codec: simple-audio-card,codec { 178 sound-dai = <&codec>; 179 }; 180 }; 181 182 sound_spdif { 183 compatible = "simple-audio-card"; 184 simple-audio-card,name = "On-board SPDIF"; 185 186 simple-audio-card,cpu { 187 sound-dai = <&spdif>; 188 }; 189 190 simple-audio-card,codec { 191 sound-dai = <&spdif_out>; 192 }; 193 }; 194 195 spdif_out: spdif-out { 196 #sound-dai-cells = <0>; 197 compatible = "linux,spdif-dit"; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 203 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 204 <GIC_PPI 14 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 11 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 10 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 210 }; 211 212 soc { 213 compatible = "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 218 de2@1000000 { 219 compatible = "allwinner,sun50i-a64-de2"; 220 reg = <0x1000000 0x400000>; 221 allwinner,sram = <&de2_sram 1>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x1000000 0x400000>; 225 226 display_clocks: clock@0 { 227 compatible = "allwinner,sun50i-a64-de2-clk"; 228 reg = <0x0 0x100000>; 229 clocks = <&ccu CLK_DE>, 230 <&ccu CLK_BUS_DE>; 231 clock-names = "mod", 232 "bus"; 233 resets = <&ccu RST_BUS_DE>; 234 #clock-cells = <1>; 235 #reset-cells = <1>; 236 }; 237 238 mixer0: mixer@100000 { 239 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 240 reg = <0x100000 0x100000>; 241 clocks = <&display_clocks CLK_BUS_MIXER0>, 242 <&display_clocks CLK_MIXER0>; 243 clock-names = "bus", 244 "mod"; 245 resets = <&display_clocks RST_MIXER0>; 246 247 ports { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 mixer0_out: port@1 { 252 reg = <1>; 253 254 mixer0_out_tcon0: endpoint { 255 remote-endpoint = <&tcon0_in_mixer0>; 256 }; 257 }; 258 }; 259 }; 260 261 mixer1: mixer@200000 { 262 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 263 reg = <0x200000 0x100000>; 264 clocks = <&display_clocks CLK_BUS_MIXER1>, 265 <&display_clocks CLK_MIXER1>; 266 clock-names = "bus", 267 "mod"; 268 resets = <&display_clocks RST_MIXER1>; 269 270 ports { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 mixer1_out: port@1 { 275 reg = <1>; 276 277 mixer1_out_tcon1: endpoint { 278 remote-endpoint = <&tcon1_in_mixer1>; 279 }; 280 }; 281 }; 282 }; 283 }; 284 285 syscon: syscon@1c00000 { 286 compatible = "allwinner,sun50i-a64-system-control"; 287 reg = <0x01c00000 0x1000>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges; 291 292 sram_c: sram@18000 { 293 compatible = "mmio-sram"; 294 reg = <0x00018000 0x28000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0 0x00018000 0x28000>; 298 299 de2_sram: sram-section@0 { 300 compatible = "allwinner,sun50i-a64-sram-c"; 301 reg = <0x0000 0x28000>; 302 }; 303 }; 304 }; 305 306 dma: dma-controller@1c02000 { 307 compatible = "allwinner,sun50i-a64-dma"; 308 reg = <0x01c02000 0x1000>; 309 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&ccu CLK_BUS_DMA>; 311 dma-channels = <8>; 312 dma-requests = <27>; 313 resets = <&ccu RST_BUS_DMA>; 314 #dma-cells = <1>; 315 }; 316 317 tcon0: lcd-controller@1c0c000 { 318 compatible = "allwinner,sun50i-a64-tcon-lcd", 319 "allwinner,sun8i-a83t-tcon-lcd"; 320 reg = <0x01c0c000 0x1000>; 321 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 323 clock-names = "ahb", "tcon-ch0"; 324 clock-output-names = "tcon-pixel-clock"; 325 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 326 reset-names = "lcd", "lvds"; 327 328 ports { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 332 tcon0_in: port@0 { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <0>; 336 337 tcon0_in_mixer0: endpoint@0 { 338 reg = <0>; 339 remote-endpoint = <&mixer0_out_tcon0>; 340 }; 341 }; 342 343 tcon0_out: port@1 { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 reg = <1>; 347 }; 348 }; 349 }; 350 351 tcon1: lcd-controller@1c0d000 { 352 compatible = "allwinner,sun50i-a64-tcon-tv", 353 "allwinner,sun8i-a83t-tcon-tv"; 354 reg = <0x01c0d000 0x1000>; 355 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 357 clock-names = "ahb", "tcon-ch1"; 358 resets = <&ccu RST_BUS_TCON1>; 359 reset-names = "lcd"; 360 361 ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 tcon1_in: port@0 { 366 reg = <0>; 367 368 tcon1_in_mixer1: endpoint { 369 remote-endpoint = <&mixer1_out_tcon1>; 370 }; 371 }; 372 373 tcon1_out: port@1 { 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <1>; 377 378 tcon1_out_hdmi: endpoint@1 { 379 reg = <1>; 380 remote-endpoint = <&hdmi_in_tcon1>; 381 }; 382 }; 383 }; 384 }; 385 386 mmc0: mmc@1c0f000 { 387 compatible = "allwinner,sun50i-a64-mmc"; 388 reg = <0x01c0f000 0x1000>; 389 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 390 clock-names = "ahb", "mmc"; 391 resets = <&ccu RST_BUS_MMC0>; 392 reset-names = "ahb"; 393 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 394 max-frequency = <150000000>; 395 status = "disabled"; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 }; 399 400 mmc1: mmc@1c10000 { 401 compatible = "allwinner,sun50i-a64-mmc"; 402 reg = <0x01c10000 0x1000>; 403 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 404 clock-names = "ahb", "mmc"; 405 resets = <&ccu RST_BUS_MMC1>; 406 reset-names = "ahb"; 407 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 408 max-frequency = <150000000>; 409 status = "disabled"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 }; 413 414 mmc2: mmc@1c11000 { 415 compatible = "allwinner,sun50i-a64-emmc"; 416 reg = <0x01c11000 0x1000>; 417 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 418 clock-names = "ahb", "mmc"; 419 resets = <&ccu RST_BUS_MMC2>; 420 reset-names = "ahb"; 421 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 422 max-frequency = <200000000>; 423 status = "disabled"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 }; 427 428 sid: eeprom@1c14000 { 429 compatible = "allwinner,sun50i-a64-sid"; 430 reg = <0x1c14000 0x400>; 431 }; 432 433 usb_otg: usb@1c19000 { 434 compatible = "allwinner,sun8i-a33-musb"; 435 reg = <0x01c19000 0x0400>; 436 clocks = <&ccu CLK_BUS_OTG>; 437 resets = <&ccu RST_BUS_OTG>; 438 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 439 interrupt-names = "mc"; 440 phys = <&usbphy 0>; 441 phy-names = "usb"; 442 extcon = <&usbphy 0>; 443 status = "disabled"; 444 }; 445 446 usbphy: phy@1c19400 { 447 compatible = "allwinner,sun50i-a64-usb-phy"; 448 reg = <0x01c19400 0x14>, 449 <0x01c1a800 0x4>, 450 <0x01c1b800 0x4>; 451 reg-names = "phy_ctrl", 452 "pmu0", 453 "pmu1"; 454 clocks = <&ccu CLK_USB_PHY0>, 455 <&ccu CLK_USB_PHY1>; 456 clock-names = "usb0_phy", 457 "usb1_phy"; 458 resets = <&ccu RST_USB_PHY0>, 459 <&ccu RST_USB_PHY1>; 460 reset-names = "usb0_reset", 461 "usb1_reset"; 462 status = "disabled"; 463 #phy-cells = <1>; 464 }; 465 466 ehci0: usb@1c1a000 { 467 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 468 reg = <0x01c1a000 0x100>; 469 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&ccu CLK_BUS_OHCI0>, 471 <&ccu CLK_BUS_EHCI0>, 472 <&ccu CLK_USB_OHCI0>; 473 resets = <&ccu RST_BUS_OHCI0>, 474 <&ccu RST_BUS_EHCI0>; 475 status = "disabled"; 476 }; 477 478 ohci0: usb@1c1a400 { 479 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 480 reg = <0x01c1a400 0x100>; 481 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&ccu CLK_BUS_OHCI0>, 483 <&ccu CLK_USB_OHCI0>; 484 resets = <&ccu RST_BUS_OHCI0>; 485 status = "disabled"; 486 }; 487 488 ehci1: usb@1c1b000 { 489 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 490 reg = <0x01c1b000 0x100>; 491 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_OHCI1>, 493 <&ccu CLK_BUS_EHCI1>, 494 <&ccu CLK_USB_OHCI1>; 495 resets = <&ccu RST_BUS_OHCI1>, 496 <&ccu RST_BUS_EHCI1>; 497 phys = <&usbphy 1>; 498 phy-names = "usb"; 499 status = "disabled"; 500 }; 501 502 ohci1: usb@1c1b400 { 503 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 504 reg = <0x01c1b400 0x100>; 505 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&ccu CLK_BUS_OHCI1>, 507 <&ccu CLK_USB_OHCI1>; 508 resets = <&ccu RST_BUS_OHCI1>; 509 phys = <&usbphy 1>; 510 phy-names = "usb"; 511 status = "disabled"; 512 }; 513 514 ccu: clock@1c20000 { 515 compatible = "allwinner,sun50i-a64-ccu"; 516 reg = <0x01c20000 0x400>; 517 clocks = <&osc24M>, <&osc32k>; 518 clock-names = "hosc", "losc"; 519 #clock-cells = <1>; 520 #reset-cells = <1>; 521 }; 522 523 pio: pinctrl@1c20800 { 524 compatible = "allwinner,sun50i-a64-pinctrl"; 525 reg = <0x01c20800 0x400>; 526 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&ccu 58>; 530 gpio-controller; 531 #gpio-cells = <3>; 532 interrupt-controller; 533 #interrupt-cells = <3>; 534 535 i2c0_pins: i2c0_pins { 536 pins = "PH0", "PH1"; 537 function = "i2c0"; 538 }; 539 540 i2c1_pins: i2c1_pins { 541 pins = "PH2", "PH3"; 542 function = "i2c1"; 543 }; 544 545 mmc0_pins: mmc0-pins { 546 pins = "PF0", "PF1", "PF2", "PF3", 547 "PF4", "PF5"; 548 function = "mmc0"; 549 drive-strength = <30>; 550 bias-pull-up; 551 }; 552 553 mmc1_pins: mmc1-pins { 554 pins = "PG0", "PG1", "PG2", "PG3", 555 "PG4", "PG5"; 556 function = "mmc1"; 557 drive-strength = <30>; 558 bias-pull-up; 559 }; 560 561 mmc2_pins: mmc2-pins { 562 pins = "PC5", "PC6", "PC8", "PC9", 563 "PC10","PC11", "PC12", "PC13", 564 "PC14", "PC15", "PC16"; 565 function = "mmc2"; 566 drive-strength = <30>; 567 bias-pull-up; 568 }; 569 570 mmc2_ds_pin: mmc2-ds-pin { 571 pins = "PC1"; 572 function = "mmc2"; 573 drive-strength = <30>; 574 bias-pull-up; 575 }; 576 577 pwm_pin: pwm_pin { 578 pins = "PD22"; 579 function = "pwm"; 580 }; 581 582 rmii_pins: rmii_pins { 583 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 584 "PD18", "PD19", "PD20", "PD22", "PD23"; 585 function = "emac"; 586 drive-strength = <40>; 587 }; 588 589 rgmii_pins: rgmii_pins { 590 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 591 "PD13", "PD15", "PD16", "PD17", "PD18", 592 "PD19", "PD20", "PD21", "PD22", "PD23"; 593 function = "emac"; 594 drive-strength = <40>; 595 }; 596 597 spdif_tx_pin: spdif { 598 pins = "PH8"; 599 function = "spdif"; 600 }; 601 602 spi0_pins: spi0 { 603 pins = "PC0", "PC1", "PC2", "PC3"; 604 function = "spi0"; 605 }; 606 607 spi1_pins: spi1 { 608 pins = "PD0", "PD1", "PD2", "PD3"; 609 function = "spi1"; 610 }; 611 612 uart0_pb_pins: uart0-pb-pins { 613 pins = "PB8", "PB9"; 614 function = "uart0"; 615 }; 616 617 uart1_pins: uart1_pins { 618 pins = "PG6", "PG7"; 619 function = "uart1"; 620 }; 621 622 uart1_rts_cts_pins: uart1_rts_cts_pins { 623 pins = "PG8", "PG9"; 624 function = "uart1"; 625 }; 626 627 uart2_pins: uart2-pins { 628 pins = "PB0", "PB1"; 629 function = "uart2"; 630 }; 631 632 uart3_pins: uart3-pins { 633 pins = "PD0", "PD1"; 634 function = "uart3"; 635 }; 636 637 uart4_pins: uart4-pins { 638 pins = "PD2", "PD3"; 639 function = "uart4"; 640 }; 641 642 uart4_rts_cts_pins: uart4-rts-cts-pins { 643 pins = "PD4", "PD5"; 644 function = "uart4"; 645 }; 646 }; 647 648 spdif: spdif@1c21000 { 649 #sound-dai-cells = <0>; 650 compatible = "allwinner,sun50i-a64-spdif", 651 "allwinner,sun8i-h3-spdif"; 652 reg = <0x01c21000 0x400>; 653 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 655 resets = <&ccu RST_BUS_SPDIF>; 656 clock-names = "apb", "spdif"; 657 dmas = <&dma 2>; 658 dma-names = "tx"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&spdif_tx_pin>; 661 status = "disabled"; 662 }; 663 664 i2s0: i2s@1c22000 { 665 #sound-dai-cells = <0>; 666 compatible = "allwinner,sun50i-a64-i2s", 667 "allwinner,sun8i-h3-i2s"; 668 reg = <0x01c22000 0x400>; 669 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 671 clock-names = "apb", "mod"; 672 resets = <&ccu RST_BUS_I2S0>; 673 dma-names = "rx", "tx"; 674 dmas = <&dma 3>, <&dma 3>; 675 status = "disabled"; 676 }; 677 678 i2s1: i2s@1c22400 { 679 #sound-dai-cells = <0>; 680 compatible = "allwinner,sun50i-a64-i2s", 681 "allwinner,sun8i-h3-i2s"; 682 reg = <0x01c22400 0x400>; 683 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 685 clock-names = "apb", "mod"; 686 resets = <&ccu RST_BUS_I2S1>; 687 dma-names = "rx", "tx"; 688 dmas = <&dma 4>, <&dma 4>; 689 status = "disabled"; 690 }; 691 692 dai: dai@1c22c00 { 693 #sound-dai-cells = <0>; 694 compatible = "allwinner,sun50i-a64-codec-i2s"; 695 reg = <0x01c22c00 0x200>; 696 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 698 clock-names = "apb", "mod"; 699 resets = <&ccu RST_BUS_CODEC>; 700 reset-names = "rst"; 701 dmas = <&dma 15>, <&dma 15>; 702 dma-names = "rx", "tx"; 703 status = "disabled"; 704 }; 705 706 codec: codec@1c22e00 { 707 #sound-dai-cells = <0>; 708 compatible = "allwinner,sun8i-a33-codec"; 709 reg = <0x01c22e00 0x600>; 710 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 712 clock-names = "bus", "mod"; 713 status = "disabled"; 714 }; 715 716 uart0: serial@1c28000 { 717 compatible = "snps,dw-apb-uart"; 718 reg = <0x01c28000 0x400>; 719 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 720 reg-shift = <2>; 721 reg-io-width = <4>; 722 clocks = <&ccu CLK_BUS_UART0>; 723 resets = <&ccu RST_BUS_UART0>; 724 status = "disabled"; 725 }; 726 727 uart1: serial@1c28400 { 728 compatible = "snps,dw-apb-uart"; 729 reg = <0x01c28400 0x400>; 730 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 731 reg-shift = <2>; 732 reg-io-width = <4>; 733 clocks = <&ccu CLK_BUS_UART1>; 734 resets = <&ccu RST_BUS_UART1>; 735 status = "disabled"; 736 }; 737 738 uart2: serial@1c28800 { 739 compatible = "snps,dw-apb-uart"; 740 reg = <0x01c28800 0x400>; 741 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 742 reg-shift = <2>; 743 reg-io-width = <4>; 744 clocks = <&ccu CLK_BUS_UART2>; 745 resets = <&ccu RST_BUS_UART2>; 746 status = "disabled"; 747 }; 748 749 uart3: serial@1c28c00 { 750 compatible = "snps,dw-apb-uart"; 751 reg = <0x01c28c00 0x400>; 752 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 753 reg-shift = <2>; 754 reg-io-width = <4>; 755 clocks = <&ccu CLK_BUS_UART3>; 756 resets = <&ccu RST_BUS_UART3>; 757 status = "disabled"; 758 }; 759 760 uart4: serial@1c29000 { 761 compatible = "snps,dw-apb-uart"; 762 reg = <0x01c29000 0x400>; 763 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 764 reg-shift = <2>; 765 reg-io-width = <4>; 766 clocks = <&ccu CLK_BUS_UART4>; 767 resets = <&ccu RST_BUS_UART4>; 768 status = "disabled"; 769 }; 770 771 i2c0: i2c@1c2ac00 { 772 compatible = "allwinner,sun6i-a31-i2c"; 773 reg = <0x01c2ac00 0x400>; 774 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&ccu CLK_BUS_I2C0>; 776 resets = <&ccu RST_BUS_I2C0>; 777 status = "disabled"; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 }; 781 782 i2c1: i2c@1c2b000 { 783 compatible = "allwinner,sun6i-a31-i2c"; 784 reg = <0x01c2b000 0x400>; 785 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_I2C1>; 787 resets = <&ccu RST_BUS_I2C1>; 788 status = "disabled"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 }; 792 793 i2c2: i2c@1c2b400 { 794 compatible = "allwinner,sun6i-a31-i2c"; 795 reg = <0x01c2b400 0x400>; 796 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&ccu CLK_BUS_I2C2>; 798 resets = <&ccu RST_BUS_I2C2>; 799 status = "disabled"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 }; 803 804 805 spi0: spi@1c68000 { 806 compatible = "allwinner,sun8i-h3-spi"; 807 reg = <0x01c68000 0x1000>; 808 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 810 clock-names = "ahb", "mod"; 811 dmas = <&dma 23>, <&dma 23>; 812 dma-names = "rx", "tx"; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&spi0_pins>; 815 resets = <&ccu RST_BUS_SPI0>; 816 status = "disabled"; 817 num-cs = <1>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 }; 821 822 spi1: spi@1c69000 { 823 compatible = "allwinner,sun8i-h3-spi"; 824 reg = <0x01c69000 0x1000>; 825 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 827 clock-names = "ahb", "mod"; 828 dmas = <&dma 24>, <&dma 24>; 829 dma-names = "rx", "tx"; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&spi1_pins>; 832 resets = <&ccu RST_BUS_SPI1>; 833 status = "disabled"; 834 num-cs = <1>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 }; 838 839 emac: ethernet@1c30000 { 840 compatible = "allwinner,sun50i-a64-emac"; 841 syscon = <&syscon>; 842 reg = <0x01c30000 0x10000>; 843 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 844 interrupt-names = "macirq"; 845 resets = <&ccu RST_BUS_EMAC>; 846 reset-names = "stmmaceth"; 847 clocks = <&ccu CLK_BUS_EMAC>; 848 clock-names = "stmmaceth"; 849 status = "disabled"; 850 851 mdio: mdio { 852 compatible = "snps,dwmac-mdio"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 }; 856 }; 857 858 mali: gpu@1c40000 { 859 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 860 reg = <0x01c40000 0x10000>; 861 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "gp", 869 "gpmmu", 870 "pp0", 871 "ppmmu0", 872 "pp1", 873 "ppmmu1", 874 "pmu"; 875 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 876 clock-names = "bus", "core"; 877 resets = <&ccu RST_BUS_GPU>; 878 }; 879 880 gic: interrupt-controller@1c81000 { 881 compatible = "arm,gic-400"; 882 reg = <0x01c81000 0x1000>, 883 <0x01c82000 0x2000>, 884 <0x01c84000 0x2000>, 885 <0x01c86000 0x2000>; 886 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 887 interrupt-controller; 888 #interrupt-cells = <3>; 889 }; 890 891 pwm: pwm@1c21400 { 892 compatible = "allwinner,sun50i-a64-pwm", 893 "allwinner,sun5i-a13-pwm"; 894 reg = <0x01c21400 0x400>; 895 clocks = <&osc24M>; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&pwm_pin>; 898 #pwm-cells = <3>; 899 status = "disabled"; 900 }; 901 902 hdmi: hdmi@1ee0000 { 903 compatible = "allwinner,sun50i-a64-dw-hdmi", 904 "allwinner,sun8i-a83t-dw-hdmi"; 905 reg = <0x01ee0000 0x10000>; 906 reg-io-width = <1>; 907 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 909 <&ccu CLK_HDMI>; 910 clock-names = "iahb", "isfr", "tmds"; 911 resets = <&ccu RST_BUS_HDMI1>; 912 reset-names = "ctrl"; 913 phys = <&hdmi_phy>; 914 phy-names = "hdmi-phy"; 915 status = "disabled"; 916 917 ports { 918 #address-cells = <1>; 919 #size-cells = <0>; 920 921 hdmi_in: port@0 { 922 reg = <0>; 923 924 hdmi_in_tcon1: endpoint { 925 remote-endpoint = <&tcon1_out_hdmi>; 926 }; 927 }; 928 929 hdmi_out: port@1 { 930 reg = <1>; 931 }; 932 }; 933 }; 934 935 hdmi_phy: hdmi-phy@1ef0000 { 936 compatible = "allwinner,sun50i-a64-hdmi-phy"; 937 reg = <0x01ef0000 0x10000>; 938 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 939 <&ccu 7>; 940 clock-names = "bus", "mod", "pll-0"; 941 resets = <&ccu RST_BUS_HDMI0>; 942 reset-names = "phy"; 943 #phy-cells = <0>; 944 }; 945 946 rtc: rtc@1f00000 { 947 compatible = "allwinner,sun6i-a31-rtc"; 948 reg = <0x01f00000 0x54>; 949 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 951 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 952 clocks = <&osc32k>; 953 #clock-cells = <1>; 954 }; 955 956 r_intc: interrupt-controller@1f00c00 { 957 compatible = "allwinner,sun50i-a64-r-intc", 958 "allwinner,sun6i-a31-r-intc"; 959 interrupt-controller; 960 #interrupt-cells = <2>; 961 reg = <0x01f00c00 0x400>; 962 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 963 }; 964 965 r_ccu: clock@1f01400 { 966 compatible = "allwinner,sun50i-a64-r-ccu"; 967 reg = <0x01f01400 0x100>; 968 clocks = <&osc24M>, <&osc32k>, <&iosc>, 969 <&ccu 11>; 970 clock-names = "hosc", "losc", "iosc", "pll-periph"; 971 #clock-cells = <1>; 972 #reset-cells = <1>; 973 }; 974 975 codec_analog: codec-analog@1f015c0 { 976 compatible = "allwinner,sun50i-a64-codec-analog"; 977 reg = <0x01f015c0 0x4>; 978 status = "disabled"; 979 }; 980 981 r_i2c: i2c@1f02400 { 982 compatible = "allwinner,sun50i-a64-i2c", 983 "allwinner,sun6i-a31-i2c"; 984 reg = <0x01f02400 0x400>; 985 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&r_ccu CLK_APB0_I2C>; 987 resets = <&r_ccu RST_APB0_I2C>; 988 status = "disabled"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 }; 992 993 r_pwm: pwm@1f03800 { 994 compatible = "allwinner,sun50i-a64-pwm", 995 "allwinner,sun5i-a13-pwm"; 996 reg = <0x01f03800 0x400>; 997 clocks = <&osc24M>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&r_pwm_pin>; 1000 #pwm-cells = <3>; 1001 status = "disabled"; 1002 }; 1003 1004 r_pio: pinctrl@1f02c00 { 1005 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1006 reg = <0x01f02c00 0x400>; 1007 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1009 clock-names = "apb", "hosc", "losc"; 1010 gpio-controller; 1011 #gpio-cells = <3>; 1012 interrupt-controller; 1013 #interrupt-cells = <3>; 1014 1015 r_i2c_pl89_pins: r-i2c-pl89-pins { 1016 pins = "PL8", "PL9"; 1017 function = "s_i2c"; 1018 }; 1019 1020 r_pwm_pin: pwm { 1021 pins = "PL10"; 1022 function = "s_pwm"; 1023 }; 1024 1025 r_rsb_pins: rsb { 1026 pins = "PL0", "PL1"; 1027 function = "s_rsb"; 1028 }; 1029 }; 1030 1031 r_rsb: rsb@1f03400 { 1032 compatible = "allwinner,sun8i-a23-rsb"; 1033 reg = <0x01f03400 0x400>; 1034 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&r_ccu 6>; 1036 clock-frequency = <3000000>; 1037 resets = <&r_ccu 2>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&r_rsb_pins>; 1040 status = "disabled"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 }; 1044 1045 wdt0: watchdog@1c20ca0 { 1046 compatible = "allwinner,sun50i-a64-wdt", 1047 "allwinner,sun6i-a31-wdt"; 1048 reg = <0x01c20ca0 0x20>; 1049 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1050 }; 1051 }; 1052}; 1053