1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 145 iosc: internal-osc-clk { 146 #clock-cells = <0>; 147 compatible = "fixed-clock"; 148 clock-frequency = <16000000>; 149 clock-accuracy = <300000000>; 150 clock-output-names = "iosc"; 151 }; 152 153 psci { 154 compatible = "arm,psci-0.2"; 155 method = "smc"; 156 }; 157 158 sound_spdif { 159 compatible = "simple-audio-card"; 160 simple-audio-card,name = "On-board SPDIF"; 161 162 simple-audio-card,cpu { 163 sound-dai = <&spdif>; 164 }; 165 166 simple-audio-card,codec { 167 sound-dai = <&spdif_out>; 168 }; 169 }; 170 171 spdif_out: spdif-out { 172 #sound-dai-cells = <0>; 173 compatible = "linux,spdif-dit"; 174 }; 175 176 timer { 177 compatible = "arm,armv8-timer"; 178 interrupts = <GIC_PPI 13 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 180 <GIC_PPI 14 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 182 <GIC_PPI 11 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 10 185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 soc { 189 compatible = "simple-bus"; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 ranges; 193 194 de2@1000000 { 195 compatible = "allwinner,sun50i-a64-de2"; 196 reg = <0x1000000 0x400000>; 197 allwinner,sram = <&de2_sram 1>; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0 0x1000000 0x400000>; 201 202 display_clocks: clock@0 { 203 compatible = "allwinner,sun50i-a64-de2-clk"; 204 reg = <0x0 0x100000>; 205 clocks = <&ccu CLK_DE>, 206 <&ccu CLK_BUS_DE>; 207 clock-names = "mod", 208 "bus"; 209 resets = <&ccu RST_BUS_DE>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 }; 213 214 mixer0: mixer@100000 { 215 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 216 reg = <0x100000 0x100000>; 217 clocks = <&display_clocks CLK_BUS_MIXER0>, 218 <&display_clocks CLK_MIXER0>; 219 clock-names = "bus", 220 "mod"; 221 resets = <&display_clocks RST_MIXER0>; 222 223 ports { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 mixer0_out: port@1 { 228 reg = <1>; 229 230 mixer0_out_tcon0: endpoint { 231 remote-endpoint = <&tcon0_in_mixer0>; 232 }; 233 }; 234 }; 235 }; 236 237 mixer1: mixer@200000 { 238 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 239 reg = <0x200000 0x100000>; 240 clocks = <&display_clocks CLK_BUS_MIXER1>, 241 <&display_clocks CLK_MIXER1>; 242 clock-names = "bus", 243 "mod"; 244 resets = <&display_clocks RST_MIXER1>; 245 246 ports { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 250 mixer1_out: port@1 { 251 reg = <1>; 252 253 mixer1_out_tcon1: endpoint { 254 remote-endpoint = <&tcon1_in_mixer1>; 255 }; 256 }; 257 }; 258 }; 259 }; 260 261 syscon: syscon@1c00000 { 262 compatible = "allwinner,sun50i-a64-system-control"; 263 reg = <0x01c00000 0x1000>; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges; 267 268 sram_c: sram@18000 { 269 compatible = "mmio-sram"; 270 reg = <0x00018000 0x28000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges = <0 0x00018000 0x28000>; 274 275 de2_sram: sram-section@0 { 276 compatible = "allwinner,sun50i-a64-sram-c"; 277 reg = <0x0000 0x28000>; 278 }; 279 }; 280 }; 281 282 dma: dma-controller@1c02000 { 283 compatible = "allwinner,sun50i-a64-dma"; 284 reg = <0x01c02000 0x1000>; 285 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&ccu CLK_BUS_DMA>; 287 dma-channels = <8>; 288 dma-requests = <27>; 289 resets = <&ccu RST_BUS_DMA>; 290 #dma-cells = <1>; 291 }; 292 293 tcon0: lcd-controller@1c0c000 { 294 compatible = "allwinner,sun50i-a64-tcon-lcd", 295 "allwinner,sun8i-a83t-tcon-lcd"; 296 reg = <0x01c0c000 0x1000>; 297 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 299 clock-names = "ahb", "tcon-ch0"; 300 clock-output-names = "tcon-pixel-clock"; 301 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 302 reset-names = "lcd", "lvds"; 303 304 ports { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 tcon0_in: port@0 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <0>; 312 313 tcon0_in_mixer0: endpoint@0 { 314 reg = <0>; 315 remote-endpoint = <&mixer0_out_tcon0>; 316 }; 317 }; 318 319 tcon0_out: port@1 { 320 #address-cells = <1>; 321 #size-cells = <0>; 322 reg = <1>; 323 }; 324 }; 325 }; 326 327 tcon1: lcd-controller@1c0d000 { 328 compatible = "allwinner,sun50i-a64-tcon-tv", 329 "allwinner,sun8i-a83t-tcon-tv"; 330 reg = <0x01c0d000 0x1000>; 331 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 333 clock-names = "ahb", "tcon-ch1"; 334 resets = <&ccu RST_BUS_TCON1>; 335 reset-names = "lcd"; 336 337 ports { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 341 tcon1_in: port@0 { 342 reg = <0>; 343 344 tcon1_in_mixer1: endpoint { 345 remote-endpoint = <&mixer1_out_tcon1>; 346 }; 347 }; 348 349 tcon1_out: port@1 { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <1>; 353 354 tcon1_out_hdmi: endpoint@1 { 355 reg = <1>; 356 remote-endpoint = <&hdmi_in_tcon1>; 357 }; 358 }; 359 }; 360 }; 361 362 mmc0: mmc@1c0f000 { 363 compatible = "allwinner,sun50i-a64-mmc"; 364 reg = <0x01c0f000 0x1000>; 365 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 366 clock-names = "ahb", "mmc"; 367 resets = <&ccu RST_BUS_MMC0>; 368 reset-names = "ahb"; 369 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 370 max-frequency = <150000000>; 371 status = "disabled"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 }; 375 376 mmc1: mmc@1c10000 { 377 compatible = "allwinner,sun50i-a64-mmc"; 378 reg = <0x01c10000 0x1000>; 379 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 380 clock-names = "ahb", "mmc"; 381 resets = <&ccu RST_BUS_MMC1>; 382 reset-names = "ahb"; 383 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 384 max-frequency = <150000000>; 385 status = "disabled"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 }; 389 390 mmc2: mmc@1c11000 { 391 compatible = "allwinner,sun50i-a64-emmc"; 392 reg = <0x01c11000 0x1000>; 393 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 394 clock-names = "ahb", "mmc"; 395 resets = <&ccu RST_BUS_MMC2>; 396 reset-names = "ahb"; 397 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 398 max-frequency = <200000000>; 399 status = "disabled"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 }; 403 404 sid: eeprom@1c14000 { 405 compatible = "allwinner,sun50i-a64-sid"; 406 reg = <0x1c14000 0x400>; 407 }; 408 409 usb_otg: usb@1c19000 { 410 compatible = "allwinner,sun8i-a33-musb"; 411 reg = <0x01c19000 0x0400>; 412 clocks = <&ccu CLK_BUS_OTG>; 413 resets = <&ccu RST_BUS_OTG>; 414 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "mc"; 416 phys = <&usbphy 0>; 417 phy-names = "usb"; 418 extcon = <&usbphy 0>; 419 status = "disabled"; 420 }; 421 422 usbphy: phy@1c19400 { 423 compatible = "allwinner,sun50i-a64-usb-phy"; 424 reg = <0x01c19400 0x14>, 425 <0x01c1a800 0x4>, 426 <0x01c1b800 0x4>; 427 reg-names = "phy_ctrl", 428 "pmu0", 429 "pmu1"; 430 clocks = <&ccu CLK_USB_PHY0>, 431 <&ccu CLK_USB_PHY1>; 432 clock-names = "usb0_phy", 433 "usb1_phy"; 434 resets = <&ccu RST_USB_PHY0>, 435 <&ccu RST_USB_PHY1>; 436 reset-names = "usb0_reset", 437 "usb1_reset"; 438 status = "disabled"; 439 #phy-cells = <1>; 440 }; 441 442 ehci0: usb@1c1a000 { 443 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 444 reg = <0x01c1a000 0x100>; 445 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&ccu CLK_BUS_OHCI0>, 447 <&ccu CLK_BUS_EHCI0>, 448 <&ccu CLK_USB_OHCI0>; 449 resets = <&ccu RST_BUS_OHCI0>, 450 <&ccu RST_BUS_EHCI0>; 451 status = "disabled"; 452 }; 453 454 ohci0: usb@1c1a400 { 455 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 456 reg = <0x01c1a400 0x100>; 457 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&ccu CLK_BUS_OHCI0>, 459 <&ccu CLK_USB_OHCI0>; 460 resets = <&ccu RST_BUS_OHCI0>; 461 status = "disabled"; 462 }; 463 464 ehci1: usb@1c1b000 { 465 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 466 reg = <0x01c1b000 0x100>; 467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&ccu CLK_BUS_OHCI1>, 469 <&ccu CLK_BUS_EHCI1>, 470 <&ccu CLK_USB_OHCI1>; 471 resets = <&ccu RST_BUS_OHCI1>, 472 <&ccu RST_BUS_EHCI1>; 473 phys = <&usbphy 1>; 474 phy-names = "usb"; 475 status = "disabled"; 476 }; 477 478 ohci1: usb@1c1b400 { 479 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 480 reg = <0x01c1b400 0x100>; 481 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&ccu CLK_BUS_OHCI1>, 483 <&ccu CLK_USB_OHCI1>; 484 resets = <&ccu RST_BUS_OHCI1>; 485 phys = <&usbphy 1>; 486 phy-names = "usb"; 487 status = "disabled"; 488 }; 489 490 ccu: clock@1c20000 { 491 compatible = "allwinner,sun50i-a64-ccu"; 492 reg = <0x01c20000 0x400>; 493 clocks = <&osc24M>, <&osc32k>; 494 clock-names = "hosc", "losc"; 495 #clock-cells = <1>; 496 #reset-cells = <1>; 497 }; 498 499 pio: pinctrl@1c20800 { 500 compatible = "allwinner,sun50i-a64-pinctrl"; 501 reg = <0x01c20800 0x400>; 502 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&ccu 58>; 506 gpio-controller; 507 #gpio-cells = <3>; 508 interrupt-controller; 509 #interrupt-cells = <3>; 510 511 i2c0_pins: i2c0_pins { 512 pins = "PH0", "PH1"; 513 function = "i2c0"; 514 }; 515 516 i2c1_pins: i2c1_pins { 517 pins = "PH2", "PH3"; 518 function = "i2c1"; 519 }; 520 521 mmc0_pins: mmc0-pins { 522 pins = "PF0", "PF1", "PF2", "PF3", 523 "PF4", "PF5"; 524 function = "mmc0"; 525 drive-strength = <30>; 526 bias-pull-up; 527 }; 528 529 mmc1_pins: mmc1-pins { 530 pins = "PG0", "PG1", "PG2", "PG3", 531 "PG4", "PG5"; 532 function = "mmc1"; 533 drive-strength = <30>; 534 bias-pull-up; 535 }; 536 537 mmc2_pins: mmc2-pins { 538 pins = "PC5", "PC6", "PC8", "PC9", 539 "PC10","PC11", "PC12", "PC13", 540 "PC14", "PC15", "PC16"; 541 function = "mmc2"; 542 drive-strength = <30>; 543 bias-pull-up; 544 }; 545 546 mmc2_ds_pin: mmc2-ds-pin { 547 pins = "PC1"; 548 function = "mmc2"; 549 drive-strength = <30>; 550 bias-pull-up; 551 }; 552 553 pwm_pin: pwm_pin { 554 pins = "PD22"; 555 function = "pwm"; 556 }; 557 558 rmii_pins: rmii_pins { 559 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 560 "PD18", "PD19", "PD20", "PD22", "PD23"; 561 function = "emac"; 562 drive-strength = <40>; 563 }; 564 565 rgmii_pins: rgmii_pins { 566 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 567 "PD13", "PD15", "PD16", "PD17", "PD18", 568 "PD19", "PD20", "PD21", "PD22", "PD23"; 569 function = "emac"; 570 drive-strength = <40>; 571 }; 572 573 spdif_tx_pin: spdif { 574 pins = "PH8"; 575 function = "spdif"; 576 }; 577 578 spi0_pins: spi0 { 579 pins = "PC0", "PC1", "PC2", "PC3"; 580 function = "spi0"; 581 }; 582 583 spi1_pins: spi1 { 584 pins = "PD0", "PD1", "PD2", "PD3"; 585 function = "spi1"; 586 }; 587 588 uart0_pb_pins: uart0-pb-pins { 589 pins = "PB8", "PB9"; 590 function = "uart0"; 591 }; 592 593 uart1_pins: uart1_pins { 594 pins = "PG6", "PG7"; 595 function = "uart1"; 596 }; 597 598 uart1_rts_cts_pins: uart1_rts_cts_pins { 599 pins = "PG8", "PG9"; 600 function = "uart1"; 601 }; 602 603 uart2_pins: uart2-pins { 604 pins = "PB0", "PB1"; 605 function = "uart2"; 606 }; 607 608 uart3_pins: uart3-pins { 609 pins = "PD0", "PD1"; 610 function = "uart3"; 611 }; 612 613 uart4_pins: uart4-pins { 614 pins = "PD2", "PD3"; 615 function = "uart4"; 616 }; 617 618 uart4_rts_cts_pins: uart4-rts-cts-pins { 619 pins = "PD4", "PD5"; 620 function = "uart4"; 621 }; 622 }; 623 624 spdif: spdif@1c21000 { 625 #sound-dai-cells = <0>; 626 compatible = "allwinner,sun50i-a64-spdif", 627 "allwinner,sun8i-h3-spdif"; 628 reg = <0x01c21000 0x400>; 629 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 631 resets = <&ccu RST_BUS_SPDIF>; 632 clock-names = "apb", "spdif"; 633 dmas = <&dma 2>; 634 dma-names = "tx"; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&spdif_tx_pin>; 637 status = "disabled"; 638 }; 639 640 i2s0: i2s@1c22000 { 641 #sound-dai-cells = <0>; 642 compatible = "allwinner,sun50i-a64-i2s", 643 "allwinner,sun8i-h3-i2s"; 644 reg = <0x01c22000 0x400>; 645 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 647 clock-names = "apb", "mod"; 648 resets = <&ccu RST_BUS_I2S0>; 649 dma-names = "rx", "tx"; 650 dmas = <&dma 3>, <&dma 3>; 651 status = "disabled"; 652 }; 653 654 i2s1: i2s@1c22400 { 655 #sound-dai-cells = <0>; 656 compatible = "allwinner,sun50i-a64-i2s", 657 "allwinner,sun8i-h3-i2s"; 658 reg = <0x01c22400 0x400>; 659 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 661 clock-names = "apb", "mod"; 662 resets = <&ccu RST_BUS_I2S1>; 663 dma-names = "rx", "tx"; 664 dmas = <&dma 4>, <&dma 4>; 665 status = "disabled"; 666 }; 667 668 uart0: serial@1c28000 { 669 compatible = "snps,dw-apb-uart"; 670 reg = <0x01c28000 0x400>; 671 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 672 reg-shift = <2>; 673 reg-io-width = <4>; 674 clocks = <&ccu CLK_BUS_UART0>; 675 resets = <&ccu RST_BUS_UART0>; 676 status = "disabled"; 677 }; 678 679 uart1: serial@1c28400 { 680 compatible = "snps,dw-apb-uart"; 681 reg = <0x01c28400 0x400>; 682 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 683 reg-shift = <2>; 684 reg-io-width = <4>; 685 clocks = <&ccu CLK_BUS_UART1>; 686 resets = <&ccu RST_BUS_UART1>; 687 status = "disabled"; 688 }; 689 690 uart2: serial@1c28800 { 691 compatible = "snps,dw-apb-uart"; 692 reg = <0x01c28800 0x400>; 693 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 694 reg-shift = <2>; 695 reg-io-width = <4>; 696 clocks = <&ccu CLK_BUS_UART2>; 697 resets = <&ccu RST_BUS_UART2>; 698 status = "disabled"; 699 }; 700 701 uart3: serial@1c28c00 { 702 compatible = "snps,dw-apb-uart"; 703 reg = <0x01c28c00 0x400>; 704 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 705 reg-shift = <2>; 706 reg-io-width = <4>; 707 clocks = <&ccu CLK_BUS_UART3>; 708 resets = <&ccu RST_BUS_UART3>; 709 status = "disabled"; 710 }; 711 712 uart4: serial@1c29000 { 713 compatible = "snps,dw-apb-uart"; 714 reg = <0x01c29000 0x400>; 715 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 716 reg-shift = <2>; 717 reg-io-width = <4>; 718 clocks = <&ccu CLK_BUS_UART4>; 719 resets = <&ccu RST_BUS_UART4>; 720 status = "disabled"; 721 }; 722 723 i2c0: i2c@1c2ac00 { 724 compatible = "allwinner,sun6i-a31-i2c"; 725 reg = <0x01c2ac00 0x400>; 726 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&ccu CLK_BUS_I2C0>; 728 resets = <&ccu RST_BUS_I2C0>; 729 status = "disabled"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 }; 733 734 i2c1: i2c@1c2b000 { 735 compatible = "allwinner,sun6i-a31-i2c"; 736 reg = <0x01c2b000 0x400>; 737 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&ccu CLK_BUS_I2C1>; 739 resets = <&ccu RST_BUS_I2C1>; 740 status = "disabled"; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 }; 744 745 i2c2: i2c@1c2b400 { 746 compatible = "allwinner,sun6i-a31-i2c"; 747 reg = <0x01c2b400 0x400>; 748 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&ccu CLK_BUS_I2C2>; 750 resets = <&ccu RST_BUS_I2C2>; 751 status = "disabled"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 }; 755 756 757 spi0: spi@1c68000 { 758 compatible = "allwinner,sun8i-h3-spi"; 759 reg = <0x01c68000 0x1000>; 760 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 762 clock-names = "ahb", "mod"; 763 dmas = <&dma 23>, <&dma 23>; 764 dma-names = "rx", "tx"; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&spi0_pins>; 767 resets = <&ccu RST_BUS_SPI0>; 768 status = "disabled"; 769 num-cs = <1>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 }; 773 774 spi1: spi@1c69000 { 775 compatible = "allwinner,sun8i-h3-spi"; 776 reg = <0x01c69000 0x1000>; 777 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 779 clock-names = "ahb", "mod"; 780 dmas = <&dma 24>, <&dma 24>; 781 dma-names = "rx", "tx"; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&spi1_pins>; 784 resets = <&ccu RST_BUS_SPI1>; 785 status = "disabled"; 786 num-cs = <1>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 }; 790 791 emac: ethernet@1c30000 { 792 compatible = "allwinner,sun50i-a64-emac"; 793 syscon = <&syscon>; 794 reg = <0x01c30000 0x10000>; 795 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 796 interrupt-names = "macirq"; 797 resets = <&ccu RST_BUS_EMAC>; 798 reset-names = "stmmaceth"; 799 clocks = <&ccu CLK_BUS_EMAC>; 800 clock-names = "stmmaceth"; 801 status = "disabled"; 802 803 mdio: mdio { 804 compatible = "snps,dwmac-mdio"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 }; 808 }; 809 810 gic: interrupt-controller@1c81000 { 811 compatible = "arm,gic-400"; 812 reg = <0x01c81000 0x1000>, 813 <0x01c82000 0x2000>, 814 <0x01c84000 0x2000>, 815 <0x01c86000 0x2000>; 816 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 817 interrupt-controller; 818 #interrupt-cells = <3>; 819 }; 820 821 pwm: pwm@1c21400 { 822 compatible = "allwinner,sun50i-a64-pwm", 823 "allwinner,sun5i-a13-pwm"; 824 reg = <0x01c21400 0x400>; 825 clocks = <&osc24M>; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&pwm_pin>; 828 #pwm-cells = <3>; 829 status = "disabled"; 830 }; 831 832 hdmi: hdmi@1ee0000 { 833 compatible = "allwinner,sun50i-a64-dw-hdmi", 834 "allwinner,sun8i-a83t-dw-hdmi"; 835 reg = <0x01ee0000 0x10000>; 836 reg-io-width = <1>; 837 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 839 <&ccu CLK_HDMI>; 840 clock-names = "iahb", "isfr", "tmds"; 841 resets = <&ccu RST_BUS_HDMI1>; 842 reset-names = "ctrl"; 843 phys = <&hdmi_phy>; 844 phy-names = "hdmi-phy"; 845 status = "disabled"; 846 847 ports { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 851 hdmi_in: port@0 { 852 reg = <0>; 853 854 hdmi_in_tcon1: endpoint { 855 remote-endpoint = <&tcon1_out_hdmi>; 856 }; 857 }; 858 859 hdmi_out: port@1 { 860 reg = <1>; 861 }; 862 }; 863 }; 864 865 hdmi_phy: hdmi-phy@1ef0000 { 866 compatible = "allwinner,sun50i-a64-hdmi-phy"; 867 reg = <0x01ef0000 0x10000>; 868 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 869 <&ccu 7>; 870 clock-names = "bus", "mod", "pll-0"; 871 resets = <&ccu RST_BUS_HDMI0>; 872 reset-names = "phy"; 873 #phy-cells = <0>; 874 }; 875 876 rtc: rtc@1f00000 { 877 compatible = "allwinner,sun6i-a31-rtc"; 878 reg = <0x01f00000 0x54>; 879 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 881 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 882 clocks = <&osc32k>; 883 #clock-cells = <1>; 884 }; 885 886 r_intc: interrupt-controller@1f00c00 { 887 compatible = "allwinner,sun50i-a64-r-intc", 888 "allwinner,sun6i-a31-r-intc"; 889 interrupt-controller; 890 #interrupt-cells = <2>; 891 reg = <0x01f00c00 0x400>; 892 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 893 }; 894 895 r_ccu: clock@1f01400 { 896 compatible = "allwinner,sun50i-a64-r-ccu"; 897 reg = <0x01f01400 0x100>; 898 clocks = <&osc24M>, <&osc32k>, <&iosc>, 899 <&ccu 11>; 900 clock-names = "hosc", "losc", "iosc", "pll-periph"; 901 #clock-cells = <1>; 902 #reset-cells = <1>; 903 }; 904 905 r_i2c: i2c@1f02400 { 906 compatible = "allwinner,sun50i-a64-i2c", 907 "allwinner,sun6i-a31-i2c"; 908 reg = <0x01f02400 0x400>; 909 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&r_ccu CLK_APB0_I2C>; 911 resets = <&r_ccu RST_APB0_I2C>; 912 status = "disabled"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 }; 916 917 r_pwm: pwm@1f03800 { 918 compatible = "allwinner,sun50i-a64-pwm", 919 "allwinner,sun5i-a13-pwm"; 920 reg = <0x01f03800 0x400>; 921 clocks = <&osc24M>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&r_pwm_pin>; 924 #pwm-cells = <3>; 925 status = "disabled"; 926 }; 927 928 r_pio: pinctrl@1f02c00 { 929 compatible = "allwinner,sun50i-a64-r-pinctrl"; 930 reg = <0x01f02c00 0x400>; 931 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 933 clock-names = "apb", "hosc", "losc"; 934 gpio-controller; 935 #gpio-cells = <3>; 936 interrupt-controller; 937 #interrupt-cells = <3>; 938 939 r_i2c_pl89_pins: r-i2c-pl89-pins { 940 pins = "PL8", "PL9"; 941 function = "s_i2c"; 942 }; 943 944 r_pwm_pin: pwm { 945 pins = "PL10"; 946 function = "s_pwm"; 947 }; 948 949 r_rsb_pins: rsb { 950 pins = "PL0", "PL1"; 951 function = "s_rsb"; 952 }; 953 }; 954 955 r_rsb: rsb@1f03400 { 956 compatible = "allwinner,sun8i-a23-rsb"; 957 reg = <0x01f03400 0x400>; 958 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&r_ccu 6>; 960 clock-frequency = <3000000>; 961 resets = <&r_ccu 2>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&r_rsb_pins>; 964 status = "disabled"; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 }; 968 969 wdt0: watchdog@1c20ca0 { 970 compatible = "allwinner,sun50i-a64-wdt", 971 "allwinner,sun6i-a31-wdt"; 972 reg = <0x01c20ca0 0x20>; 973 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 974 }; 975 }; 976}; 977