1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 bus@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_BUS_DE>, 232 <&ccu CLK_DE>; 233 clock-names = "bus", 234 "mod"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <1>; 257 258 mixer0_out_tcon0: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&tcon0_in_mixer0>; 261 }; 262 263 mixer0_out_tcon1: endpoint@1 { 264 reg = <1>; 265 remote-endpoint = <&tcon1_in_mixer0>; 266 }; 267 }; 268 }; 269 }; 270 271 mixer1: mixer@200000 { 272 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273 reg = <0x200000 0x100000>; 274 clocks = <&display_clocks CLK_BUS_MIXER1>, 275 <&display_clocks CLK_MIXER1>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&display_clocks RST_MIXER1>; 279 280 ports { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 mixer1_out: port@1 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <1>; 288 289 mixer1_out_tcon0: endpoint@0 { 290 reg = <0>; 291 remote-endpoint = <&tcon0_in_mixer1>; 292 }; 293 294 mixer1_out_tcon1: endpoint@1 { 295 reg = <1>; 296 remote-endpoint = <&tcon1_in_mixer1>; 297 }; 298 }; 299 }; 300 }; 301 }; 302 303 syscon: syscon@1c00000 { 304 compatible = "allwinner,sun50i-a64-system-control"; 305 reg = <0x01c00000 0x1000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges; 309 310 sram_c: sram@18000 { 311 compatible = "mmio-sram"; 312 reg = <0x00018000 0x28000>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0 0x00018000 0x28000>; 316 317 de2_sram: sram-section@0 { 318 compatible = "allwinner,sun50i-a64-sram-c"; 319 reg = <0x0000 0x28000>; 320 }; 321 }; 322 323 sram_c1: sram@1d00000 { 324 compatible = "mmio-sram"; 325 reg = <0x01d00000 0x40000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0 0x01d00000 0x40000>; 329 330 ve_sram: sram-section@0 { 331 compatible = "allwinner,sun50i-a64-sram-c1", 332 "allwinner,sun4i-a10-sram-c1"; 333 reg = <0x000000 0x40000>; 334 }; 335 }; 336 }; 337 338 dma: dma-controller@1c02000 { 339 compatible = "allwinner,sun50i-a64-dma"; 340 reg = <0x01c02000 0x1000>; 341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&ccu CLK_BUS_DMA>; 343 dma-channels = <8>; 344 dma-requests = <27>; 345 resets = <&ccu RST_BUS_DMA>; 346 #dma-cells = <1>; 347 }; 348 349 tcon0: lcd-controller@1c0c000 { 350 compatible = "allwinner,sun50i-a64-tcon-lcd", 351 "allwinner,sun8i-a83t-tcon-lcd"; 352 reg = <0x01c0c000 0x1000>; 353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 355 clock-names = "ahb", "tcon-ch0"; 356 clock-output-names = "tcon-pixel-clock"; 357 #clock-cells = <0>; 358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 359 reset-names = "lcd", "lvds"; 360 361 ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 tcon0_in: port@0 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0>; 369 370 tcon0_in_mixer0: endpoint@0 { 371 reg = <0>; 372 remote-endpoint = <&mixer0_out_tcon0>; 373 }; 374 375 tcon0_in_mixer1: endpoint@1 { 376 reg = <1>; 377 remote-endpoint = <&mixer1_out_tcon0>; 378 }; 379 }; 380 381 tcon0_out: port@1 { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <1>; 385 }; 386 }; 387 }; 388 389 tcon1: lcd-controller@1c0d000 { 390 compatible = "allwinner,sun50i-a64-tcon-tv", 391 "allwinner,sun8i-a83t-tcon-tv"; 392 reg = <0x01c0d000 0x1000>; 393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 395 clock-names = "ahb", "tcon-ch1"; 396 resets = <&ccu RST_BUS_TCON1>; 397 reset-names = "lcd"; 398 399 ports { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 tcon1_in: port@0 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0>; 407 408 tcon1_in_mixer0: endpoint@0 { 409 reg = <0>; 410 remote-endpoint = <&mixer0_out_tcon1>; 411 }; 412 413 tcon1_in_mixer1: endpoint@1 { 414 reg = <1>; 415 remote-endpoint = <&mixer1_out_tcon1>; 416 }; 417 }; 418 419 tcon1_out: port@1 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <1>; 423 424 tcon1_out_hdmi: endpoint@1 { 425 reg = <1>; 426 remote-endpoint = <&hdmi_in_tcon1>; 427 }; 428 }; 429 }; 430 }; 431 432 video-codec@1c0e000 { 433 compatible = "allwinner,sun50i-a64-video-engine"; 434 reg = <0x01c0e000 0x1000>; 435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 436 <&ccu CLK_DRAM_VE>; 437 clock-names = "ahb", "mod", "ram"; 438 resets = <&ccu RST_BUS_VE>; 439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 440 allwinner,sram = <&ve_sram 1>; 441 }; 442 443 mmc0: mmc@1c0f000 { 444 compatible = "allwinner,sun50i-a64-mmc"; 445 reg = <0x01c0f000 0x1000>; 446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 447 clock-names = "ahb", "mmc"; 448 resets = <&ccu RST_BUS_MMC0>; 449 reset-names = "ahb"; 450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 451 max-frequency = <150000000>; 452 status = "disabled"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 }; 456 457 mmc1: mmc@1c10000 { 458 compatible = "allwinner,sun50i-a64-mmc"; 459 reg = <0x01c10000 0x1000>; 460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 461 clock-names = "ahb", "mmc"; 462 resets = <&ccu RST_BUS_MMC1>; 463 reset-names = "ahb"; 464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 465 max-frequency = <150000000>; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 mmc2: mmc@1c11000 { 472 compatible = "allwinner,sun50i-a64-emmc"; 473 reg = <0x01c11000 0x1000>; 474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 475 clock-names = "ahb", "mmc"; 476 resets = <&ccu RST_BUS_MMC2>; 477 reset-names = "ahb"; 478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 479 max-frequency = <200000000>; 480 status = "disabled"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 }; 484 485 sid: eeprom@1c14000 { 486 compatible = "allwinner,sun50i-a64-sid"; 487 reg = <0x1c14000 0x400>; 488 }; 489 490 usb_otg: usb@1c19000 { 491 compatible = "allwinner,sun8i-a33-musb"; 492 reg = <0x01c19000 0x0400>; 493 clocks = <&ccu CLK_BUS_OTG>; 494 resets = <&ccu RST_BUS_OTG>; 495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "mc"; 497 phys = <&usbphy 0>; 498 phy-names = "usb"; 499 extcon = <&usbphy 0>; 500 dr_mode = "otg"; 501 status = "disabled"; 502 }; 503 504 usbphy: phy@1c19400 { 505 compatible = "allwinner,sun50i-a64-usb-phy"; 506 reg = <0x01c19400 0x14>, 507 <0x01c1a800 0x4>, 508 <0x01c1b800 0x4>; 509 reg-names = "phy_ctrl", 510 "pmu0", 511 "pmu1"; 512 clocks = <&ccu CLK_USB_PHY0>, 513 <&ccu CLK_USB_PHY1>; 514 clock-names = "usb0_phy", 515 "usb1_phy"; 516 resets = <&ccu RST_USB_PHY0>, 517 <&ccu RST_USB_PHY1>; 518 reset-names = "usb0_reset", 519 "usb1_reset"; 520 status = "disabled"; 521 #phy-cells = <1>; 522 }; 523 524 ehci0: usb@1c1a000 { 525 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 526 reg = <0x01c1a000 0x100>; 527 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&ccu CLK_BUS_OHCI0>, 529 <&ccu CLK_BUS_EHCI0>, 530 <&ccu CLK_USB_OHCI0>; 531 resets = <&ccu RST_BUS_OHCI0>, 532 <&ccu RST_BUS_EHCI0>; 533 status = "disabled"; 534 }; 535 536 ohci0: usb@1c1a400 { 537 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 538 reg = <0x01c1a400 0x100>; 539 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&ccu CLK_BUS_OHCI0>, 541 <&ccu CLK_USB_OHCI0>; 542 resets = <&ccu RST_BUS_OHCI0>; 543 status = "disabled"; 544 }; 545 546 ehci1: usb@1c1b000 { 547 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 548 reg = <0x01c1b000 0x100>; 549 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&ccu CLK_BUS_OHCI1>, 551 <&ccu CLK_BUS_EHCI1>, 552 <&ccu CLK_USB_OHCI1>; 553 resets = <&ccu RST_BUS_OHCI1>, 554 <&ccu RST_BUS_EHCI1>; 555 phys = <&usbphy 1>; 556 phy-names = "usb"; 557 status = "disabled"; 558 }; 559 560 ohci1: usb@1c1b400 { 561 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 562 reg = <0x01c1b400 0x100>; 563 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_BUS_OHCI1>, 565 <&ccu CLK_USB_OHCI1>; 566 resets = <&ccu RST_BUS_OHCI1>; 567 phys = <&usbphy 1>; 568 phy-names = "usb"; 569 status = "disabled"; 570 }; 571 572 ccu: clock@1c20000 { 573 compatible = "allwinner,sun50i-a64-ccu"; 574 reg = <0x01c20000 0x400>; 575 clocks = <&osc24M>, <&rtc 0>; 576 clock-names = "hosc", "losc"; 577 #clock-cells = <1>; 578 #reset-cells = <1>; 579 }; 580 581 pio: pinctrl@1c20800 { 582 compatible = "allwinner,sun50i-a64-pinctrl"; 583 reg = <0x01c20800 0x400>; 584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 588 clock-names = "apb", "hosc", "losc"; 589 gpio-controller; 590 #gpio-cells = <3>; 591 interrupt-controller; 592 #interrupt-cells = <3>; 593 594 csi_pins: csi-pins { 595 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 596 "PE7", "PE8", "PE9", "PE10", "PE11"; 597 function = "csi"; 598 }; 599 600 /omit-if-no-ref/ 601 csi_mclk_pin: csi-mclk-pin { 602 pins = "PE1"; 603 function = "csi"; 604 }; 605 606 i2c0_pins: i2c0-pins { 607 pins = "PH0", "PH1"; 608 function = "i2c0"; 609 }; 610 611 i2c1_pins: i2c1-pins { 612 pins = "PH2", "PH3"; 613 function = "i2c1"; 614 }; 615 616 /omit-if-no-ref/ 617 lcd_rgb666_pins: lcd-rgb666-pins { 618 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 619 "PD5", "PD6", "PD7", "PD8", "PD9", 620 "PD10", "PD11", "PD12", "PD13", 621 "PD14", "PD15", "PD16", "PD17", 622 "PD18", "PD19", "PD20", "PD21"; 623 function = "lcd0"; 624 }; 625 626 mmc0_pins: mmc0-pins { 627 pins = "PF0", "PF1", "PF2", "PF3", 628 "PF4", "PF5"; 629 function = "mmc0"; 630 drive-strength = <30>; 631 bias-pull-up; 632 }; 633 634 mmc1_pins: mmc1-pins { 635 pins = "PG0", "PG1", "PG2", "PG3", 636 "PG4", "PG5"; 637 function = "mmc1"; 638 drive-strength = <30>; 639 bias-pull-up; 640 }; 641 642 mmc2_pins: mmc2-pins { 643 pins = "PC5", "PC6", "PC8", "PC9", 644 "PC10","PC11", "PC12", "PC13", 645 "PC14", "PC15", "PC16"; 646 function = "mmc2"; 647 drive-strength = <30>; 648 bias-pull-up; 649 }; 650 651 mmc2_ds_pin: mmc2-ds-pin { 652 pins = "PC1"; 653 function = "mmc2"; 654 drive-strength = <30>; 655 bias-pull-up; 656 }; 657 658 pwm_pin: pwm-pin { 659 pins = "PD22"; 660 function = "pwm"; 661 }; 662 663 rmii_pins: rmii-pins { 664 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 665 "PD18", "PD19", "PD20", "PD22", "PD23"; 666 function = "emac"; 667 drive-strength = <40>; 668 }; 669 670 rgmii_pins: rgmii-pins { 671 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 672 "PD13", "PD15", "PD16", "PD17", "PD18", 673 "PD19", "PD20", "PD21", "PD22", "PD23"; 674 function = "emac"; 675 drive-strength = <40>; 676 }; 677 678 spdif_tx_pin: spdif-tx-pin { 679 pins = "PH8"; 680 function = "spdif"; 681 }; 682 683 spi0_pins: spi0-pins { 684 pins = "PC0", "PC1", "PC2", "PC3"; 685 function = "spi0"; 686 }; 687 688 spi1_pins: spi1-pins { 689 pins = "PD0", "PD1", "PD2", "PD3"; 690 function = "spi1"; 691 }; 692 693 uart0_pb_pins: uart0-pb-pins { 694 pins = "PB8", "PB9"; 695 function = "uart0"; 696 }; 697 698 uart1_pins: uart1-pins { 699 pins = "PG6", "PG7"; 700 function = "uart1"; 701 }; 702 703 uart1_rts_cts_pins: uart1-rts-cts-pins { 704 pins = "PG8", "PG9"; 705 function = "uart1"; 706 }; 707 708 uart2_pins: uart2-pins { 709 pins = "PB0", "PB1"; 710 function = "uart2"; 711 }; 712 713 uart3_pins: uart3-pins { 714 pins = "PD0", "PD1"; 715 function = "uart3"; 716 }; 717 718 uart4_pins: uart4-pins { 719 pins = "PD2", "PD3"; 720 function = "uart4"; 721 }; 722 723 uart4_rts_cts_pins: uart4-rts-cts-pins { 724 pins = "PD4", "PD5"; 725 function = "uart4"; 726 }; 727 }; 728 729 spdif: spdif@1c21000 { 730 #sound-dai-cells = <0>; 731 compatible = "allwinner,sun50i-a64-spdif", 732 "allwinner,sun8i-h3-spdif"; 733 reg = <0x01c21000 0x400>; 734 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 736 resets = <&ccu RST_BUS_SPDIF>; 737 clock-names = "apb", "spdif"; 738 dmas = <&dma 2>; 739 dma-names = "tx"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&spdif_tx_pin>; 742 status = "disabled"; 743 }; 744 745 lradc: lradc@1c21800 { 746 compatible = "allwinner,sun50i-a64-lradc", 747 "allwinner,sun8i-a83t-r-lradc"; 748 reg = <0x01c21800 0x400>; 749 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 750 status = "disabled"; 751 }; 752 753 i2s0: i2s@1c22000 { 754 #sound-dai-cells = <0>; 755 compatible = "allwinner,sun50i-a64-i2s", 756 "allwinner,sun8i-h3-i2s"; 757 reg = <0x01c22000 0x400>; 758 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 760 clock-names = "apb", "mod"; 761 resets = <&ccu RST_BUS_I2S0>; 762 dma-names = "rx", "tx"; 763 dmas = <&dma 3>, <&dma 3>; 764 status = "disabled"; 765 }; 766 767 i2s1: i2s@1c22400 { 768 #sound-dai-cells = <0>; 769 compatible = "allwinner,sun50i-a64-i2s", 770 "allwinner,sun8i-h3-i2s"; 771 reg = <0x01c22400 0x400>; 772 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 774 clock-names = "apb", "mod"; 775 resets = <&ccu RST_BUS_I2S1>; 776 dma-names = "rx", "tx"; 777 dmas = <&dma 4>, <&dma 4>; 778 status = "disabled"; 779 }; 780 781 dai: dai@1c22c00 { 782 #sound-dai-cells = <0>; 783 compatible = "allwinner,sun50i-a64-codec-i2s"; 784 reg = <0x01c22c00 0x200>; 785 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 787 clock-names = "apb", "mod"; 788 resets = <&ccu RST_BUS_CODEC>; 789 dmas = <&dma 15>, <&dma 15>; 790 dma-names = "rx", "tx"; 791 status = "disabled"; 792 }; 793 794 codec: codec@1c22e00 { 795 #sound-dai-cells = <0>; 796 compatible = "allwinner,sun8i-a33-codec"; 797 reg = <0x01c22e00 0x600>; 798 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 800 clock-names = "bus", "mod"; 801 status = "disabled"; 802 }; 803 804 uart0: serial@1c28000 { 805 compatible = "snps,dw-apb-uart"; 806 reg = <0x01c28000 0x400>; 807 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 808 reg-shift = <2>; 809 reg-io-width = <4>; 810 clocks = <&ccu CLK_BUS_UART0>; 811 resets = <&ccu RST_BUS_UART0>; 812 status = "disabled"; 813 }; 814 815 uart1: serial@1c28400 { 816 compatible = "snps,dw-apb-uart"; 817 reg = <0x01c28400 0x400>; 818 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 819 reg-shift = <2>; 820 reg-io-width = <4>; 821 clocks = <&ccu CLK_BUS_UART1>; 822 resets = <&ccu RST_BUS_UART1>; 823 status = "disabled"; 824 }; 825 826 uart2: serial@1c28800 { 827 compatible = "snps,dw-apb-uart"; 828 reg = <0x01c28800 0x400>; 829 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 830 reg-shift = <2>; 831 reg-io-width = <4>; 832 clocks = <&ccu CLK_BUS_UART2>; 833 resets = <&ccu RST_BUS_UART2>; 834 status = "disabled"; 835 }; 836 837 uart3: serial@1c28c00 { 838 compatible = "snps,dw-apb-uart"; 839 reg = <0x01c28c00 0x400>; 840 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 841 reg-shift = <2>; 842 reg-io-width = <4>; 843 clocks = <&ccu CLK_BUS_UART3>; 844 resets = <&ccu RST_BUS_UART3>; 845 status = "disabled"; 846 }; 847 848 uart4: serial@1c29000 { 849 compatible = "snps,dw-apb-uart"; 850 reg = <0x01c29000 0x400>; 851 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 852 reg-shift = <2>; 853 reg-io-width = <4>; 854 clocks = <&ccu CLK_BUS_UART4>; 855 resets = <&ccu RST_BUS_UART4>; 856 status = "disabled"; 857 }; 858 859 i2c0: i2c@1c2ac00 { 860 compatible = "allwinner,sun6i-a31-i2c"; 861 reg = <0x01c2ac00 0x400>; 862 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&ccu CLK_BUS_I2C0>; 864 resets = <&ccu RST_BUS_I2C0>; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&i2c0_pins>; 867 status = "disabled"; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 }; 871 872 i2c1: i2c@1c2b000 { 873 compatible = "allwinner,sun6i-a31-i2c"; 874 reg = <0x01c2b000 0x400>; 875 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&ccu CLK_BUS_I2C1>; 877 resets = <&ccu RST_BUS_I2C1>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&i2c1_pins>; 880 status = "disabled"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 }; 884 885 i2c2: i2c@1c2b400 { 886 compatible = "allwinner,sun6i-a31-i2c"; 887 reg = <0x01c2b400 0x400>; 888 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&ccu CLK_BUS_I2C2>; 890 resets = <&ccu RST_BUS_I2C2>; 891 status = "disabled"; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 }; 895 896 897 spi0: spi@1c68000 { 898 compatible = "allwinner,sun8i-h3-spi"; 899 reg = <0x01c68000 0x1000>; 900 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 902 clock-names = "ahb", "mod"; 903 dmas = <&dma 23>, <&dma 23>; 904 dma-names = "rx", "tx"; 905 pinctrl-names = "default"; 906 pinctrl-0 = <&spi0_pins>; 907 resets = <&ccu RST_BUS_SPI0>; 908 status = "disabled"; 909 num-cs = <1>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 }; 913 914 spi1: spi@1c69000 { 915 compatible = "allwinner,sun8i-h3-spi"; 916 reg = <0x01c69000 0x1000>; 917 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 919 clock-names = "ahb", "mod"; 920 dmas = <&dma 24>, <&dma 24>; 921 dma-names = "rx", "tx"; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&spi1_pins>; 924 resets = <&ccu RST_BUS_SPI1>; 925 status = "disabled"; 926 num-cs = <1>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 }; 930 931 emac: ethernet@1c30000 { 932 compatible = "allwinner,sun50i-a64-emac"; 933 syscon = <&syscon>; 934 reg = <0x01c30000 0x10000>; 935 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-names = "macirq"; 937 resets = <&ccu RST_BUS_EMAC>; 938 reset-names = "stmmaceth"; 939 clocks = <&ccu CLK_BUS_EMAC>; 940 clock-names = "stmmaceth"; 941 status = "disabled"; 942 943 mdio: mdio { 944 compatible = "snps,dwmac-mdio"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 }; 948 }; 949 950 mali: gpu@1c40000 { 951 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 952 reg = <0x01c40000 0x10000>; 953 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 960 interrupt-names = "gp", 961 "gpmmu", 962 "pp0", 963 "ppmmu0", 964 "pp1", 965 "ppmmu1", 966 "pmu"; 967 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 968 clock-names = "bus", "core"; 969 resets = <&ccu RST_BUS_GPU>; 970 }; 971 972 gic: interrupt-controller@1c81000 { 973 compatible = "arm,gic-400"; 974 reg = <0x01c81000 0x1000>, 975 <0x01c82000 0x2000>, 976 <0x01c84000 0x2000>, 977 <0x01c86000 0x2000>; 978 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 979 interrupt-controller; 980 #interrupt-cells = <3>; 981 }; 982 983 pwm: pwm@1c21400 { 984 compatible = "allwinner,sun50i-a64-pwm", 985 "allwinner,sun5i-a13-pwm"; 986 reg = <0x01c21400 0x400>; 987 clocks = <&osc24M>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&pwm_pin>; 990 #pwm-cells = <3>; 991 status = "disabled"; 992 }; 993 994 csi: csi@1cb0000 { 995 compatible = "allwinner,sun50i-a64-csi"; 996 reg = <0x01cb0000 0x1000>; 997 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&ccu CLK_BUS_CSI>, 999 <&ccu CLK_CSI_SCLK>, 1000 <&ccu CLK_DRAM_CSI>; 1001 clock-names = "bus", "mod", "ram"; 1002 resets = <&ccu RST_BUS_CSI>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&csi_pins>; 1005 status = "disabled"; 1006 }; 1007 1008 hdmi: hdmi@1ee0000 { 1009 compatible = "allwinner,sun50i-a64-dw-hdmi", 1010 "allwinner,sun8i-a83t-dw-hdmi"; 1011 reg = <0x01ee0000 0x10000>; 1012 reg-io-width = <1>; 1013 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1015 <&ccu CLK_HDMI>; 1016 clock-names = "iahb", "isfr", "tmds"; 1017 resets = <&ccu RST_BUS_HDMI1>; 1018 reset-names = "ctrl"; 1019 phys = <&hdmi_phy>; 1020 phy-names = "phy"; 1021 status = "disabled"; 1022 1023 ports { 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 1027 hdmi_in: port@0 { 1028 reg = <0>; 1029 1030 hdmi_in_tcon1: endpoint { 1031 remote-endpoint = <&tcon1_out_hdmi>; 1032 }; 1033 }; 1034 1035 hdmi_out: port@1 { 1036 reg = <1>; 1037 }; 1038 }; 1039 }; 1040 1041 hdmi_phy: hdmi-phy@1ef0000 { 1042 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1043 reg = <0x01ef0000 0x10000>; 1044 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1045 <&ccu 7>; 1046 clock-names = "bus", "mod", "pll-0"; 1047 resets = <&ccu RST_BUS_HDMI0>; 1048 reset-names = "phy"; 1049 #phy-cells = <0>; 1050 }; 1051 1052 rtc: rtc@1f00000 { 1053 compatible = "allwinner,sun50i-a64-rtc", 1054 "allwinner,sun8i-h3-rtc"; 1055 reg = <0x01f00000 0x400>; 1056 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1058 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1059 clocks = <&osc32k>; 1060 #clock-cells = <1>; 1061 }; 1062 1063 r_intc: interrupt-controller@1f00c00 { 1064 compatible = "allwinner,sun50i-a64-r-intc", 1065 "allwinner,sun6i-a31-r-intc"; 1066 interrupt-controller; 1067 #interrupt-cells = <2>; 1068 reg = <0x01f00c00 0x400>; 1069 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1070 }; 1071 1072 r_ccu: clock@1f01400 { 1073 compatible = "allwinner,sun50i-a64-r-ccu"; 1074 reg = <0x01f01400 0x100>; 1075 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1076 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1077 #clock-cells = <1>; 1078 #reset-cells = <1>; 1079 }; 1080 1081 codec_analog: codec-analog@1f015c0 { 1082 compatible = "allwinner,sun50i-a64-codec-analog"; 1083 reg = <0x01f015c0 0x4>; 1084 status = "disabled"; 1085 }; 1086 1087 r_i2c: i2c@1f02400 { 1088 compatible = "allwinner,sun50i-a64-i2c", 1089 "allwinner,sun6i-a31-i2c"; 1090 reg = <0x01f02400 0x400>; 1091 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&r_ccu CLK_APB0_I2C>; 1093 resets = <&r_ccu RST_APB0_I2C>; 1094 status = "disabled"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 }; 1098 1099 r_ir: ir@1f02000 { 1100 compatible = "allwinner,sun50i-a64-ir", 1101 "allwinner,sun6i-a31-ir"; 1102 reg = <0x01f02000 0x400>; 1103 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1104 clock-names = "apb", "ir"; 1105 resets = <&r_ccu RST_APB0_IR>; 1106 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&r_ir_rx_pin>; 1109 status = "disabled"; 1110 }; 1111 1112 r_pwm: pwm@1f03800 { 1113 compatible = "allwinner,sun50i-a64-pwm", 1114 "allwinner,sun5i-a13-pwm"; 1115 reg = <0x01f03800 0x400>; 1116 clocks = <&osc24M>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&r_pwm_pin>; 1119 #pwm-cells = <3>; 1120 status = "disabled"; 1121 }; 1122 1123 r_pio: pinctrl@1f02c00 { 1124 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1125 reg = <0x01f02c00 0x400>; 1126 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1128 clock-names = "apb", "hosc", "losc"; 1129 gpio-controller; 1130 #gpio-cells = <3>; 1131 interrupt-controller; 1132 #interrupt-cells = <3>; 1133 1134 r_i2c_pl89_pins: r-i2c-pl89-pins { 1135 pins = "PL8", "PL9"; 1136 function = "s_i2c"; 1137 }; 1138 1139 r_ir_rx_pin: r-ir-rx-pin { 1140 pins = "PL11"; 1141 function = "s_cir_rx"; 1142 }; 1143 1144 r_pwm_pin: r-pwm-pin { 1145 pins = "PL10"; 1146 function = "s_pwm"; 1147 }; 1148 1149 r_rsb_pins: r-rsb-pins { 1150 pins = "PL0", "PL1"; 1151 function = "s_rsb"; 1152 }; 1153 }; 1154 1155 r_rsb: rsb@1f03400 { 1156 compatible = "allwinner,sun8i-a23-rsb"; 1157 reg = <0x01f03400 0x400>; 1158 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&r_ccu 6>; 1160 clock-frequency = <3000000>; 1161 resets = <&r_ccu 2>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&r_rsb_pins>; 1164 status = "disabled"; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 }; 1168 1169 wdt0: watchdog@1c20ca0 { 1170 compatible = "allwinner,sun50i-a64-wdt", 1171 "allwinner,sun6i-a31-wdt"; 1172 reg = <0x01c20ca0 0x20>; 1173 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&osc24M>; 1175 }; 1176 }; 1177}; 1178