1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 145 iosc: internal-osc-clk { 146 #clock-cells = <0>; 147 compatible = "fixed-clock"; 148 clock-frequency = <16000000>; 149 clock-accuracy = <300000000>; 150 clock-output-names = "iosc"; 151 }; 152 153 psci { 154 compatible = "arm,psci-0.2"; 155 method = "smc"; 156 }; 157 158 sound: sound { 159 compatible = "simple-audio-card"; 160 simple-audio-card,name = "sun50i-a64-audio"; 161 simple-audio-card,format = "i2s"; 162 simple-audio-card,frame-master = <&cpudai>; 163 simple-audio-card,bitclock-master = <&cpudai>; 164 simple-audio-card,mclk-fs = <128>; 165 simple-audio-card,aux-devs = <&codec_analog>; 166 simple-audio-card,routing = 167 "Left DAC", "AIF1 Slot 0 Left", 168 "Right DAC", "AIF1 Slot 0 Right", 169 "AIF1 Slot 0 Left ADC", "Left ADC", 170 "AIF1 Slot 0 Right ADC", "Right ADC"; 171 status = "disabled"; 172 173 cpudai: simple-audio-card,cpu { 174 sound-dai = <&dai>; 175 }; 176 177 link_codec: simple-audio-card,codec { 178 sound-dai = <&codec>; 179 }; 180 }; 181 182 sound_spdif { 183 compatible = "simple-audio-card"; 184 simple-audio-card,name = "On-board SPDIF"; 185 186 simple-audio-card,cpu { 187 sound-dai = <&spdif>; 188 }; 189 190 simple-audio-card,codec { 191 sound-dai = <&spdif_out>; 192 }; 193 }; 194 195 spdif_out: spdif-out { 196 #sound-dai-cells = <0>; 197 compatible = "linux,spdif-dit"; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 203 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 204 <GIC_PPI 14 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 11 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 10 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 210 }; 211 212 soc { 213 compatible = "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 218 de2@1000000 { 219 compatible = "allwinner,sun50i-a64-de2"; 220 reg = <0x1000000 0x400000>; 221 allwinner,sram = <&de2_sram 1>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x1000000 0x400000>; 225 226 display_clocks: clock@0 { 227 compatible = "allwinner,sun50i-a64-de2-clk"; 228 reg = <0x0 0x100000>; 229 clocks = <&ccu CLK_DE>, 230 <&ccu CLK_BUS_DE>; 231 clock-names = "mod", 232 "bus"; 233 resets = <&ccu RST_BUS_DE>; 234 #clock-cells = <1>; 235 #reset-cells = <1>; 236 }; 237 238 mixer0: mixer@100000 { 239 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 240 reg = <0x100000 0x100000>; 241 clocks = <&display_clocks CLK_BUS_MIXER0>, 242 <&display_clocks CLK_MIXER0>; 243 clock-names = "bus", 244 "mod"; 245 resets = <&display_clocks RST_MIXER0>; 246 247 ports { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 mixer0_out: port@1 { 252 reg = <1>; 253 254 mixer0_out_tcon0: endpoint { 255 remote-endpoint = <&tcon0_in_mixer0>; 256 }; 257 }; 258 }; 259 }; 260 261 mixer1: mixer@200000 { 262 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 263 reg = <0x200000 0x100000>; 264 clocks = <&display_clocks CLK_BUS_MIXER1>, 265 <&display_clocks CLK_MIXER1>; 266 clock-names = "bus", 267 "mod"; 268 resets = <&display_clocks RST_MIXER1>; 269 270 ports { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 mixer1_out: port@1 { 275 reg = <1>; 276 277 mixer1_out_tcon1: endpoint { 278 remote-endpoint = <&tcon1_in_mixer1>; 279 }; 280 }; 281 }; 282 }; 283 }; 284 285 syscon: syscon@1c00000 { 286 compatible = "allwinner,sun50i-a64-system-control"; 287 reg = <0x01c00000 0x1000>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges; 291 292 sram_c: sram@18000 { 293 compatible = "mmio-sram"; 294 reg = <0x00018000 0x28000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0 0x00018000 0x28000>; 298 299 de2_sram: sram-section@0 { 300 compatible = "allwinner,sun50i-a64-sram-c"; 301 reg = <0x0000 0x28000>; 302 }; 303 }; 304 305 sram_c1: sram@1d00000 { 306 compatible = "mmio-sram"; 307 reg = <0x01d00000 0x40000>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0 0x01d00000 0x40000>; 311 312 ve_sram: sram-section@0 { 313 compatible = "allwinner,sun50i-a64-sram-c1", 314 "allwinner,sun4i-a10-sram-c1"; 315 reg = <0x000000 0x40000>; 316 }; 317 }; 318 }; 319 320 dma: dma-controller@1c02000 { 321 compatible = "allwinner,sun50i-a64-dma"; 322 reg = <0x01c02000 0x1000>; 323 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&ccu CLK_BUS_DMA>; 325 dma-channels = <8>; 326 dma-requests = <27>; 327 resets = <&ccu RST_BUS_DMA>; 328 #dma-cells = <1>; 329 }; 330 331 tcon0: lcd-controller@1c0c000 { 332 compatible = "allwinner,sun50i-a64-tcon-lcd", 333 "allwinner,sun8i-a83t-tcon-lcd"; 334 reg = <0x01c0c000 0x1000>; 335 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 337 clock-names = "ahb", "tcon-ch0"; 338 clock-output-names = "tcon-pixel-clock"; 339 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 340 reset-names = "lcd", "lvds"; 341 342 ports { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 tcon0_in: port@0 { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 reg = <0>; 350 351 tcon0_in_mixer0: endpoint@0 { 352 reg = <0>; 353 remote-endpoint = <&mixer0_out_tcon0>; 354 }; 355 }; 356 357 tcon0_out: port@1 { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 reg = <1>; 361 }; 362 }; 363 }; 364 365 tcon1: lcd-controller@1c0d000 { 366 compatible = "allwinner,sun50i-a64-tcon-tv", 367 "allwinner,sun8i-a83t-tcon-tv"; 368 reg = <0x01c0d000 0x1000>; 369 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 371 clock-names = "ahb", "tcon-ch1"; 372 resets = <&ccu RST_BUS_TCON1>; 373 reset-names = "lcd"; 374 375 ports { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 379 tcon1_in: port@0 { 380 reg = <0>; 381 382 tcon1_in_mixer1: endpoint { 383 remote-endpoint = <&mixer1_out_tcon1>; 384 }; 385 }; 386 387 tcon1_out: port@1 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <1>; 391 392 tcon1_out_hdmi: endpoint@1 { 393 reg = <1>; 394 remote-endpoint = <&hdmi_in_tcon1>; 395 }; 396 }; 397 }; 398 }; 399 400 video-codec@1c0e000 { 401 compatible = "allwinner,sun50i-h5-video-engine"; 402 reg = <0x01c0e000 0x1000>; 403 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 404 <&ccu CLK_DRAM_VE>; 405 clock-names = "ahb", "mod", "ram"; 406 resets = <&ccu RST_BUS_VE>; 407 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 408 allwinner,sram = <&ve_sram 1>; 409 }; 410 411 mmc0: mmc@1c0f000 { 412 compatible = "allwinner,sun50i-a64-mmc"; 413 reg = <0x01c0f000 0x1000>; 414 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 415 clock-names = "ahb", "mmc"; 416 resets = <&ccu RST_BUS_MMC0>; 417 reset-names = "ahb"; 418 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 419 max-frequency = <150000000>; 420 status = "disabled"; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 }; 424 425 mmc1: mmc@1c10000 { 426 compatible = "allwinner,sun50i-a64-mmc"; 427 reg = <0x01c10000 0x1000>; 428 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 429 clock-names = "ahb", "mmc"; 430 resets = <&ccu RST_BUS_MMC1>; 431 reset-names = "ahb"; 432 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 433 max-frequency = <150000000>; 434 status = "disabled"; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 }; 438 439 mmc2: mmc@1c11000 { 440 compatible = "allwinner,sun50i-a64-emmc"; 441 reg = <0x01c11000 0x1000>; 442 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 443 clock-names = "ahb", "mmc"; 444 resets = <&ccu RST_BUS_MMC2>; 445 reset-names = "ahb"; 446 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 447 max-frequency = <200000000>; 448 status = "disabled"; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 }; 452 453 sid: eeprom@1c14000 { 454 compatible = "allwinner,sun50i-a64-sid"; 455 reg = <0x1c14000 0x400>; 456 }; 457 458 usb_otg: usb@1c19000 { 459 compatible = "allwinner,sun8i-a33-musb"; 460 reg = <0x01c19000 0x0400>; 461 clocks = <&ccu CLK_BUS_OTG>; 462 resets = <&ccu RST_BUS_OTG>; 463 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "mc"; 465 phys = <&usbphy 0>; 466 phy-names = "usb"; 467 extcon = <&usbphy 0>; 468 status = "disabled"; 469 }; 470 471 usbphy: phy@1c19400 { 472 compatible = "allwinner,sun50i-a64-usb-phy"; 473 reg = <0x01c19400 0x14>, 474 <0x01c1a800 0x4>, 475 <0x01c1b800 0x4>; 476 reg-names = "phy_ctrl", 477 "pmu0", 478 "pmu1"; 479 clocks = <&ccu CLK_USB_PHY0>, 480 <&ccu CLK_USB_PHY1>; 481 clock-names = "usb0_phy", 482 "usb1_phy"; 483 resets = <&ccu RST_USB_PHY0>, 484 <&ccu RST_USB_PHY1>; 485 reset-names = "usb0_reset", 486 "usb1_reset"; 487 status = "disabled"; 488 #phy-cells = <1>; 489 }; 490 491 ehci0: usb@1c1a000 { 492 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 493 reg = <0x01c1a000 0x100>; 494 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&ccu CLK_BUS_OHCI0>, 496 <&ccu CLK_BUS_EHCI0>, 497 <&ccu CLK_USB_OHCI0>; 498 resets = <&ccu RST_BUS_OHCI0>, 499 <&ccu RST_BUS_EHCI0>; 500 status = "disabled"; 501 }; 502 503 ohci0: usb@1c1a400 { 504 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 505 reg = <0x01c1a400 0x100>; 506 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&ccu CLK_BUS_OHCI0>, 508 <&ccu CLK_USB_OHCI0>; 509 resets = <&ccu RST_BUS_OHCI0>; 510 status = "disabled"; 511 }; 512 513 ehci1: usb@1c1b000 { 514 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 515 reg = <0x01c1b000 0x100>; 516 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&ccu CLK_BUS_OHCI1>, 518 <&ccu CLK_BUS_EHCI1>, 519 <&ccu CLK_USB_OHCI1>; 520 resets = <&ccu RST_BUS_OHCI1>, 521 <&ccu RST_BUS_EHCI1>; 522 phys = <&usbphy 1>; 523 phy-names = "usb"; 524 status = "disabled"; 525 }; 526 527 ohci1: usb@1c1b400 { 528 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 529 reg = <0x01c1b400 0x100>; 530 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&ccu CLK_BUS_OHCI1>, 532 <&ccu CLK_USB_OHCI1>; 533 resets = <&ccu RST_BUS_OHCI1>; 534 phys = <&usbphy 1>; 535 phy-names = "usb"; 536 status = "disabled"; 537 }; 538 539 ccu: clock@1c20000 { 540 compatible = "allwinner,sun50i-a64-ccu"; 541 reg = <0x01c20000 0x400>; 542 clocks = <&osc24M>, <&osc32k>; 543 clock-names = "hosc", "losc"; 544 #clock-cells = <1>; 545 #reset-cells = <1>; 546 }; 547 548 pio: pinctrl@1c20800 { 549 compatible = "allwinner,sun50i-a64-pinctrl"; 550 reg = <0x01c20800 0x400>; 551 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&ccu 58>; 555 gpio-controller; 556 #gpio-cells = <3>; 557 interrupt-controller; 558 #interrupt-cells = <3>; 559 560 i2c0_pins: i2c0_pins { 561 pins = "PH0", "PH1"; 562 function = "i2c0"; 563 }; 564 565 i2c1_pins: i2c1_pins { 566 pins = "PH2", "PH3"; 567 function = "i2c1"; 568 }; 569 570 mmc0_pins: mmc0-pins { 571 pins = "PF0", "PF1", "PF2", "PF3", 572 "PF4", "PF5"; 573 function = "mmc0"; 574 drive-strength = <30>; 575 bias-pull-up; 576 }; 577 578 mmc1_pins: mmc1-pins { 579 pins = "PG0", "PG1", "PG2", "PG3", 580 "PG4", "PG5"; 581 function = "mmc1"; 582 drive-strength = <30>; 583 bias-pull-up; 584 }; 585 586 mmc2_pins: mmc2-pins { 587 pins = "PC5", "PC6", "PC8", "PC9", 588 "PC10","PC11", "PC12", "PC13", 589 "PC14", "PC15", "PC16"; 590 function = "mmc2"; 591 drive-strength = <30>; 592 bias-pull-up; 593 }; 594 595 mmc2_ds_pin: mmc2-ds-pin { 596 pins = "PC1"; 597 function = "mmc2"; 598 drive-strength = <30>; 599 bias-pull-up; 600 }; 601 602 pwm_pin: pwm_pin { 603 pins = "PD22"; 604 function = "pwm"; 605 }; 606 607 rmii_pins: rmii_pins { 608 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 609 "PD18", "PD19", "PD20", "PD22", "PD23"; 610 function = "emac"; 611 drive-strength = <40>; 612 }; 613 614 rgmii_pins: rgmii_pins { 615 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 616 "PD13", "PD15", "PD16", "PD17", "PD18", 617 "PD19", "PD20", "PD21", "PD22", "PD23"; 618 function = "emac"; 619 drive-strength = <40>; 620 }; 621 622 spdif_tx_pin: spdif { 623 pins = "PH8"; 624 function = "spdif"; 625 }; 626 627 spi0_pins: spi0 { 628 pins = "PC0", "PC1", "PC2", "PC3"; 629 function = "spi0"; 630 }; 631 632 spi1_pins: spi1 { 633 pins = "PD0", "PD1", "PD2", "PD3"; 634 function = "spi1"; 635 }; 636 637 uart0_pb_pins: uart0-pb-pins { 638 pins = "PB8", "PB9"; 639 function = "uart0"; 640 }; 641 642 uart1_pins: uart1_pins { 643 pins = "PG6", "PG7"; 644 function = "uart1"; 645 }; 646 647 uart1_rts_cts_pins: uart1_rts_cts_pins { 648 pins = "PG8", "PG9"; 649 function = "uart1"; 650 }; 651 652 uart2_pins: uart2-pins { 653 pins = "PB0", "PB1"; 654 function = "uart2"; 655 }; 656 657 uart3_pins: uart3-pins { 658 pins = "PD0", "PD1"; 659 function = "uart3"; 660 }; 661 662 uart4_pins: uart4-pins { 663 pins = "PD2", "PD3"; 664 function = "uart4"; 665 }; 666 667 uart4_rts_cts_pins: uart4-rts-cts-pins { 668 pins = "PD4", "PD5"; 669 function = "uart4"; 670 }; 671 }; 672 673 spdif: spdif@1c21000 { 674 #sound-dai-cells = <0>; 675 compatible = "allwinner,sun50i-a64-spdif", 676 "allwinner,sun8i-h3-spdif"; 677 reg = <0x01c21000 0x400>; 678 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 680 resets = <&ccu RST_BUS_SPDIF>; 681 clock-names = "apb", "spdif"; 682 dmas = <&dma 2>; 683 dma-names = "tx"; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&spdif_tx_pin>; 686 status = "disabled"; 687 }; 688 689 i2s0: i2s@1c22000 { 690 #sound-dai-cells = <0>; 691 compatible = "allwinner,sun50i-a64-i2s", 692 "allwinner,sun8i-h3-i2s"; 693 reg = <0x01c22000 0x400>; 694 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 696 clock-names = "apb", "mod"; 697 resets = <&ccu RST_BUS_I2S0>; 698 dma-names = "rx", "tx"; 699 dmas = <&dma 3>, <&dma 3>; 700 status = "disabled"; 701 }; 702 703 i2s1: i2s@1c22400 { 704 #sound-dai-cells = <0>; 705 compatible = "allwinner,sun50i-a64-i2s", 706 "allwinner,sun8i-h3-i2s"; 707 reg = <0x01c22400 0x400>; 708 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 710 clock-names = "apb", "mod"; 711 resets = <&ccu RST_BUS_I2S1>; 712 dma-names = "rx", "tx"; 713 dmas = <&dma 4>, <&dma 4>; 714 status = "disabled"; 715 }; 716 717 dai: dai@1c22c00 { 718 #sound-dai-cells = <0>; 719 compatible = "allwinner,sun50i-a64-codec-i2s"; 720 reg = <0x01c22c00 0x200>; 721 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 723 clock-names = "apb", "mod"; 724 resets = <&ccu RST_BUS_CODEC>; 725 reset-names = "rst"; 726 dmas = <&dma 15>, <&dma 15>; 727 dma-names = "rx", "tx"; 728 status = "disabled"; 729 }; 730 731 codec: codec@1c22e00 { 732 #sound-dai-cells = <0>; 733 compatible = "allwinner,sun8i-a33-codec"; 734 reg = <0x01c22e00 0x600>; 735 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 737 clock-names = "bus", "mod"; 738 status = "disabled"; 739 }; 740 741 uart0: serial@1c28000 { 742 compatible = "snps,dw-apb-uart"; 743 reg = <0x01c28000 0x400>; 744 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 745 reg-shift = <2>; 746 reg-io-width = <4>; 747 clocks = <&ccu CLK_BUS_UART0>; 748 resets = <&ccu RST_BUS_UART0>; 749 status = "disabled"; 750 }; 751 752 uart1: serial@1c28400 { 753 compatible = "snps,dw-apb-uart"; 754 reg = <0x01c28400 0x400>; 755 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 756 reg-shift = <2>; 757 reg-io-width = <4>; 758 clocks = <&ccu CLK_BUS_UART1>; 759 resets = <&ccu RST_BUS_UART1>; 760 status = "disabled"; 761 }; 762 763 uart2: serial@1c28800 { 764 compatible = "snps,dw-apb-uart"; 765 reg = <0x01c28800 0x400>; 766 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 767 reg-shift = <2>; 768 reg-io-width = <4>; 769 clocks = <&ccu CLK_BUS_UART2>; 770 resets = <&ccu RST_BUS_UART2>; 771 status = "disabled"; 772 }; 773 774 uart3: serial@1c28c00 { 775 compatible = "snps,dw-apb-uart"; 776 reg = <0x01c28c00 0x400>; 777 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 778 reg-shift = <2>; 779 reg-io-width = <4>; 780 clocks = <&ccu CLK_BUS_UART3>; 781 resets = <&ccu RST_BUS_UART3>; 782 status = "disabled"; 783 }; 784 785 uart4: serial@1c29000 { 786 compatible = "snps,dw-apb-uart"; 787 reg = <0x01c29000 0x400>; 788 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 789 reg-shift = <2>; 790 reg-io-width = <4>; 791 clocks = <&ccu CLK_BUS_UART4>; 792 resets = <&ccu RST_BUS_UART4>; 793 status = "disabled"; 794 }; 795 796 i2c0: i2c@1c2ac00 { 797 compatible = "allwinner,sun6i-a31-i2c"; 798 reg = <0x01c2ac00 0x400>; 799 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&ccu CLK_BUS_I2C0>; 801 resets = <&ccu RST_BUS_I2C0>; 802 status = "disabled"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 }; 806 807 i2c1: i2c@1c2b000 { 808 compatible = "allwinner,sun6i-a31-i2c"; 809 reg = <0x01c2b000 0x400>; 810 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&ccu CLK_BUS_I2C1>; 812 resets = <&ccu RST_BUS_I2C1>; 813 status = "disabled"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 }; 817 818 i2c2: i2c@1c2b400 { 819 compatible = "allwinner,sun6i-a31-i2c"; 820 reg = <0x01c2b400 0x400>; 821 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&ccu CLK_BUS_I2C2>; 823 resets = <&ccu RST_BUS_I2C2>; 824 status = "disabled"; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 }; 828 829 830 spi0: spi@1c68000 { 831 compatible = "allwinner,sun8i-h3-spi"; 832 reg = <0x01c68000 0x1000>; 833 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 835 clock-names = "ahb", "mod"; 836 dmas = <&dma 23>, <&dma 23>; 837 dma-names = "rx", "tx"; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&spi0_pins>; 840 resets = <&ccu RST_BUS_SPI0>; 841 status = "disabled"; 842 num-cs = <1>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 }; 846 847 spi1: spi@1c69000 { 848 compatible = "allwinner,sun8i-h3-spi"; 849 reg = <0x01c69000 0x1000>; 850 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 852 clock-names = "ahb", "mod"; 853 dmas = <&dma 24>, <&dma 24>; 854 dma-names = "rx", "tx"; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&spi1_pins>; 857 resets = <&ccu RST_BUS_SPI1>; 858 status = "disabled"; 859 num-cs = <1>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 }; 863 864 emac: ethernet@1c30000 { 865 compatible = "allwinner,sun50i-a64-emac"; 866 syscon = <&syscon>; 867 reg = <0x01c30000 0x10000>; 868 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-names = "macirq"; 870 resets = <&ccu RST_BUS_EMAC>; 871 reset-names = "stmmaceth"; 872 clocks = <&ccu CLK_BUS_EMAC>; 873 clock-names = "stmmaceth"; 874 status = "disabled"; 875 876 mdio: mdio { 877 compatible = "snps,dwmac-mdio"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 }; 881 }; 882 883 mali: gpu@1c40000 { 884 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 885 reg = <0x01c40000 0x10000>; 886 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 893 interrupt-names = "gp", 894 "gpmmu", 895 "pp0", 896 "ppmmu0", 897 "pp1", 898 "ppmmu1", 899 "pmu"; 900 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 901 clock-names = "bus", "core"; 902 resets = <&ccu RST_BUS_GPU>; 903 }; 904 905 gic: interrupt-controller@1c81000 { 906 compatible = "arm,gic-400"; 907 reg = <0x01c81000 0x1000>, 908 <0x01c82000 0x2000>, 909 <0x01c84000 0x2000>, 910 <0x01c86000 0x2000>; 911 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 912 interrupt-controller; 913 #interrupt-cells = <3>; 914 }; 915 916 pwm: pwm@1c21400 { 917 compatible = "allwinner,sun50i-a64-pwm", 918 "allwinner,sun5i-a13-pwm"; 919 reg = <0x01c21400 0x400>; 920 clocks = <&osc24M>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&pwm_pin>; 923 #pwm-cells = <3>; 924 status = "disabled"; 925 }; 926 927 hdmi: hdmi@1ee0000 { 928 compatible = "allwinner,sun50i-a64-dw-hdmi", 929 "allwinner,sun8i-a83t-dw-hdmi"; 930 reg = <0x01ee0000 0x10000>; 931 reg-io-width = <1>; 932 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 934 <&ccu CLK_HDMI>; 935 clock-names = "iahb", "isfr", "tmds"; 936 resets = <&ccu RST_BUS_HDMI1>; 937 reset-names = "ctrl"; 938 phys = <&hdmi_phy>; 939 phy-names = "hdmi-phy"; 940 status = "disabled"; 941 942 ports { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 946 hdmi_in: port@0 { 947 reg = <0>; 948 949 hdmi_in_tcon1: endpoint { 950 remote-endpoint = <&tcon1_out_hdmi>; 951 }; 952 }; 953 954 hdmi_out: port@1 { 955 reg = <1>; 956 }; 957 }; 958 }; 959 960 hdmi_phy: hdmi-phy@1ef0000 { 961 compatible = "allwinner,sun50i-a64-hdmi-phy"; 962 reg = <0x01ef0000 0x10000>; 963 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 964 <&ccu 7>; 965 clock-names = "bus", "mod", "pll-0"; 966 resets = <&ccu RST_BUS_HDMI0>; 967 reset-names = "phy"; 968 #phy-cells = <0>; 969 }; 970 971 rtc: rtc@1f00000 { 972 compatible = "allwinner,sun6i-a31-rtc"; 973 reg = <0x01f00000 0x54>; 974 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 976 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 977 clocks = <&osc32k>; 978 #clock-cells = <1>; 979 }; 980 981 r_intc: interrupt-controller@1f00c00 { 982 compatible = "allwinner,sun50i-a64-r-intc", 983 "allwinner,sun6i-a31-r-intc"; 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 reg = <0x01f00c00 0x400>; 987 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 988 }; 989 990 r_ccu: clock@1f01400 { 991 compatible = "allwinner,sun50i-a64-r-ccu"; 992 reg = <0x01f01400 0x100>; 993 clocks = <&osc24M>, <&osc32k>, <&iosc>, 994 <&ccu 11>; 995 clock-names = "hosc", "losc", "iosc", "pll-periph"; 996 #clock-cells = <1>; 997 #reset-cells = <1>; 998 }; 999 1000 codec_analog: codec-analog@1f015c0 { 1001 compatible = "allwinner,sun50i-a64-codec-analog"; 1002 reg = <0x01f015c0 0x4>; 1003 status = "disabled"; 1004 }; 1005 1006 r_i2c: i2c@1f02400 { 1007 compatible = "allwinner,sun50i-a64-i2c", 1008 "allwinner,sun6i-a31-i2c"; 1009 reg = <0x01f02400 0x400>; 1010 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&r_ccu CLK_APB0_I2C>; 1012 resets = <&r_ccu RST_APB0_I2C>; 1013 status = "disabled"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 }; 1017 1018 r_pwm: pwm@1f03800 { 1019 compatible = "allwinner,sun50i-a64-pwm", 1020 "allwinner,sun5i-a13-pwm"; 1021 reg = <0x01f03800 0x400>; 1022 clocks = <&osc24M>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&r_pwm_pin>; 1025 #pwm-cells = <3>; 1026 status = "disabled"; 1027 }; 1028 1029 r_pio: pinctrl@1f02c00 { 1030 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1031 reg = <0x01f02c00 0x400>; 1032 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1034 clock-names = "apb", "hosc", "losc"; 1035 gpio-controller; 1036 #gpio-cells = <3>; 1037 interrupt-controller; 1038 #interrupt-cells = <3>; 1039 1040 r_i2c_pl89_pins: r-i2c-pl89-pins { 1041 pins = "PL8", "PL9"; 1042 function = "s_i2c"; 1043 }; 1044 1045 r_pwm_pin: pwm { 1046 pins = "PL10"; 1047 function = "s_pwm"; 1048 }; 1049 1050 r_rsb_pins: rsb { 1051 pins = "PL0", "PL1"; 1052 function = "s_rsb"; 1053 }; 1054 }; 1055 1056 r_rsb: rsb@1f03400 { 1057 compatible = "allwinner,sun8i-a23-rsb"; 1058 reg = <0x01f03400 0x400>; 1059 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&r_ccu 6>; 1061 clock-frequency = <3000000>; 1062 resets = <&r_ccu 2>; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&r_rsb_pins>; 1065 status = "disabled"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 }; 1069 1070 wdt0: watchdog@1c20ca0 { 1071 compatible = "allwinner,sun50i-a64-wdt", 1072 "allwinner,sun6i-a31-wdt"; 1073 reg = <0x01c20ca0 0x20>; 1074 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1075 }; 1076 }; 1077}; 1078