1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-r-ccu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/sun50i-a64-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/reset/sun8i-r-ccu.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 chosen { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 simplefb_lcd: framebuffer-lcd { 25 compatible = "allwinner,simple-framebuffer", 26 "simple-framebuffer"; 27 allwinner,pipeline = "mixer0-lcd0"; 28 clocks = <&ccu CLK_TCON0>, 29 <&display_clocks CLK_MIXER0>; 30 status = "disabled"; 31 }; 32 33 simplefb_hdmi: framebuffer-hdmi { 34 compatible = "allwinner,simple-framebuffer", 35 "simple-framebuffer"; 36 allwinner,pipeline = "mixer1-lcd1-hdmi"; 37 clocks = <&display_clocks CLK_MIXER1>, 38 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 39 status = "disabled"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 reg = <0>; 51 enable-method = "psci"; 52 next-level-cache = <&L2>; 53 }; 54 55 cpu1: cpu@1 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 reg = <1>; 59 enable-method = "psci"; 60 next-level-cache = <&L2>; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "arm,cortex-a53"; 65 device_type = "cpu"; 66 reg = <2>; 67 enable-method = "psci"; 68 next-level-cache = <&L2>; 69 }; 70 71 cpu3: cpu@3 { 72 compatible = "arm,cortex-a53"; 73 device_type = "cpu"; 74 reg = <3>; 75 enable-method = "psci"; 76 next-level-cache = <&L2>; 77 }; 78 79 L2: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 }; 83 }; 84 85 de: display-engine { 86 compatible = "allwinner,sun50i-a64-display-engine"; 87 allwinner,pipelines = <&mixer0>, 88 <&mixer1>; 89 status = "disabled"; 90 }; 91 92 osc24M: osc24M_clk { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 clock-frequency = <24000000>; 96 clock-output-names = "osc24M"; 97 }; 98 99 osc32k: osc32k_clk { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <32768>; 103 clock-output-names = "ext-osc32k"; 104 }; 105 106 pmu { 107 compatible = "arm,cortex-a53-pmu"; 108 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 112 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 113 }; 114 115 psci { 116 compatible = "arm,psci-0.2"; 117 method = "smc"; 118 }; 119 120 sound: sound { 121 compatible = "simple-audio-card"; 122 simple-audio-card,name = "sun50i-a64-audio"; 123 simple-audio-card,format = "i2s"; 124 simple-audio-card,frame-master = <&cpudai>; 125 simple-audio-card,bitclock-master = <&cpudai>; 126 simple-audio-card,mclk-fs = <128>; 127 simple-audio-card,aux-devs = <&codec_analog>; 128 simple-audio-card,routing = 129 "Left DAC", "AIF1 Slot 0 Left", 130 "Right DAC", "AIF1 Slot 0 Right", 131 "AIF1 Slot 0 Left ADC", "Left ADC", 132 "AIF1 Slot 0 Right ADC", "Right ADC"; 133 status = "disabled"; 134 135 cpudai: simple-audio-card,cpu { 136 sound-dai = <&dai>; 137 }; 138 139 link_codec: simple-audio-card,codec { 140 sound-dai = <&codec>; 141 }; 142 }; 143 144 sound_spdif { 145 compatible = "simple-audio-card"; 146 simple-audio-card,name = "On-board SPDIF"; 147 148 simple-audio-card,cpu { 149 sound-dai = <&spdif>; 150 }; 151 152 simple-audio-card,codec { 153 sound-dai = <&spdif_out>; 154 }; 155 }; 156 157 spdif_out: spdif-out { 158 #sound-dai-cells = <0>; 159 compatible = "linux,spdif-dit"; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 allwinner,erratum-unknown1; 165 interrupts = <GIC_PPI 13 166 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 167 <GIC_PPI 14 168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 169 <GIC_PPI 11 170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 171 <GIC_PPI 10 172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 173 }; 174 175 soc { 176 compatible = "simple-bus"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 ranges; 180 181 bus@1000000 { 182 compatible = "allwinner,sun50i-a64-de2"; 183 reg = <0x1000000 0x400000>; 184 allwinner,sram = <&de2_sram 1>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 ranges = <0 0x1000000 0x400000>; 188 189 display_clocks: clock@0 { 190 compatible = "allwinner,sun50i-a64-de2-clk"; 191 reg = <0x0 0x100000>; 192 clocks = <&ccu CLK_BUS_DE>, 193 <&ccu CLK_DE>; 194 clock-names = "bus", 195 "mod"; 196 resets = <&ccu RST_BUS_DE>; 197 #clock-cells = <1>; 198 #reset-cells = <1>; 199 }; 200 201 mixer0: mixer@100000 { 202 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 203 reg = <0x100000 0x100000>; 204 clocks = <&display_clocks CLK_BUS_MIXER0>, 205 <&display_clocks CLK_MIXER0>; 206 clock-names = "bus", 207 "mod"; 208 resets = <&display_clocks RST_MIXER0>; 209 210 ports { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 mixer0_out: port@1 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <1>; 218 219 mixer0_out_tcon0: endpoint@0 { 220 reg = <0>; 221 remote-endpoint = <&tcon0_in_mixer0>; 222 }; 223 224 mixer0_out_tcon1: endpoint@1 { 225 reg = <1>; 226 remote-endpoint = <&tcon1_in_mixer0>; 227 }; 228 }; 229 }; 230 }; 231 232 mixer1: mixer@200000 { 233 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 234 reg = <0x200000 0x100000>; 235 clocks = <&display_clocks CLK_BUS_MIXER1>, 236 <&display_clocks CLK_MIXER1>; 237 clock-names = "bus", 238 "mod"; 239 resets = <&display_clocks RST_MIXER1>; 240 241 ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 mixer1_out: port@1 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <1>; 249 250 mixer1_out_tcon0: endpoint@0 { 251 reg = <0>; 252 remote-endpoint = <&tcon0_in_mixer1>; 253 }; 254 255 mixer1_out_tcon1: endpoint@1 { 256 reg = <1>; 257 remote-endpoint = <&tcon1_in_mixer1>; 258 }; 259 }; 260 }; 261 }; 262 }; 263 264 syscon: syscon@1c00000 { 265 compatible = "allwinner,sun50i-a64-system-control"; 266 reg = <0x01c00000 0x1000>; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges; 270 271 sram_c: sram@18000 { 272 compatible = "mmio-sram"; 273 reg = <0x00018000 0x28000>; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges = <0 0x00018000 0x28000>; 277 278 de2_sram: sram-section@0 { 279 compatible = "allwinner,sun50i-a64-sram-c"; 280 reg = <0x0000 0x28000>; 281 }; 282 }; 283 284 sram_c1: sram@1d00000 { 285 compatible = "mmio-sram"; 286 reg = <0x01d00000 0x40000>; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges = <0 0x01d00000 0x40000>; 290 291 ve_sram: sram-section@0 { 292 compatible = "allwinner,sun50i-a64-sram-c1", 293 "allwinner,sun4i-a10-sram-c1"; 294 reg = <0x000000 0x40000>; 295 }; 296 }; 297 }; 298 299 dma: dma-controller@1c02000 { 300 compatible = "allwinner,sun50i-a64-dma"; 301 reg = <0x01c02000 0x1000>; 302 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&ccu CLK_BUS_DMA>; 304 dma-channels = <8>; 305 dma-requests = <27>; 306 resets = <&ccu RST_BUS_DMA>; 307 #dma-cells = <1>; 308 }; 309 310 tcon0: lcd-controller@1c0c000 { 311 compatible = "allwinner,sun50i-a64-tcon-lcd", 312 "allwinner,sun8i-a83t-tcon-lcd"; 313 reg = <0x01c0c000 0x1000>; 314 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 316 clock-names = "ahb", "tcon-ch0"; 317 clock-output-names = "tcon-pixel-clock"; 318 #clock-cells = <0>; 319 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 320 reset-names = "lcd", "lvds"; 321 322 ports { 323 #address-cells = <1>; 324 #size-cells = <0>; 325 326 tcon0_in: port@0 { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <0>; 330 331 tcon0_in_mixer0: endpoint@0 { 332 reg = <0>; 333 remote-endpoint = <&mixer0_out_tcon0>; 334 }; 335 336 tcon0_in_mixer1: endpoint@1 { 337 reg = <1>; 338 remote-endpoint = <&mixer1_out_tcon0>; 339 }; 340 }; 341 342 tcon0_out: port@1 { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 reg = <1>; 346 }; 347 }; 348 }; 349 350 tcon1: lcd-controller@1c0d000 { 351 compatible = "allwinner,sun50i-a64-tcon-tv", 352 "allwinner,sun8i-a83t-tcon-tv"; 353 reg = <0x01c0d000 0x1000>; 354 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 356 clock-names = "ahb", "tcon-ch1"; 357 resets = <&ccu RST_BUS_TCON1>; 358 reset-names = "lcd"; 359 360 ports { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 tcon1_in: port@0 { 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <0>; 368 369 tcon1_in_mixer0: endpoint@0 { 370 reg = <0>; 371 remote-endpoint = <&mixer0_out_tcon1>; 372 }; 373 374 tcon1_in_mixer1: endpoint@1 { 375 reg = <1>; 376 remote-endpoint = <&mixer1_out_tcon1>; 377 }; 378 }; 379 380 tcon1_out: port@1 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <1>; 384 385 tcon1_out_hdmi: endpoint@1 { 386 reg = <1>; 387 remote-endpoint = <&hdmi_in_tcon1>; 388 }; 389 }; 390 }; 391 }; 392 393 video-codec@1c0e000 { 394 compatible = "allwinner,sun50i-a64-video-engine"; 395 reg = <0x01c0e000 0x1000>; 396 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 397 <&ccu CLK_DRAM_VE>; 398 clock-names = "ahb", "mod", "ram"; 399 resets = <&ccu RST_BUS_VE>; 400 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 401 allwinner,sram = <&ve_sram 1>; 402 }; 403 404 mmc0: mmc@1c0f000 { 405 compatible = "allwinner,sun50i-a64-mmc"; 406 reg = <0x01c0f000 0x1000>; 407 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 408 clock-names = "ahb", "mmc"; 409 resets = <&ccu RST_BUS_MMC0>; 410 reset-names = "ahb"; 411 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 412 max-frequency = <150000000>; 413 status = "disabled"; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 }; 417 418 mmc1: mmc@1c10000 { 419 compatible = "allwinner,sun50i-a64-mmc"; 420 reg = <0x01c10000 0x1000>; 421 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 422 clock-names = "ahb", "mmc"; 423 resets = <&ccu RST_BUS_MMC1>; 424 reset-names = "ahb"; 425 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 426 max-frequency = <150000000>; 427 status = "disabled"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 432 mmc2: mmc@1c11000 { 433 compatible = "allwinner,sun50i-a64-emmc"; 434 reg = <0x01c11000 0x1000>; 435 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 436 clock-names = "ahb", "mmc"; 437 resets = <&ccu RST_BUS_MMC2>; 438 reset-names = "ahb"; 439 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 440 max-frequency = <200000000>; 441 status = "disabled"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 446 sid: eeprom@1c14000 { 447 compatible = "allwinner,sun50i-a64-sid"; 448 reg = <0x1c14000 0x400>; 449 }; 450 451 crypto: crypto@1c15000 { 452 compatible = "allwinner,sun50i-a64-crypto"; 453 reg = <0x01c15000 0x1000>; 454 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 456 clock-names = "bus", "mod"; 457 resets = <&ccu RST_BUS_CE>; 458 }; 459 460 usb_otg: usb@1c19000 { 461 compatible = "allwinner,sun8i-a33-musb"; 462 reg = <0x01c19000 0x0400>; 463 clocks = <&ccu CLK_BUS_OTG>; 464 resets = <&ccu RST_BUS_OTG>; 465 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-names = "mc"; 467 phys = <&usbphy 0>; 468 phy-names = "usb"; 469 extcon = <&usbphy 0>; 470 dr_mode = "otg"; 471 status = "disabled"; 472 }; 473 474 usbphy: phy@1c19400 { 475 compatible = "allwinner,sun50i-a64-usb-phy"; 476 reg = <0x01c19400 0x14>, 477 <0x01c1a800 0x4>, 478 <0x01c1b800 0x4>; 479 reg-names = "phy_ctrl", 480 "pmu0", 481 "pmu1"; 482 clocks = <&ccu CLK_USB_PHY0>, 483 <&ccu CLK_USB_PHY1>; 484 clock-names = "usb0_phy", 485 "usb1_phy"; 486 resets = <&ccu RST_USB_PHY0>, 487 <&ccu RST_USB_PHY1>; 488 reset-names = "usb0_reset", 489 "usb1_reset"; 490 status = "disabled"; 491 #phy-cells = <1>; 492 }; 493 494 ehci0: usb@1c1a000 { 495 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 496 reg = <0x01c1a000 0x100>; 497 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&ccu CLK_BUS_OHCI0>, 499 <&ccu CLK_BUS_EHCI0>, 500 <&ccu CLK_USB_OHCI0>; 501 resets = <&ccu RST_BUS_OHCI0>, 502 <&ccu RST_BUS_EHCI0>; 503 status = "disabled"; 504 }; 505 506 ohci0: usb@1c1a400 { 507 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 508 reg = <0x01c1a400 0x100>; 509 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&ccu CLK_BUS_OHCI0>, 511 <&ccu CLK_USB_OHCI0>; 512 resets = <&ccu RST_BUS_OHCI0>; 513 status = "disabled"; 514 }; 515 516 ehci1: usb@1c1b000 { 517 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 518 reg = <0x01c1b000 0x100>; 519 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&ccu CLK_BUS_OHCI1>, 521 <&ccu CLK_BUS_EHCI1>, 522 <&ccu CLK_USB_OHCI1>; 523 resets = <&ccu RST_BUS_OHCI1>, 524 <&ccu RST_BUS_EHCI1>; 525 phys = <&usbphy 1>; 526 phy-names = "usb"; 527 status = "disabled"; 528 }; 529 530 ohci1: usb@1c1b400 { 531 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 532 reg = <0x01c1b400 0x100>; 533 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&ccu CLK_BUS_OHCI1>, 535 <&ccu CLK_USB_OHCI1>; 536 resets = <&ccu RST_BUS_OHCI1>; 537 phys = <&usbphy 1>; 538 phy-names = "usb"; 539 status = "disabled"; 540 }; 541 542 ccu: clock@1c20000 { 543 compatible = "allwinner,sun50i-a64-ccu"; 544 reg = <0x01c20000 0x400>; 545 clocks = <&osc24M>, <&rtc 0>; 546 clock-names = "hosc", "losc"; 547 #clock-cells = <1>; 548 #reset-cells = <1>; 549 }; 550 551 pio: pinctrl@1c20800 { 552 compatible = "allwinner,sun50i-a64-pinctrl"; 553 reg = <0x01c20800 0x400>; 554 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 558 clock-names = "apb", "hosc", "losc"; 559 gpio-controller; 560 #gpio-cells = <3>; 561 interrupt-controller; 562 #interrupt-cells = <3>; 563 564 csi_pins: csi-pins { 565 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 566 "PE7", "PE8", "PE9", "PE10", "PE11"; 567 function = "csi"; 568 }; 569 570 /omit-if-no-ref/ 571 csi_mclk_pin: csi-mclk-pin { 572 pins = "PE1"; 573 function = "csi"; 574 }; 575 576 i2c0_pins: i2c0-pins { 577 pins = "PH0", "PH1"; 578 function = "i2c0"; 579 }; 580 581 i2c1_pins: i2c1-pins { 582 pins = "PH2", "PH3"; 583 function = "i2c1"; 584 }; 585 586 /omit-if-no-ref/ 587 lcd_rgb666_pins: lcd-rgb666-pins { 588 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 589 "PD5", "PD6", "PD7", "PD8", "PD9", 590 "PD10", "PD11", "PD12", "PD13", 591 "PD14", "PD15", "PD16", "PD17", 592 "PD18", "PD19", "PD20", "PD21"; 593 function = "lcd0"; 594 }; 595 596 mmc0_pins: mmc0-pins { 597 pins = "PF0", "PF1", "PF2", "PF3", 598 "PF4", "PF5"; 599 function = "mmc0"; 600 drive-strength = <30>; 601 bias-pull-up; 602 }; 603 604 mmc1_pins: mmc1-pins { 605 pins = "PG0", "PG1", "PG2", "PG3", 606 "PG4", "PG5"; 607 function = "mmc1"; 608 drive-strength = <30>; 609 bias-pull-up; 610 }; 611 612 mmc2_pins: mmc2-pins { 613 pins = "PC5", "PC6", "PC8", "PC9", 614 "PC10","PC11", "PC12", "PC13", 615 "PC14", "PC15", "PC16"; 616 function = "mmc2"; 617 drive-strength = <30>; 618 bias-pull-up; 619 }; 620 621 mmc2_ds_pin: mmc2-ds-pin { 622 pins = "PC1"; 623 function = "mmc2"; 624 drive-strength = <30>; 625 bias-pull-up; 626 }; 627 628 pwm_pin: pwm-pin { 629 pins = "PD22"; 630 function = "pwm"; 631 }; 632 633 rmii_pins: rmii-pins { 634 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 635 "PD18", "PD19", "PD20", "PD22", "PD23"; 636 function = "emac"; 637 drive-strength = <40>; 638 }; 639 640 rgmii_pins: rgmii-pins { 641 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 642 "PD13", "PD15", "PD16", "PD17", "PD18", 643 "PD19", "PD20", "PD21", "PD22", "PD23"; 644 function = "emac"; 645 drive-strength = <40>; 646 }; 647 648 spdif_tx_pin: spdif-tx-pin { 649 pins = "PH8"; 650 function = "spdif"; 651 }; 652 653 spi0_pins: spi0-pins { 654 pins = "PC0", "PC1", "PC2", "PC3"; 655 function = "spi0"; 656 }; 657 658 spi1_pins: spi1-pins { 659 pins = "PD0", "PD1", "PD2", "PD3"; 660 function = "spi1"; 661 }; 662 663 uart0_pb_pins: uart0-pb-pins { 664 pins = "PB8", "PB9"; 665 function = "uart0"; 666 }; 667 668 uart1_pins: uart1-pins { 669 pins = "PG6", "PG7"; 670 function = "uart1"; 671 }; 672 673 uart1_rts_cts_pins: uart1-rts-cts-pins { 674 pins = "PG8", "PG9"; 675 function = "uart1"; 676 }; 677 678 uart2_pins: uart2-pins { 679 pins = "PB0", "PB1"; 680 function = "uart2"; 681 }; 682 683 uart3_pins: uart3-pins { 684 pins = "PD0", "PD1"; 685 function = "uart3"; 686 }; 687 688 uart4_pins: uart4-pins { 689 pins = "PD2", "PD3"; 690 function = "uart4"; 691 }; 692 693 uart4_rts_cts_pins: uart4-rts-cts-pins { 694 pins = "PD4", "PD5"; 695 function = "uart4"; 696 }; 697 }; 698 699 spdif: spdif@1c21000 { 700 #sound-dai-cells = <0>; 701 compatible = "allwinner,sun50i-a64-spdif", 702 "allwinner,sun8i-h3-spdif"; 703 reg = <0x01c21000 0x400>; 704 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 706 resets = <&ccu RST_BUS_SPDIF>; 707 clock-names = "apb", "spdif"; 708 dmas = <&dma 2>; 709 dma-names = "tx"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&spdif_tx_pin>; 712 status = "disabled"; 713 }; 714 715 lradc: lradc@1c21800 { 716 compatible = "allwinner,sun50i-a64-lradc", 717 "allwinner,sun8i-a83t-r-lradc"; 718 reg = <0x01c21800 0x400>; 719 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 720 status = "disabled"; 721 }; 722 723 i2s0: i2s@1c22000 { 724 #sound-dai-cells = <0>; 725 compatible = "allwinner,sun50i-a64-i2s", 726 "allwinner,sun8i-h3-i2s"; 727 reg = <0x01c22000 0x400>; 728 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 730 clock-names = "apb", "mod"; 731 resets = <&ccu RST_BUS_I2S0>; 732 dma-names = "rx", "tx"; 733 dmas = <&dma 3>, <&dma 3>; 734 status = "disabled"; 735 }; 736 737 i2s1: i2s@1c22400 { 738 #sound-dai-cells = <0>; 739 compatible = "allwinner,sun50i-a64-i2s", 740 "allwinner,sun8i-h3-i2s"; 741 reg = <0x01c22400 0x400>; 742 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 744 clock-names = "apb", "mod"; 745 resets = <&ccu RST_BUS_I2S1>; 746 dma-names = "rx", "tx"; 747 dmas = <&dma 4>, <&dma 4>; 748 status = "disabled"; 749 }; 750 751 dai: dai@1c22c00 { 752 #sound-dai-cells = <0>; 753 compatible = "allwinner,sun50i-a64-codec-i2s"; 754 reg = <0x01c22c00 0x200>; 755 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 757 clock-names = "apb", "mod"; 758 resets = <&ccu RST_BUS_CODEC>; 759 dmas = <&dma 15>, <&dma 15>; 760 dma-names = "rx", "tx"; 761 status = "disabled"; 762 }; 763 764 codec: codec@1c22e00 { 765 #sound-dai-cells = <0>; 766 compatible = "allwinner,sun8i-a33-codec"; 767 reg = <0x01c22e00 0x600>; 768 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 770 clock-names = "bus", "mod"; 771 status = "disabled"; 772 }; 773 774 uart0: serial@1c28000 { 775 compatible = "snps,dw-apb-uart"; 776 reg = <0x01c28000 0x400>; 777 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 778 reg-shift = <2>; 779 reg-io-width = <4>; 780 clocks = <&ccu CLK_BUS_UART0>; 781 resets = <&ccu RST_BUS_UART0>; 782 status = "disabled"; 783 }; 784 785 uart1: serial@1c28400 { 786 compatible = "snps,dw-apb-uart"; 787 reg = <0x01c28400 0x400>; 788 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 789 reg-shift = <2>; 790 reg-io-width = <4>; 791 clocks = <&ccu CLK_BUS_UART1>; 792 resets = <&ccu RST_BUS_UART1>; 793 status = "disabled"; 794 }; 795 796 uart2: serial@1c28800 { 797 compatible = "snps,dw-apb-uart"; 798 reg = <0x01c28800 0x400>; 799 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 800 reg-shift = <2>; 801 reg-io-width = <4>; 802 clocks = <&ccu CLK_BUS_UART2>; 803 resets = <&ccu RST_BUS_UART2>; 804 status = "disabled"; 805 }; 806 807 uart3: serial@1c28c00 { 808 compatible = "snps,dw-apb-uart"; 809 reg = <0x01c28c00 0x400>; 810 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 811 reg-shift = <2>; 812 reg-io-width = <4>; 813 clocks = <&ccu CLK_BUS_UART3>; 814 resets = <&ccu RST_BUS_UART3>; 815 status = "disabled"; 816 }; 817 818 uart4: serial@1c29000 { 819 compatible = "snps,dw-apb-uart"; 820 reg = <0x01c29000 0x400>; 821 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 822 reg-shift = <2>; 823 reg-io-width = <4>; 824 clocks = <&ccu CLK_BUS_UART4>; 825 resets = <&ccu RST_BUS_UART4>; 826 status = "disabled"; 827 }; 828 829 i2c0: i2c@1c2ac00 { 830 compatible = "allwinner,sun6i-a31-i2c"; 831 reg = <0x01c2ac00 0x400>; 832 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&ccu CLK_BUS_I2C0>; 834 resets = <&ccu RST_BUS_I2C0>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&i2c0_pins>; 837 status = "disabled"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 }; 841 842 i2c1: i2c@1c2b000 { 843 compatible = "allwinner,sun6i-a31-i2c"; 844 reg = <0x01c2b000 0x400>; 845 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&ccu CLK_BUS_I2C1>; 847 resets = <&ccu RST_BUS_I2C1>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&i2c1_pins>; 850 status = "disabled"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 }; 854 855 i2c2: i2c@1c2b400 { 856 compatible = "allwinner,sun6i-a31-i2c"; 857 reg = <0x01c2b400 0x400>; 858 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&ccu CLK_BUS_I2C2>; 860 resets = <&ccu RST_BUS_I2C2>; 861 status = "disabled"; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 }; 865 866 867 spi0: spi@1c68000 { 868 compatible = "allwinner,sun8i-h3-spi"; 869 reg = <0x01c68000 0x1000>; 870 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 872 clock-names = "ahb", "mod"; 873 dmas = <&dma 23>, <&dma 23>; 874 dma-names = "rx", "tx"; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&spi0_pins>; 877 resets = <&ccu RST_BUS_SPI0>; 878 status = "disabled"; 879 num-cs = <1>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 }; 883 884 spi1: spi@1c69000 { 885 compatible = "allwinner,sun8i-h3-spi"; 886 reg = <0x01c69000 0x1000>; 887 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 889 clock-names = "ahb", "mod"; 890 dmas = <&dma 24>, <&dma 24>; 891 dma-names = "rx", "tx"; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&spi1_pins>; 894 resets = <&ccu RST_BUS_SPI1>; 895 status = "disabled"; 896 num-cs = <1>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 }; 900 901 emac: ethernet@1c30000 { 902 compatible = "allwinner,sun50i-a64-emac"; 903 syscon = <&syscon>; 904 reg = <0x01c30000 0x10000>; 905 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "macirq"; 907 resets = <&ccu RST_BUS_EMAC>; 908 reset-names = "stmmaceth"; 909 clocks = <&ccu CLK_BUS_EMAC>; 910 clock-names = "stmmaceth"; 911 status = "disabled"; 912 913 mdio: mdio { 914 compatible = "snps,dwmac-mdio"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 }; 918 }; 919 920 mali: gpu@1c40000 { 921 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 922 reg = <0x01c40000 0x10000>; 923 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "gp", 931 "gpmmu", 932 "pp0", 933 "ppmmu0", 934 "pp1", 935 "ppmmu1", 936 "pmu"; 937 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 938 clock-names = "bus", "core"; 939 resets = <&ccu RST_BUS_GPU>; 940 }; 941 942 gic: interrupt-controller@1c81000 { 943 compatible = "arm,gic-400"; 944 reg = <0x01c81000 0x1000>, 945 <0x01c82000 0x2000>, 946 <0x01c84000 0x2000>, 947 <0x01c86000 0x2000>; 948 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 949 interrupt-controller; 950 #interrupt-cells = <3>; 951 }; 952 953 pwm: pwm@1c21400 { 954 compatible = "allwinner,sun50i-a64-pwm", 955 "allwinner,sun5i-a13-pwm"; 956 reg = <0x01c21400 0x400>; 957 clocks = <&osc24M>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&pwm_pin>; 960 #pwm-cells = <3>; 961 status = "disabled"; 962 }; 963 964 csi: csi@1cb0000 { 965 compatible = "allwinner,sun50i-a64-csi"; 966 reg = <0x01cb0000 0x1000>; 967 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&ccu CLK_BUS_CSI>, 969 <&ccu CLK_CSI_SCLK>, 970 <&ccu CLK_DRAM_CSI>; 971 clock-names = "bus", "mod", "ram"; 972 resets = <&ccu RST_BUS_CSI>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&csi_pins>; 975 status = "disabled"; 976 }; 977 978 hdmi: hdmi@1ee0000 { 979 compatible = "allwinner,sun50i-a64-dw-hdmi", 980 "allwinner,sun8i-a83t-dw-hdmi"; 981 reg = <0x01ee0000 0x10000>; 982 reg-io-width = <1>; 983 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 985 <&ccu CLK_HDMI>; 986 clock-names = "iahb", "isfr", "tmds"; 987 resets = <&ccu RST_BUS_HDMI1>; 988 reset-names = "ctrl"; 989 phys = <&hdmi_phy>; 990 phy-names = "phy"; 991 status = "disabled"; 992 993 ports { 994 #address-cells = <1>; 995 #size-cells = <0>; 996 997 hdmi_in: port@0 { 998 reg = <0>; 999 1000 hdmi_in_tcon1: endpoint { 1001 remote-endpoint = <&tcon1_out_hdmi>; 1002 }; 1003 }; 1004 1005 hdmi_out: port@1 { 1006 reg = <1>; 1007 }; 1008 }; 1009 }; 1010 1011 hdmi_phy: hdmi-phy@1ef0000 { 1012 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1013 reg = <0x01ef0000 0x10000>; 1014 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1015 <&ccu 7>; 1016 clock-names = "bus", "mod", "pll-0"; 1017 resets = <&ccu RST_BUS_HDMI0>; 1018 reset-names = "phy"; 1019 #phy-cells = <0>; 1020 }; 1021 1022 rtc: rtc@1f00000 { 1023 compatible = "allwinner,sun50i-a64-rtc", 1024 "allwinner,sun8i-h3-rtc"; 1025 reg = <0x01f00000 0x400>; 1026 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1028 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1029 clocks = <&osc32k>; 1030 #clock-cells = <1>; 1031 }; 1032 1033 r_intc: interrupt-controller@1f00c00 { 1034 compatible = "allwinner,sun50i-a64-r-intc", 1035 "allwinner,sun6i-a31-r-intc"; 1036 interrupt-controller; 1037 #interrupt-cells = <2>; 1038 reg = <0x01f00c00 0x400>; 1039 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1040 }; 1041 1042 r_ccu: clock@1f01400 { 1043 compatible = "allwinner,sun50i-a64-r-ccu"; 1044 reg = <0x01f01400 0x100>; 1045 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1046 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1047 #clock-cells = <1>; 1048 #reset-cells = <1>; 1049 }; 1050 1051 codec_analog: codec-analog@1f015c0 { 1052 compatible = "allwinner,sun50i-a64-codec-analog"; 1053 reg = <0x01f015c0 0x4>; 1054 status = "disabled"; 1055 }; 1056 1057 r_i2c: i2c@1f02400 { 1058 compatible = "allwinner,sun50i-a64-i2c", 1059 "allwinner,sun6i-a31-i2c"; 1060 reg = <0x01f02400 0x400>; 1061 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&r_ccu CLK_APB0_I2C>; 1063 resets = <&r_ccu RST_APB0_I2C>; 1064 status = "disabled"; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 }; 1068 1069 r_ir: ir@1f02000 { 1070 compatible = "allwinner,sun50i-a64-ir", 1071 "allwinner,sun6i-a31-ir"; 1072 reg = <0x01f02000 0x400>; 1073 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1074 clock-names = "apb", "ir"; 1075 resets = <&r_ccu RST_APB0_IR>; 1076 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&r_ir_rx_pin>; 1079 status = "disabled"; 1080 }; 1081 1082 r_pwm: pwm@1f03800 { 1083 compatible = "allwinner,sun50i-a64-pwm", 1084 "allwinner,sun5i-a13-pwm"; 1085 reg = <0x01f03800 0x400>; 1086 clocks = <&osc24M>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&r_pwm_pin>; 1089 #pwm-cells = <3>; 1090 status = "disabled"; 1091 }; 1092 1093 r_pio: pinctrl@1f02c00 { 1094 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1095 reg = <0x01f02c00 0x400>; 1096 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1098 clock-names = "apb", "hosc", "losc"; 1099 gpio-controller; 1100 #gpio-cells = <3>; 1101 interrupt-controller; 1102 #interrupt-cells = <3>; 1103 1104 r_i2c_pl89_pins: r-i2c-pl89-pins { 1105 pins = "PL8", "PL9"; 1106 function = "s_i2c"; 1107 }; 1108 1109 r_ir_rx_pin: r-ir-rx-pin { 1110 pins = "PL11"; 1111 function = "s_cir_rx"; 1112 }; 1113 1114 r_pwm_pin: r-pwm-pin { 1115 pins = "PL10"; 1116 function = "s_pwm"; 1117 }; 1118 1119 r_rsb_pins: r-rsb-pins { 1120 pins = "PL0", "PL1"; 1121 function = "s_rsb"; 1122 }; 1123 }; 1124 1125 r_rsb: rsb@1f03400 { 1126 compatible = "allwinner,sun8i-a23-rsb"; 1127 reg = <0x01f03400 0x400>; 1128 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&r_ccu 6>; 1130 clock-frequency = <3000000>; 1131 resets = <&r_ccu 2>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&r_rsb_pins>; 1134 status = "disabled"; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 }; 1138 1139 wdt0: watchdog@1c20ca0 { 1140 compatible = "allwinner,sun50i-a64-wdt", 1141 "allwinner,sun6i-a31-wdt"; 1142 reg = <0x01c20ca0 0x20>; 1143 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&osc24M>; 1145 }; 1146 }; 1147}; 1148