1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 bus@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_DE>, 232 <&ccu CLK_BUS_DE>; 233 clock-names = "mod", 234 "bus"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <1>; 257 258 mixer0_out_tcon0: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&tcon0_in_mixer0>; 261 }; 262 263 mixer0_out_tcon1: endpoint@1 { 264 reg = <1>; 265 remote-endpoint = <&tcon1_in_mixer0>; 266 }; 267 }; 268 }; 269 }; 270 271 mixer1: mixer@200000 { 272 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273 reg = <0x200000 0x100000>; 274 clocks = <&display_clocks CLK_BUS_MIXER1>, 275 <&display_clocks CLK_MIXER1>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&display_clocks RST_MIXER1>; 279 280 ports { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 mixer1_out: port@1 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <1>; 288 289 mixer1_out_tcon0: endpoint@0 { 290 reg = <0>; 291 remote-endpoint = <&tcon0_in_mixer1>; 292 }; 293 294 mixer1_out_tcon1: endpoint@1 { 295 reg = <1>; 296 remote-endpoint = <&tcon1_in_mixer1>; 297 }; 298 }; 299 }; 300 }; 301 }; 302 303 syscon: syscon@1c00000 { 304 compatible = "allwinner,sun50i-a64-system-control"; 305 reg = <0x01c00000 0x1000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges; 309 310 sram_c: sram@18000 { 311 compatible = "mmio-sram"; 312 reg = <0x00018000 0x28000>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0 0x00018000 0x28000>; 316 317 de2_sram: sram-section@0 { 318 compatible = "allwinner,sun50i-a64-sram-c"; 319 reg = <0x0000 0x28000>; 320 }; 321 }; 322 323 sram_c1: sram@1d00000 { 324 compatible = "mmio-sram"; 325 reg = <0x01d00000 0x40000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0 0x01d00000 0x40000>; 329 330 ve_sram: sram-section@0 { 331 compatible = "allwinner,sun50i-a64-sram-c1", 332 "allwinner,sun4i-a10-sram-c1"; 333 reg = <0x000000 0x40000>; 334 }; 335 }; 336 }; 337 338 dma: dma-controller@1c02000 { 339 compatible = "allwinner,sun50i-a64-dma"; 340 reg = <0x01c02000 0x1000>; 341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&ccu CLK_BUS_DMA>; 343 dma-channels = <8>; 344 dma-requests = <27>; 345 resets = <&ccu RST_BUS_DMA>; 346 #dma-cells = <1>; 347 }; 348 349 tcon0: lcd-controller@1c0c000 { 350 compatible = "allwinner,sun50i-a64-tcon-lcd", 351 "allwinner,sun8i-a83t-tcon-lcd"; 352 reg = <0x01c0c000 0x1000>; 353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 355 clock-names = "ahb", "tcon-ch0"; 356 clock-output-names = "tcon-pixel-clock"; 357 #clock-cells = <0>; 358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 359 reset-names = "lcd", "lvds"; 360 361 ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 tcon0_in: port@0 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0>; 369 370 tcon0_in_mixer0: endpoint@0 { 371 reg = <0>; 372 remote-endpoint = <&mixer0_out_tcon0>; 373 }; 374 375 tcon0_in_mixer1: endpoint@1 { 376 reg = <1>; 377 remote-endpoint = <&mixer1_out_tcon0>; 378 }; 379 }; 380 381 tcon0_out: port@1 { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <1>; 385 }; 386 }; 387 }; 388 389 tcon1: lcd-controller@1c0d000 { 390 compatible = "allwinner,sun50i-a64-tcon-tv", 391 "allwinner,sun8i-a83t-tcon-tv"; 392 reg = <0x01c0d000 0x1000>; 393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 395 clock-names = "ahb", "tcon-ch1"; 396 resets = <&ccu RST_BUS_TCON1>; 397 reset-names = "lcd"; 398 399 ports { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 tcon1_in: port@0 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0>; 407 408 tcon1_in_mixer0: endpoint@0 { 409 reg = <0>; 410 remote-endpoint = <&mixer0_out_tcon1>; 411 }; 412 413 tcon1_in_mixer1: endpoint@1 { 414 reg = <1>; 415 remote-endpoint = <&mixer1_out_tcon1>; 416 }; 417 }; 418 419 tcon1_out: port@1 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <1>; 423 424 tcon1_out_hdmi: endpoint@1 { 425 reg = <1>; 426 remote-endpoint = <&hdmi_in_tcon1>; 427 }; 428 }; 429 }; 430 }; 431 432 video-codec@1c0e000 { 433 compatible = "allwinner,sun50i-a64-video-engine"; 434 reg = <0x01c0e000 0x1000>; 435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 436 <&ccu CLK_DRAM_VE>; 437 clock-names = "ahb", "mod", "ram"; 438 resets = <&ccu RST_BUS_VE>; 439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 440 allwinner,sram = <&ve_sram 1>; 441 }; 442 443 mmc0: mmc@1c0f000 { 444 compatible = "allwinner,sun50i-a64-mmc"; 445 reg = <0x01c0f000 0x1000>; 446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 447 clock-names = "ahb", "mmc"; 448 resets = <&ccu RST_BUS_MMC0>; 449 reset-names = "ahb"; 450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 451 max-frequency = <150000000>; 452 status = "disabled"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 }; 456 457 mmc1: mmc@1c10000 { 458 compatible = "allwinner,sun50i-a64-mmc"; 459 reg = <0x01c10000 0x1000>; 460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 461 clock-names = "ahb", "mmc"; 462 resets = <&ccu RST_BUS_MMC1>; 463 reset-names = "ahb"; 464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 465 max-frequency = <150000000>; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 mmc2: mmc@1c11000 { 472 compatible = "allwinner,sun50i-a64-emmc"; 473 reg = <0x01c11000 0x1000>; 474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 475 clock-names = "ahb", "mmc"; 476 resets = <&ccu RST_BUS_MMC2>; 477 reset-names = "ahb"; 478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 479 max-frequency = <200000000>; 480 status = "disabled"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 }; 484 485 sid: eeprom@1c14000 { 486 compatible = "allwinner,sun50i-a64-sid"; 487 reg = <0x1c14000 0x400>; 488 }; 489 490 usb_otg: usb@1c19000 { 491 compatible = "allwinner,sun8i-a33-musb"; 492 reg = <0x01c19000 0x0400>; 493 clocks = <&ccu CLK_BUS_OTG>; 494 resets = <&ccu RST_BUS_OTG>; 495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "mc"; 497 phys = <&usbphy 0>; 498 phy-names = "usb"; 499 extcon = <&usbphy 0>; 500 dr_mode = "otg"; 501 status = "disabled"; 502 }; 503 504 usbphy: phy@1c19400 { 505 compatible = "allwinner,sun50i-a64-usb-phy"; 506 reg = <0x01c19400 0x14>, 507 <0x01c1a800 0x4>, 508 <0x01c1b800 0x4>; 509 reg-names = "phy_ctrl", 510 "pmu0", 511 "pmu1"; 512 clocks = <&ccu CLK_USB_PHY0>, 513 <&ccu CLK_USB_PHY1>; 514 clock-names = "usb0_phy", 515 "usb1_phy"; 516 resets = <&ccu RST_USB_PHY0>, 517 <&ccu RST_USB_PHY1>; 518 reset-names = "usb0_reset", 519 "usb1_reset"; 520 status = "disabled"; 521 #phy-cells = <1>; 522 }; 523 524 ehci0: usb@1c1a000 { 525 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 526 reg = <0x01c1a000 0x100>; 527 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&ccu CLK_BUS_OHCI0>, 529 <&ccu CLK_BUS_EHCI0>, 530 <&ccu CLK_USB_OHCI0>; 531 resets = <&ccu RST_BUS_OHCI0>, 532 <&ccu RST_BUS_EHCI0>; 533 status = "disabled"; 534 }; 535 536 ohci0: usb@1c1a400 { 537 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 538 reg = <0x01c1a400 0x100>; 539 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&ccu CLK_BUS_OHCI0>, 541 <&ccu CLK_USB_OHCI0>; 542 resets = <&ccu RST_BUS_OHCI0>; 543 status = "disabled"; 544 }; 545 546 ehci1: usb@1c1b000 { 547 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 548 reg = <0x01c1b000 0x100>; 549 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&ccu CLK_BUS_OHCI1>, 551 <&ccu CLK_BUS_EHCI1>, 552 <&ccu CLK_USB_OHCI1>; 553 resets = <&ccu RST_BUS_OHCI1>, 554 <&ccu RST_BUS_EHCI1>; 555 phys = <&usbphy 1>; 556 status = "disabled"; 557 }; 558 559 ohci1: usb@1c1b400 { 560 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 561 reg = <0x01c1b400 0x100>; 562 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&ccu CLK_BUS_OHCI1>, 564 <&ccu CLK_USB_OHCI1>; 565 resets = <&ccu RST_BUS_OHCI1>; 566 phys = <&usbphy 1>; 567 status = "disabled"; 568 }; 569 570 ccu: clock@1c20000 { 571 compatible = "allwinner,sun50i-a64-ccu"; 572 reg = <0x01c20000 0x400>; 573 clocks = <&osc24M>, <&rtc 0>; 574 clock-names = "hosc", "losc"; 575 #clock-cells = <1>; 576 #reset-cells = <1>; 577 }; 578 579 pio: pinctrl@1c20800 { 580 compatible = "allwinner,sun50i-a64-pinctrl"; 581 reg = <0x01c20800 0x400>; 582 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 586 clock-names = "apb", "hosc", "losc"; 587 gpio-controller; 588 #gpio-cells = <3>; 589 interrupt-controller; 590 #interrupt-cells = <3>; 591 592 csi_pins: csi-pins { 593 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 594 "PE7", "PE8", "PE9", "PE10", "PE11"; 595 function = "csi"; 596 }; 597 598 /omit-if-no-ref/ 599 csi_mclk_pin: csi-mclk-pin { 600 pins = "PE1"; 601 function = "csi"; 602 }; 603 604 i2c0_pins: i2c0-pins { 605 pins = "PH0", "PH1"; 606 function = "i2c0"; 607 }; 608 609 i2c1_pins: i2c1-pins { 610 pins = "PH2", "PH3"; 611 function = "i2c1"; 612 }; 613 614 /omit-if-no-ref/ 615 lcd_rgb666_pins: lcd-rgb666-pins { 616 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 617 "PD5", "PD6", "PD7", "PD8", "PD9", 618 "PD10", "PD11", "PD12", "PD13", 619 "PD14", "PD15", "PD16", "PD17", 620 "PD18", "PD19", "PD20", "PD21"; 621 function = "lcd0"; 622 }; 623 624 mmc0_pins: mmc0-pins { 625 pins = "PF0", "PF1", "PF2", "PF3", 626 "PF4", "PF5"; 627 function = "mmc0"; 628 drive-strength = <30>; 629 bias-pull-up; 630 }; 631 632 mmc1_pins: mmc1-pins { 633 pins = "PG0", "PG1", "PG2", "PG3", 634 "PG4", "PG5"; 635 function = "mmc1"; 636 drive-strength = <30>; 637 bias-pull-up; 638 }; 639 640 mmc2_pins: mmc2-pins { 641 pins = "PC5", "PC6", "PC8", "PC9", 642 "PC10","PC11", "PC12", "PC13", 643 "PC14", "PC15", "PC16"; 644 function = "mmc2"; 645 drive-strength = <30>; 646 bias-pull-up; 647 }; 648 649 mmc2_ds_pin: mmc2-ds-pin { 650 pins = "PC1"; 651 function = "mmc2"; 652 drive-strength = <30>; 653 bias-pull-up; 654 }; 655 656 pwm_pin: pwm-pin { 657 pins = "PD22"; 658 function = "pwm"; 659 }; 660 661 rmii_pins: rmii-pins { 662 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 663 "PD18", "PD19", "PD20", "PD22", "PD23"; 664 function = "emac"; 665 drive-strength = <40>; 666 }; 667 668 rgmii_pins: rgmii-pins { 669 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 670 "PD13", "PD15", "PD16", "PD17", "PD18", 671 "PD19", "PD20", "PD21", "PD22", "PD23"; 672 function = "emac"; 673 drive-strength = <40>; 674 }; 675 676 spdif_tx_pin: spdif-tx-pin { 677 pins = "PH8"; 678 function = "spdif"; 679 }; 680 681 spi0_pins: spi0-pins { 682 pins = "PC0", "PC1", "PC2", "PC3"; 683 function = "spi0"; 684 }; 685 686 spi1_pins: spi1-pins { 687 pins = "PD0", "PD1", "PD2", "PD3"; 688 function = "spi1"; 689 }; 690 691 uart0_pb_pins: uart0-pb-pins { 692 pins = "PB8", "PB9"; 693 function = "uart0"; 694 }; 695 696 uart1_pins: uart1-pins { 697 pins = "PG6", "PG7"; 698 function = "uart1"; 699 }; 700 701 uart1_rts_cts_pins: uart1-rts-cts-pins { 702 pins = "PG8", "PG9"; 703 function = "uart1"; 704 }; 705 706 uart2_pins: uart2-pins { 707 pins = "PB0", "PB1"; 708 function = "uart2"; 709 }; 710 711 uart3_pins: uart3-pins { 712 pins = "PD0", "PD1"; 713 function = "uart3"; 714 }; 715 716 uart4_pins: uart4-pins { 717 pins = "PD2", "PD3"; 718 function = "uart4"; 719 }; 720 721 uart4_rts_cts_pins: uart4-rts-cts-pins { 722 pins = "PD4", "PD5"; 723 function = "uart4"; 724 }; 725 }; 726 727 spdif: spdif@1c21000 { 728 #sound-dai-cells = <0>; 729 compatible = "allwinner,sun50i-a64-spdif", 730 "allwinner,sun8i-h3-spdif"; 731 reg = <0x01c21000 0x400>; 732 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 734 resets = <&ccu RST_BUS_SPDIF>; 735 clock-names = "apb", "spdif"; 736 dmas = <&dma 2>; 737 dma-names = "tx"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&spdif_tx_pin>; 740 status = "disabled"; 741 }; 742 743 i2s0: i2s@1c22000 { 744 #sound-dai-cells = <0>; 745 compatible = "allwinner,sun50i-a64-i2s", 746 "allwinner,sun8i-h3-i2s"; 747 reg = <0x01c22000 0x400>; 748 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 750 clock-names = "apb", "mod"; 751 resets = <&ccu RST_BUS_I2S0>; 752 dma-names = "rx", "tx"; 753 dmas = <&dma 3>, <&dma 3>; 754 status = "disabled"; 755 }; 756 757 i2s1: i2s@1c22400 { 758 #sound-dai-cells = <0>; 759 compatible = "allwinner,sun50i-a64-i2s", 760 "allwinner,sun8i-h3-i2s"; 761 reg = <0x01c22400 0x400>; 762 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 764 clock-names = "apb", "mod"; 765 resets = <&ccu RST_BUS_I2S1>; 766 dma-names = "rx", "tx"; 767 dmas = <&dma 4>, <&dma 4>; 768 status = "disabled"; 769 }; 770 771 dai: dai@1c22c00 { 772 #sound-dai-cells = <0>; 773 compatible = "allwinner,sun50i-a64-codec-i2s"; 774 reg = <0x01c22c00 0x200>; 775 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 777 clock-names = "apb", "mod"; 778 resets = <&ccu RST_BUS_CODEC>; 779 dmas = <&dma 15>, <&dma 15>; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 782 }; 783 784 codec: codec@1c22e00 { 785 #sound-dai-cells = <0>; 786 compatible = "allwinner,sun8i-a33-codec"; 787 reg = <0x01c22e00 0x600>; 788 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 790 clock-names = "bus", "mod"; 791 status = "disabled"; 792 }; 793 794 uart0: serial@1c28000 { 795 compatible = "snps,dw-apb-uart"; 796 reg = <0x01c28000 0x400>; 797 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 798 reg-shift = <2>; 799 reg-io-width = <4>; 800 clocks = <&ccu CLK_BUS_UART0>; 801 resets = <&ccu RST_BUS_UART0>; 802 status = "disabled"; 803 }; 804 805 uart1: serial@1c28400 { 806 compatible = "snps,dw-apb-uart"; 807 reg = <0x01c28400 0x400>; 808 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 809 reg-shift = <2>; 810 reg-io-width = <4>; 811 clocks = <&ccu CLK_BUS_UART1>; 812 resets = <&ccu RST_BUS_UART1>; 813 status = "disabled"; 814 }; 815 816 uart2: serial@1c28800 { 817 compatible = "snps,dw-apb-uart"; 818 reg = <0x01c28800 0x400>; 819 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 820 reg-shift = <2>; 821 reg-io-width = <4>; 822 clocks = <&ccu CLK_BUS_UART2>; 823 resets = <&ccu RST_BUS_UART2>; 824 status = "disabled"; 825 }; 826 827 uart3: serial@1c28c00 { 828 compatible = "snps,dw-apb-uart"; 829 reg = <0x01c28c00 0x400>; 830 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 831 reg-shift = <2>; 832 reg-io-width = <4>; 833 clocks = <&ccu CLK_BUS_UART3>; 834 resets = <&ccu RST_BUS_UART3>; 835 status = "disabled"; 836 }; 837 838 uart4: serial@1c29000 { 839 compatible = "snps,dw-apb-uart"; 840 reg = <0x01c29000 0x400>; 841 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 842 reg-shift = <2>; 843 reg-io-width = <4>; 844 clocks = <&ccu CLK_BUS_UART4>; 845 resets = <&ccu RST_BUS_UART4>; 846 status = "disabled"; 847 }; 848 849 i2c0: i2c@1c2ac00 { 850 compatible = "allwinner,sun6i-a31-i2c"; 851 reg = <0x01c2ac00 0x400>; 852 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&ccu CLK_BUS_I2C0>; 854 resets = <&ccu RST_BUS_I2C0>; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&i2c0_pins>; 857 status = "disabled"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 }; 861 862 i2c1: i2c@1c2b000 { 863 compatible = "allwinner,sun6i-a31-i2c"; 864 reg = <0x01c2b000 0x400>; 865 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&ccu CLK_BUS_I2C1>; 867 resets = <&ccu RST_BUS_I2C1>; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&i2c1_pins>; 870 status = "disabled"; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 }; 874 875 i2c2: i2c@1c2b400 { 876 compatible = "allwinner,sun6i-a31-i2c"; 877 reg = <0x01c2b400 0x400>; 878 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&ccu CLK_BUS_I2C2>; 880 resets = <&ccu RST_BUS_I2C2>; 881 status = "disabled"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 }; 885 886 887 spi0: spi@1c68000 { 888 compatible = "allwinner,sun8i-h3-spi"; 889 reg = <0x01c68000 0x1000>; 890 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 892 clock-names = "ahb", "mod"; 893 dmas = <&dma 23>, <&dma 23>; 894 dma-names = "rx", "tx"; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&spi0_pins>; 897 resets = <&ccu RST_BUS_SPI0>; 898 status = "disabled"; 899 num-cs = <1>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 }; 903 904 spi1: spi@1c69000 { 905 compatible = "allwinner,sun8i-h3-spi"; 906 reg = <0x01c69000 0x1000>; 907 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 909 clock-names = "ahb", "mod"; 910 dmas = <&dma 24>, <&dma 24>; 911 dma-names = "rx", "tx"; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&spi1_pins>; 914 resets = <&ccu RST_BUS_SPI1>; 915 status = "disabled"; 916 num-cs = <1>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 }; 920 921 emac: ethernet@1c30000 { 922 compatible = "allwinner,sun50i-a64-emac"; 923 syscon = <&syscon>; 924 reg = <0x01c30000 0x10000>; 925 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "macirq"; 927 resets = <&ccu RST_BUS_EMAC>; 928 reset-names = "stmmaceth"; 929 clocks = <&ccu CLK_BUS_EMAC>; 930 clock-names = "stmmaceth"; 931 status = "disabled"; 932 933 mdio: mdio { 934 compatible = "snps,dwmac-mdio"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 }; 938 }; 939 940 mali: gpu@1c40000 { 941 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 942 reg = <0x01c40000 0x10000>; 943 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "gp", 951 "gpmmu", 952 "pp0", 953 "ppmmu0", 954 "pp1", 955 "ppmmu1", 956 "pmu"; 957 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 958 clock-names = "bus", "core"; 959 resets = <&ccu RST_BUS_GPU>; 960 }; 961 962 gic: interrupt-controller@1c81000 { 963 compatible = "arm,gic-400"; 964 reg = <0x01c81000 0x1000>, 965 <0x01c82000 0x2000>, 966 <0x01c84000 0x2000>, 967 <0x01c86000 0x2000>; 968 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 969 interrupt-controller; 970 #interrupt-cells = <3>; 971 }; 972 973 pwm: pwm@1c21400 { 974 compatible = "allwinner,sun50i-a64-pwm", 975 "allwinner,sun5i-a13-pwm"; 976 reg = <0x01c21400 0x400>; 977 clocks = <&osc24M>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&pwm_pin>; 980 #pwm-cells = <3>; 981 status = "disabled"; 982 }; 983 984 csi: csi@1cb0000 { 985 compatible = "allwinner,sun50i-a64-csi"; 986 reg = <0x01cb0000 0x1000>; 987 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&ccu CLK_BUS_CSI>, 989 <&ccu CLK_CSI_SCLK>, 990 <&ccu CLK_DRAM_CSI>; 991 clock-names = "bus", "mod", "ram"; 992 resets = <&ccu RST_BUS_CSI>; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&csi_pins>; 995 status = "disabled"; 996 }; 997 998 hdmi: hdmi@1ee0000 { 999 compatible = "allwinner,sun50i-a64-dw-hdmi", 1000 "allwinner,sun8i-a83t-dw-hdmi"; 1001 reg = <0x01ee0000 0x10000>; 1002 reg-io-width = <1>; 1003 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1005 <&ccu CLK_HDMI>; 1006 clock-names = "iahb", "isfr", "tmds"; 1007 resets = <&ccu RST_BUS_HDMI1>; 1008 reset-names = "ctrl"; 1009 phys = <&hdmi_phy>; 1010 phy-names = "hdmi-phy"; 1011 status = "disabled"; 1012 1013 ports { 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 hdmi_in: port@0 { 1018 reg = <0>; 1019 1020 hdmi_in_tcon1: endpoint { 1021 remote-endpoint = <&tcon1_out_hdmi>; 1022 }; 1023 }; 1024 1025 hdmi_out: port@1 { 1026 reg = <1>; 1027 }; 1028 }; 1029 }; 1030 1031 hdmi_phy: hdmi-phy@1ef0000 { 1032 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1033 reg = <0x01ef0000 0x10000>; 1034 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1035 <&ccu 7>; 1036 clock-names = "bus", "mod", "pll-0"; 1037 resets = <&ccu RST_BUS_HDMI0>; 1038 reset-names = "phy"; 1039 #phy-cells = <0>; 1040 }; 1041 1042 rtc: rtc@1f00000 { 1043 compatible = "allwinner,sun50i-a64-rtc", 1044 "allwinner,sun8i-h3-rtc"; 1045 reg = <0x01f00000 0x400>; 1046 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1048 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1049 clocks = <&osc32k>; 1050 #clock-cells = <1>; 1051 }; 1052 1053 r_intc: interrupt-controller@1f00c00 { 1054 compatible = "allwinner,sun50i-a64-r-intc", 1055 "allwinner,sun6i-a31-r-intc"; 1056 interrupt-controller; 1057 #interrupt-cells = <2>; 1058 reg = <0x01f00c00 0x400>; 1059 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1060 }; 1061 1062 r_ccu: clock@1f01400 { 1063 compatible = "allwinner,sun50i-a64-r-ccu"; 1064 reg = <0x01f01400 0x100>; 1065 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1066 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1067 #clock-cells = <1>; 1068 #reset-cells = <1>; 1069 }; 1070 1071 codec_analog: codec-analog@1f015c0 { 1072 compatible = "allwinner,sun50i-a64-codec-analog"; 1073 reg = <0x01f015c0 0x4>; 1074 status = "disabled"; 1075 }; 1076 1077 r_i2c: i2c@1f02400 { 1078 compatible = "allwinner,sun50i-a64-i2c", 1079 "allwinner,sun6i-a31-i2c"; 1080 reg = <0x01f02400 0x400>; 1081 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&r_ccu CLK_APB0_I2C>; 1083 resets = <&r_ccu RST_APB0_I2C>; 1084 status = "disabled"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 }; 1088 1089 r_pwm: pwm@1f03800 { 1090 compatible = "allwinner,sun50i-a64-pwm", 1091 "allwinner,sun5i-a13-pwm"; 1092 reg = <0x01f03800 0x400>; 1093 clocks = <&osc24M>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&r_pwm_pin>; 1096 #pwm-cells = <3>; 1097 status = "disabled"; 1098 }; 1099 1100 r_pio: pinctrl@1f02c00 { 1101 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1102 reg = <0x01f02c00 0x400>; 1103 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1105 clock-names = "apb", "hosc", "losc"; 1106 gpio-controller; 1107 #gpio-cells = <3>; 1108 interrupt-controller; 1109 #interrupt-cells = <3>; 1110 1111 r_i2c_pl89_pins: r-i2c-pl89-pins { 1112 pins = "PL8", "PL9"; 1113 function = "s_i2c"; 1114 }; 1115 1116 r_pwm_pin: r-pwm-pin { 1117 pins = "PL10"; 1118 function = "s_pwm"; 1119 }; 1120 1121 r_rsb_pins: r-rsb-pins { 1122 pins = "PL0", "PL1"; 1123 function = "s_rsb"; 1124 }; 1125 }; 1126 1127 r_rsb: rsb@1f03400 { 1128 compatible = "allwinner,sun8i-a23-rsb"; 1129 reg = <0x01f03400 0x400>; 1130 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&r_ccu 6>; 1132 clock-frequency = <3000000>; 1133 resets = <&r_ccu 2>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&r_rsb_pins>; 1136 status = "disabled"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 }; 1140 1141 wdt0: watchdog@1c20ca0 { 1142 compatible = "allwinner,sun50i-a64-wdt", 1143 "allwinner,sun6i-a31-wdt"; 1144 reg = <0x01c20ca0 0x20>; 1145 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1146 }; 1147 }; 1148}; 1149