1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-r-ccu.h>
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/reset/sun50i-a64-ccu.h>
49
50/ {
51	interrupt-parent = <&gic>;
52	#address-cells = <1>;
53	#size-cells = <1>;
54
55	chosen {
56		#address-cells = <1>;
57		#size-cells = <1>;
58		ranges;
59
60/*
61 * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
62 * However there is no support for this clock on A64 yet, so we depend
63 * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
64 */
65		simplefb_lcd: framebuffer-lcd {
66			compatible = "allwinner,simple-framebuffer",
67				     "simple-framebuffer";
68			allwinner,pipeline = "mixer0-lcd0";
69			clocks = <&ccu CLK_TCON0>,
70				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
71			status = "disabled";
72		};
73	};
74
75	cpus {
76		#address-cells = <1>;
77		#size-cells = <0>;
78
79		cpu0: cpu@0 {
80			compatible = "arm,cortex-a53", "arm,armv8";
81			device_type = "cpu";
82			reg = <0>;
83			enable-method = "psci";
84		};
85
86		cpu1: cpu@1 {
87			compatible = "arm,cortex-a53", "arm,armv8";
88			device_type = "cpu";
89			reg = <1>;
90			enable-method = "psci";
91		};
92
93		cpu2: cpu@2 {
94			compatible = "arm,cortex-a53", "arm,armv8";
95			device_type = "cpu";
96			reg = <2>;
97			enable-method = "psci";
98		};
99
100		cpu3: cpu@3 {
101			compatible = "arm,cortex-a53", "arm,armv8";
102			device_type = "cpu";
103			reg = <3>;
104			enable-method = "psci";
105		};
106	};
107
108	osc24M: osc24M_clk {
109		#clock-cells = <0>;
110		compatible = "fixed-clock";
111		clock-frequency = <24000000>;
112		clock-output-names = "osc24M";
113	};
114
115	osc32k: osc32k_clk {
116		#clock-cells = <0>;
117		compatible = "fixed-clock";
118		clock-frequency = <32768>;
119		clock-output-names = "osc32k";
120	};
121
122	iosc: internal-osc-clk {
123		#clock-cells = <0>;
124		compatible = "fixed-clock";
125		clock-frequency = <16000000>;
126		clock-accuracy = <300000000>;
127		clock-output-names = "iosc";
128	};
129
130	psci {
131		compatible = "arm,psci-0.2";
132		method = "smc";
133	};
134
135	sound_spdif {
136		compatible = "simple-audio-card";
137		simple-audio-card,name = "On-board SPDIF";
138
139		simple-audio-card,cpu {
140			sound-dai = <&spdif>;
141		};
142
143		simple-audio-card,codec {
144			sound-dai = <&spdif_out>;
145		};
146	};
147
148	spdif_out: spdif-out {
149		#sound-dai-cells = <0>;
150		compatible = "linux,spdif-dit";
151	};
152
153	timer {
154		compatible = "arm,armv8-timer";
155		interrupts = <GIC_PPI 13
156			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157			     <GIC_PPI 14
158			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
159			     <GIC_PPI 11
160			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
161			     <GIC_PPI 10
162			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
163	};
164
165	soc {
166		compatible = "simple-bus";
167		#address-cells = <1>;
168		#size-cells = <1>;
169		ranges;
170
171		syscon: syscon@1c00000 {
172			compatible = "allwinner,sun50i-a64-system-controller",
173				"syscon";
174			reg = <0x01c00000 0x1000>;
175		};
176
177		dma: dma-controller@1c02000 {
178			compatible = "allwinner,sun50i-a64-dma";
179			reg = <0x01c02000 0x1000>;
180			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
181			clocks = <&ccu CLK_BUS_DMA>;
182			dma-channels = <8>;
183			dma-requests = <27>;
184			resets = <&ccu RST_BUS_DMA>;
185			#dma-cells = <1>;
186		};
187
188		mmc0: mmc@1c0f000 {
189			compatible = "allwinner,sun50i-a64-mmc";
190			reg = <0x01c0f000 0x1000>;
191			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
192			clock-names = "ahb", "mmc";
193			resets = <&ccu RST_BUS_MMC0>;
194			reset-names = "ahb";
195			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
196			max-frequency = <150000000>;
197			status = "disabled";
198			#address-cells = <1>;
199			#size-cells = <0>;
200		};
201
202		mmc1: mmc@1c10000 {
203			compatible = "allwinner,sun50i-a64-mmc";
204			reg = <0x01c10000 0x1000>;
205			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
206			clock-names = "ahb", "mmc";
207			resets = <&ccu RST_BUS_MMC1>;
208			reset-names = "ahb";
209			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
210			max-frequency = <150000000>;
211			status = "disabled";
212			#address-cells = <1>;
213			#size-cells = <0>;
214		};
215
216		mmc2: mmc@1c11000 {
217			compatible = "allwinner,sun50i-a64-emmc";
218			reg = <0x01c11000 0x1000>;
219			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
220			clock-names = "ahb", "mmc";
221			resets = <&ccu RST_BUS_MMC2>;
222			reset-names = "ahb";
223			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
224			max-frequency = <200000000>;
225			status = "disabled";
226			#address-cells = <1>;
227			#size-cells = <0>;
228		};
229
230		usb_otg: usb@1c19000 {
231			compatible = "allwinner,sun8i-a33-musb";
232			reg = <0x01c19000 0x0400>;
233			clocks = <&ccu CLK_BUS_OTG>;
234			resets = <&ccu RST_BUS_OTG>;
235			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
236			interrupt-names = "mc";
237			phys = <&usbphy 0>;
238			phy-names = "usb";
239			extcon = <&usbphy 0>;
240			status = "disabled";
241		};
242
243		usbphy: phy@1c19400 {
244			compatible = "allwinner,sun50i-a64-usb-phy";
245			reg = <0x01c19400 0x14>,
246			      <0x01c1a800 0x4>,
247			      <0x01c1b800 0x4>;
248			reg-names = "phy_ctrl",
249				    "pmu0",
250				    "pmu1";
251			clocks = <&ccu CLK_USB_PHY0>,
252				 <&ccu CLK_USB_PHY1>;
253			clock-names = "usb0_phy",
254				      "usb1_phy";
255			resets = <&ccu RST_USB_PHY0>,
256				 <&ccu RST_USB_PHY1>;
257			reset-names = "usb0_reset",
258				      "usb1_reset";
259			status = "disabled";
260			#phy-cells = <1>;
261		};
262
263		ehci0: usb@1c1a000 {
264			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
265			reg = <0x01c1a000 0x100>;
266			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
267			clocks = <&ccu CLK_BUS_OHCI0>,
268				 <&ccu CLK_BUS_EHCI0>,
269				 <&ccu CLK_USB_OHCI0>;
270			resets = <&ccu RST_BUS_OHCI0>,
271				 <&ccu RST_BUS_EHCI0>;
272			status = "disabled";
273		};
274
275		ohci0: usb@1c1a400 {
276			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
277			reg = <0x01c1a400 0x100>;
278			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
279			clocks = <&ccu CLK_BUS_OHCI0>,
280				 <&ccu CLK_USB_OHCI0>;
281			resets = <&ccu RST_BUS_OHCI0>;
282			status = "disabled";
283		};
284
285		ehci1: usb@1c1b000 {
286			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
287			reg = <0x01c1b000 0x100>;
288			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
289			clocks = <&ccu CLK_BUS_OHCI1>,
290				 <&ccu CLK_BUS_EHCI1>,
291				 <&ccu CLK_USB_OHCI1>;
292			resets = <&ccu RST_BUS_OHCI1>,
293				 <&ccu RST_BUS_EHCI1>;
294			phys = <&usbphy 1>;
295			phy-names = "usb";
296			status = "disabled";
297		};
298
299		ohci1: usb@1c1b400 {
300			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
301			reg = <0x01c1b400 0x100>;
302			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
303			clocks = <&ccu CLK_BUS_OHCI1>,
304				 <&ccu CLK_USB_OHCI1>;
305			resets = <&ccu RST_BUS_OHCI1>;
306			phys = <&usbphy 1>;
307			phy-names = "usb";
308			status = "disabled";
309		};
310
311		ccu: clock@1c20000 {
312			compatible = "allwinner,sun50i-a64-ccu";
313			reg = <0x01c20000 0x400>;
314			clocks = <&osc24M>, <&osc32k>;
315			clock-names = "hosc", "losc";
316			#clock-cells = <1>;
317			#reset-cells = <1>;
318		};
319
320		pio: pinctrl@1c20800 {
321			compatible = "allwinner,sun50i-a64-pinctrl";
322			reg = <0x01c20800 0x400>;
323			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
325				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
326			clocks = <&ccu 58>;
327			gpio-controller;
328			#gpio-cells = <3>;
329			interrupt-controller;
330			#interrupt-cells = <3>;
331
332			i2c0_pins: i2c0_pins {
333				pins = "PH0", "PH1";
334				function = "i2c0";
335			};
336
337			i2c1_pins: i2c1_pins {
338				pins = "PH2", "PH3";
339				function = "i2c1";
340			};
341
342			mmc0_pins: mmc0-pins {
343				pins = "PF0", "PF1", "PF2", "PF3",
344				       "PF4", "PF5";
345				function = "mmc0";
346				drive-strength = <30>;
347				bias-pull-up;
348			};
349
350			mmc1_pins: mmc1-pins {
351				pins = "PG0", "PG1", "PG2", "PG3",
352				       "PG4", "PG5";
353				function = "mmc1";
354				drive-strength = <30>;
355				bias-pull-up;
356			};
357
358			mmc2_pins: mmc2-pins {
359				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
360				       "PC10","PC11", "PC12", "PC13",
361				       "PC14", "PC15", "PC16";
362				function = "mmc2";
363				drive-strength = <30>;
364				bias-pull-up;
365			};
366
367			rmii_pins: rmii_pins {
368				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
369				       "PD18", "PD19", "PD20", "PD22", "PD23";
370				function = "emac";
371				drive-strength = <40>;
372			};
373
374			rgmii_pins: rgmii_pins {
375				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
376				       "PD13", "PD15", "PD16", "PD17", "PD18",
377				       "PD19", "PD20", "PD21", "PD22", "PD23";
378				function = "emac";
379				drive-strength = <40>;
380			};
381
382			spdif_tx_pin: spdif {
383				pins = "PH8";
384				function = "spdif";
385			};
386
387			spi0_pins: spi0 {
388				pins = "PC0", "PC1", "PC2", "PC3";
389				function = "spi0";
390			};
391
392			spi1_pins: spi1 {
393				pins = "PD0", "PD1", "PD2", "PD3";
394				function = "spi1";
395			};
396
397			uart0_pins_a: uart0 {
398				pins = "PB8", "PB9";
399				function = "uart0";
400			};
401
402			uart1_pins: uart1_pins {
403				pins = "PG6", "PG7";
404				function = "uart1";
405			};
406
407			uart1_rts_cts_pins: uart1_rts_cts_pins {
408				pins = "PG8", "PG9";
409				function = "uart1";
410			};
411
412			uart2_pins: uart2-pins {
413				pins = "PB0", "PB1";
414				function = "uart2";
415			};
416
417			uart3_pins: uart3-pins {
418				pins = "PD0", "PD1";
419				function = "uart3";
420			};
421
422			uart4_pins: uart4-pins {
423				pins = "PD2", "PD3";
424				function = "uart4";
425			};
426
427			uart4_rts_cts_pins: uart4-rts-cts-pins {
428				pins = "PD4", "PD5";
429				function = "uart4";
430			};
431		};
432
433		spdif: spdif@1c21000 {
434			#sound-dai-cells = <0>;
435			compatible = "allwinner,sun50i-a64-spdif",
436				     "allwinner,sun8i-h3-spdif";
437			reg = <0x01c21000 0x400>;
438			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
439			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
440			resets = <&ccu RST_BUS_SPDIF>;
441			clock-names = "apb", "spdif";
442			dmas = <&dma 2>;
443			dma-names = "tx";
444			pinctrl-names = "default";
445			pinctrl-0 = <&spdif_tx_pin>;
446			status = "disabled";
447		};
448
449		i2s0: i2s@1c22000 {
450			#sound-dai-cells = <0>;
451			compatible = "allwinner,sun50i-a64-i2s",
452				     "allwinner,sun8i-h3-i2s";
453			reg = <0x01c22000 0x400>;
454			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
455			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
456			clock-names = "apb", "mod";
457			resets = <&ccu RST_BUS_I2S0>;
458			dma-names = "rx", "tx";
459			dmas = <&dma 3>, <&dma 3>;
460			status = "disabled";
461		};
462
463		i2s1: i2s@1c22400 {
464			#sound-dai-cells = <0>;
465			compatible = "allwinner,sun50i-a64-i2s",
466				     "allwinner,sun8i-h3-i2s";
467			reg = <0x01c22400 0x400>;
468			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
469			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
470			clock-names = "apb", "mod";
471			resets = <&ccu RST_BUS_I2S1>;
472			dma-names = "rx", "tx";
473			dmas = <&dma 4>, <&dma 4>;
474			status = "disabled";
475		};
476
477		uart0: serial@1c28000 {
478			compatible = "snps,dw-apb-uart";
479			reg = <0x01c28000 0x400>;
480			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
481			reg-shift = <2>;
482			reg-io-width = <4>;
483			clocks = <&ccu CLK_BUS_UART0>;
484			resets = <&ccu RST_BUS_UART0>;
485			status = "disabled";
486		};
487
488		uart1: serial@1c28400 {
489			compatible = "snps,dw-apb-uart";
490			reg = <0x01c28400 0x400>;
491			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
492			reg-shift = <2>;
493			reg-io-width = <4>;
494			clocks = <&ccu CLK_BUS_UART1>;
495			resets = <&ccu RST_BUS_UART1>;
496			status = "disabled";
497		};
498
499		uart2: serial@1c28800 {
500			compatible = "snps,dw-apb-uart";
501			reg = <0x01c28800 0x400>;
502			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
503			reg-shift = <2>;
504			reg-io-width = <4>;
505			clocks = <&ccu CLK_BUS_UART2>;
506			resets = <&ccu RST_BUS_UART2>;
507			status = "disabled";
508		};
509
510		uart3: serial@1c28c00 {
511			compatible = "snps,dw-apb-uart";
512			reg = <0x01c28c00 0x400>;
513			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
514			reg-shift = <2>;
515			reg-io-width = <4>;
516			clocks = <&ccu CLK_BUS_UART3>;
517			resets = <&ccu RST_BUS_UART3>;
518			status = "disabled";
519		};
520
521		uart4: serial@1c29000 {
522			compatible = "snps,dw-apb-uart";
523			reg = <0x01c29000 0x400>;
524			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
525			reg-shift = <2>;
526			reg-io-width = <4>;
527			clocks = <&ccu CLK_BUS_UART4>;
528			resets = <&ccu RST_BUS_UART4>;
529			status = "disabled";
530		};
531
532		i2c0: i2c@1c2ac00 {
533			compatible = "allwinner,sun6i-a31-i2c";
534			reg = <0x01c2ac00 0x400>;
535			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
536			clocks = <&ccu CLK_BUS_I2C0>;
537			resets = <&ccu RST_BUS_I2C0>;
538			status = "disabled";
539			#address-cells = <1>;
540			#size-cells = <0>;
541		};
542
543		i2c1: i2c@1c2b000 {
544			compatible = "allwinner,sun6i-a31-i2c";
545			reg = <0x01c2b000 0x400>;
546			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
547			clocks = <&ccu CLK_BUS_I2C1>;
548			resets = <&ccu RST_BUS_I2C1>;
549			status = "disabled";
550			#address-cells = <1>;
551			#size-cells = <0>;
552		};
553
554		i2c2: i2c@1c2b400 {
555			compatible = "allwinner,sun6i-a31-i2c";
556			reg = <0x01c2b400 0x400>;
557			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
558			clocks = <&ccu CLK_BUS_I2C2>;
559			resets = <&ccu RST_BUS_I2C2>;
560			status = "disabled";
561			#address-cells = <1>;
562			#size-cells = <0>;
563		};
564
565
566		spi0: spi@1c68000 {
567			compatible = "allwinner,sun8i-h3-spi";
568			reg = <0x01c68000 0x1000>;
569			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
570			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
571			clock-names = "ahb", "mod";
572			dmas = <&dma 23>, <&dma 23>;
573			dma-names = "rx", "tx";
574			pinctrl-names = "default";
575			pinctrl-0 = <&spi0_pins>;
576			resets = <&ccu RST_BUS_SPI0>;
577			status = "disabled";
578			num-cs = <1>;
579			#address-cells = <1>;
580			#size-cells = <0>;
581		};
582
583		spi1: spi@1c69000 {
584			compatible = "allwinner,sun8i-h3-spi";
585			reg = <0x01c69000 0x1000>;
586			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
587			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
588			clock-names = "ahb", "mod";
589			dmas = <&dma 24>, <&dma 24>;
590			dma-names = "rx", "tx";
591			pinctrl-names = "default";
592			pinctrl-0 = <&spi1_pins>;
593			resets = <&ccu RST_BUS_SPI1>;
594			status = "disabled";
595			num-cs = <1>;
596			#address-cells = <1>;
597			#size-cells = <0>;
598		};
599
600		emac: ethernet@1c30000 {
601			compatible = "allwinner,sun50i-a64-emac";
602			syscon = <&syscon>;
603			reg = <0x01c30000 0x10000>;
604			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
605			interrupt-names = "macirq";
606			resets = <&ccu RST_BUS_EMAC>;
607			reset-names = "stmmaceth";
608			clocks = <&ccu CLK_BUS_EMAC>;
609			clock-names = "stmmaceth";
610			status = "disabled";
611			#address-cells = <1>;
612			#size-cells = <0>;
613
614			mdio: mdio {
615				compatible = "snps,dwmac-mdio";
616				#address-cells = <1>;
617				#size-cells = <0>;
618			};
619		};
620
621		gic: interrupt-controller@1c81000 {
622			compatible = "arm,gic-400";
623			reg = <0x01c81000 0x1000>,
624			      <0x01c82000 0x2000>,
625			      <0x01c84000 0x2000>,
626			      <0x01c86000 0x2000>;
627			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
628			interrupt-controller;
629			#interrupt-cells = <3>;
630		};
631
632		rtc: rtc@1f00000 {
633			compatible = "allwinner,sun6i-a31-rtc";
634			reg = <0x01f00000 0x54>;
635			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
636				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
637		};
638
639		r_intc: interrupt-controller@1f00c00 {
640			compatible = "allwinner,sun50i-a64-r-intc",
641				     "allwinner,sun6i-a31-r-intc";
642			interrupt-controller;
643			#interrupt-cells = <2>;
644			reg = <0x01f00c00 0x400>;
645			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
646		};
647
648		r_ccu: clock@1f01400 {
649			compatible = "allwinner,sun50i-a64-r-ccu";
650			reg = <0x01f01400 0x100>;
651			clocks = <&osc24M>, <&osc32k>, <&iosc>,
652				 <&ccu 11>;
653			clock-names = "hosc", "losc", "iosc", "pll-periph";
654			#clock-cells = <1>;
655			#reset-cells = <1>;
656		};
657
658		r_pio: pinctrl@1f02c00 {
659			compatible = "allwinner,sun50i-a64-r-pinctrl";
660			reg = <0x01f02c00 0x400>;
661			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
662			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
663			clock-names = "apb", "hosc", "losc";
664			gpio-controller;
665			#gpio-cells = <3>;
666			interrupt-controller;
667			#interrupt-cells = <3>;
668
669			r_rsb_pins: rsb {
670				pins = "PL0", "PL1";
671				function = "s_rsb";
672			};
673		};
674
675		r_rsb: rsb@1f03400 {
676			compatible = "allwinner,sun8i-a23-rsb";
677			reg = <0x01f03400 0x400>;
678			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
679			clocks = <&r_ccu 6>;
680			clock-frequency = <3000000>;
681			resets = <&r_ccu 2>;
682			pinctrl-names = "default";
683			pinctrl-0 = <&r_rsb_pins>;
684			status = "disabled";
685			#address-cells = <1>;
686			#size-cells = <0>;
687		};
688
689		wdt0: watchdog@1c20ca0 {
690			compatible = "allwinner,sun50i-a64-wdt",
691				     "allwinner,sun6i-a31-wdt";
692			reg = <0x01c20ca0 0x20>;
693			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
694		};
695	};
696};
697