1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun50i-a64-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <3>; 83 enable-method = "psci"; 84 }; 85 }; 86 87 osc24M: osc24M_clk { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-output-names = "osc32k"; 99 }; 100 101 iosc: internal-osc-clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 clock-frequency = <16000000>; 105 clock-accuracy = <300000000>; 106 clock-output-names = "iosc"; 107 }; 108 109 psci { 110 compatible = "arm,psci-0.2"; 111 method = "smc"; 112 }; 113 114 timer { 115 compatible = "arm,armv8-timer"; 116 interrupts = <GIC_PPI 13 117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 118 <GIC_PPI 14 119 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 120 <GIC_PPI 11 121 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 122 <GIC_PPI 10 123 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 syscon: syscon@1c00000 { 133 compatible = "allwinner,sun50i-a64-system-controller", 134 "syscon"; 135 reg = <0x01c00000 0x1000>; 136 }; 137 138 mmc0: mmc@1c0f000 { 139 compatible = "allwinner,sun50i-a64-mmc"; 140 reg = <0x01c0f000 0x1000>; 141 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 142 clock-names = "ahb", "mmc"; 143 resets = <&ccu RST_BUS_MMC0>; 144 reset-names = "ahb"; 145 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 146 max-frequency = <150000000>; 147 status = "disabled"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 }; 151 152 mmc1: mmc@1c10000 { 153 compatible = "allwinner,sun50i-a64-mmc"; 154 reg = <0x01c10000 0x1000>; 155 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 156 clock-names = "ahb", "mmc"; 157 resets = <&ccu RST_BUS_MMC1>; 158 reset-names = "ahb"; 159 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 160 max-frequency = <150000000>; 161 status = "disabled"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 mmc2: mmc@1c11000 { 167 compatible = "allwinner,sun50i-a64-emmc"; 168 reg = <0x01c11000 0x1000>; 169 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 170 clock-names = "ahb", "mmc"; 171 resets = <&ccu RST_BUS_MMC2>; 172 reset-names = "ahb"; 173 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 174 max-frequency = <200000000>; 175 status = "disabled"; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 }; 179 180 usb_otg: usb@01c19000 { 181 compatible = "allwinner,sun8i-a33-musb"; 182 reg = <0x01c19000 0x0400>; 183 clocks = <&ccu CLK_BUS_OTG>; 184 resets = <&ccu RST_BUS_OTG>; 185 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "mc"; 187 phys = <&usbphy 0>; 188 phy-names = "usb"; 189 extcon = <&usbphy 0>; 190 status = "disabled"; 191 }; 192 193 usbphy: phy@01c19400 { 194 compatible = "allwinner,sun50i-a64-usb-phy"; 195 reg = <0x01c19400 0x14>, 196 <0x01c1a800 0x4>, 197 <0x01c1b800 0x4>; 198 reg-names = "phy_ctrl", 199 "pmu0", 200 "pmu1"; 201 clocks = <&ccu CLK_USB_PHY0>, 202 <&ccu CLK_USB_PHY1>; 203 clock-names = "usb0_phy", 204 "usb1_phy"; 205 resets = <&ccu RST_USB_PHY0>, 206 <&ccu RST_USB_PHY1>; 207 reset-names = "usb0_reset", 208 "usb1_reset"; 209 status = "disabled"; 210 #phy-cells = <1>; 211 }; 212 213 ehci1: usb@01c1b000 { 214 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 215 reg = <0x01c1b000 0x100>; 216 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&ccu CLK_BUS_OHCI1>, 218 <&ccu CLK_BUS_EHCI1>, 219 <&ccu CLK_USB_OHCI1>; 220 resets = <&ccu RST_BUS_OHCI1>, 221 <&ccu RST_BUS_EHCI1>; 222 phys = <&usbphy 1>; 223 phy-names = "usb"; 224 status = "disabled"; 225 }; 226 227 ohci1: usb@01c1b400 { 228 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 229 reg = <0x01c1b400 0x100>; 230 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&ccu CLK_BUS_OHCI1>, 232 <&ccu CLK_USB_OHCI1>; 233 resets = <&ccu RST_BUS_OHCI1>; 234 phys = <&usbphy 1>; 235 phy-names = "usb"; 236 status = "disabled"; 237 }; 238 239 ccu: clock@01c20000 { 240 compatible = "allwinner,sun50i-a64-ccu"; 241 reg = <0x01c20000 0x400>; 242 clocks = <&osc24M>, <&osc32k>; 243 clock-names = "hosc", "losc"; 244 #clock-cells = <1>; 245 #reset-cells = <1>; 246 }; 247 248 pio: pinctrl@1c20800 { 249 compatible = "allwinner,sun50i-a64-pinctrl"; 250 reg = <0x01c20800 0x400>; 251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&ccu 58>; 255 gpio-controller; 256 #gpio-cells = <3>; 257 interrupt-controller; 258 #interrupt-cells = <3>; 259 260 i2c1_pins: i2c1_pins { 261 pins = "PH2", "PH3"; 262 function = "i2c1"; 263 }; 264 265 mmc0_pins: mmc0-pins { 266 pins = "PF0", "PF1", "PF2", "PF3", 267 "PF4", "PF5"; 268 function = "mmc0"; 269 drive-strength = <30>; 270 bias-pull-up; 271 }; 272 273 mmc1_pins: mmc1-pins { 274 pins = "PG0", "PG1", "PG2", "PG3", 275 "PG4", "PG5"; 276 function = "mmc1"; 277 drive-strength = <30>; 278 bias-pull-up; 279 }; 280 281 mmc2_pins: mmc2-pins { 282 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 283 "PC10","PC11", "PC12", "PC13", 284 "PC14", "PC15", "PC16"; 285 function = "mmc2"; 286 drive-strength = <30>; 287 bias-pull-up; 288 }; 289 290 uart0_pins_a: uart0@0 { 291 pins = "PB8", "PB9"; 292 function = "uart0"; 293 }; 294 295 uart1_pins: uart1_pins { 296 pins = "PG6", "PG7"; 297 function = "uart1"; 298 }; 299 300 uart1_rts_cts_pins: uart1_rts_cts_pins { 301 pins = "PG8", "PG9"; 302 function = "uart1"; 303 }; 304 }; 305 306 uart0: serial@1c28000 { 307 compatible = "snps,dw-apb-uart"; 308 reg = <0x01c28000 0x400>; 309 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 310 reg-shift = <2>; 311 reg-io-width = <4>; 312 clocks = <&ccu 67>; 313 resets = <&ccu 46>; 314 status = "disabled"; 315 }; 316 317 uart1: serial@1c28400 { 318 compatible = "snps,dw-apb-uart"; 319 reg = <0x01c28400 0x400>; 320 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 321 reg-shift = <2>; 322 reg-io-width = <4>; 323 clocks = <&ccu 68>; 324 resets = <&ccu 47>; 325 status = "disabled"; 326 }; 327 328 uart2: serial@1c28800 { 329 compatible = "snps,dw-apb-uart"; 330 reg = <0x01c28800 0x400>; 331 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 332 reg-shift = <2>; 333 reg-io-width = <4>; 334 clocks = <&ccu 69>; 335 resets = <&ccu 48>; 336 status = "disabled"; 337 }; 338 339 uart3: serial@1c28c00 { 340 compatible = "snps,dw-apb-uart"; 341 reg = <0x01c28c00 0x400>; 342 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 343 reg-shift = <2>; 344 reg-io-width = <4>; 345 clocks = <&ccu 70>; 346 resets = <&ccu 49>; 347 status = "disabled"; 348 }; 349 350 uart4: serial@1c29000 { 351 compatible = "snps,dw-apb-uart"; 352 reg = <0x01c29000 0x400>; 353 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 clocks = <&ccu 71>; 357 resets = <&ccu 50>; 358 status = "disabled"; 359 }; 360 361 i2c0: i2c@1c2ac00 { 362 compatible = "allwinner,sun6i-a31-i2c"; 363 reg = <0x01c2ac00 0x400>; 364 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&ccu 63>; 366 resets = <&ccu 42>; 367 status = "disabled"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 372 i2c1: i2c@1c2b000 { 373 compatible = "allwinner,sun6i-a31-i2c"; 374 reg = <0x01c2b000 0x400>; 375 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&ccu 64>; 377 resets = <&ccu 43>; 378 status = "disabled"; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 }; 382 383 i2c2: i2c@1c2b400 { 384 compatible = "allwinner,sun6i-a31-i2c"; 385 reg = <0x01c2b400 0x400>; 386 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&ccu 65>; 388 resets = <&ccu 44>; 389 status = "disabled"; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 }; 393 394 gic: interrupt-controller@1c81000 { 395 compatible = "arm,gic-400"; 396 reg = <0x01c81000 0x1000>, 397 <0x01c82000 0x2000>, 398 <0x01c84000 0x2000>, 399 <0x01c86000 0x2000>; 400 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 401 interrupt-controller; 402 #interrupt-cells = <3>; 403 }; 404 405 rtc: rtc@1f00000 { 406 compatible = "allwinner,sun6i-a31-rtc"; 407 reg = <0x01f00000 0x54>; 408 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 r_ccu: clock@1f01400 { 413 compatible = "allwinner,sun50i-a64-r-ccu"; 414 reg = <0x01f01400 0x100>; 415 clocks = <&osc24M>, <&osc32k>, <&iosc>; 416 clock-names = "hosc", "losc", "iosc"; 417 #clock-cells = <1>; 418 #reset-cells = <1>; 419 }; 420 421 r_pio: pinctrl@01f02c00 { 422 compatible = "allwinner,sun50i-a64-r-pinctrl"; 423 reg = <0x01f02c00 0x400>; 424 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; 426 clock-names = "apb", "hosc", "losc"; 427 gpio-controller; 428 #gpio-cells = <3>; 429 interrupt-controller; 430 #interrupt-cells = <3>; 431 }; 432 }; 433}; 434