1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-r-ccu.h>
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/reset/sun50i-a64-ccu.h>
49#include <dt-bindings/reset/sun8i-r-ccu.h>
50
51/ {
52	interrupt-parent = <&gic>;
53	#address-cells = <1>;
54	#size-cells = <1>;
55
56	chosen {
57		#address-cells = <1>;
58		#size-cells = <1>;
59		ranges;
60
61/*
62 * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
63 * However there is no support for this clock on A64 yet, so we depend
64 * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
65 */
66		simplefb_lcd: framebuffer-lcd {
67			compatible = "allwinner,simple-framebuffer",
68				     "simple-framebuffer";
69			allwinner,pipeline = "mixer0-lcd0";
70			clocks = <&ccu CLK_TCON0>,
71				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
72			status = "disabled";
73		};
74	};
75
76	cpus {
77		#address-cells = <1>;
78		#size-cells = <0>;
79
80		cpu0: cpu@0 {
81			compatible = "arm,cortex-a53", "arm,armv8";
82			device_type = "cpu";
83			reg = <0>;
84			enable-method = "psci";
85		};
86
87		cpu1: cpu@1 {
88			compatible = "arm,cortex-a53", "arm,armv8";
89			device_type = "cpu";
90			reg = <1>;
91			enable-method = "psci";
92		};
93
94		cpu2: cpu@2 {
95			compatible = "arm,cortex-a53", "arm,armv8";
96			device_type = "cpu";
97			reg = <2>;
98			enable-method = "psci";
99		};
100
101		cpu3: cpu@3 {
102			compatible = "arm,cortex-a53", "arm,armv8";
103			device_type = "cpu";
104			reg = <3>;
105			enable-method = "psci";
106		};
107	};
108
109	osc24M: osc24M_clk {
110		#clock-cells = <0>;
111		compatible = "fixed-clock";
112		clock-frequency = <24000000>;
113		clock-output-names = "osc24M";
114	};
115
116	osc32k: osc32k_clk {
117		#clock-cells = <0>;
118		compatible = "fixed-clock";
119		clock-frequency = <32768>;
120		clock-output-names = "osc32k";
121	};
122
123	iosc: internal-osc-clk {
124		#clock-cells = <0>;
125		compatible = "fixed-clock";
126		clock-frequency = <16000000>;
127		clock-accuracy = <300000000>;
128		clock-output-names = "iosc";
129	};
130
131	psci {
132		compatible = "arm,psci-0.2";
133		method = "smc";
134	};
135
136	sound_spdif {
137		compatible = "simple-audio-card";
138		simple-audio-card,name = "On-board SPDIF";
139
140		simple-audio-card,cpu {
141			sound-dai = <&spdif>;
142		};
143
144		simple-audio-card,codec {
145			sound-dai = <&spdif_out>;
146		};
147	};
148
149	spdif_out: spdif-out {
150		#sound-dai-cells = <0>;
151		compatible = "linux,spdif-dit";
152	};
153
154	timer {
155		compatible = "arm,armv8-timer";
156		interrupts = <GIC_PPI 13
157			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
158			     <GIC_PPI 14
159			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
160			     <GIC_PPI 11
161			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
162			     <GIC_PPI 10
163			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
164	};
165
166	soc {
167		compatible = "simple-bus";
168		#address-cells = <1>;
169		#size-cells = <1>;
170		ranges;
171
172		syscon: syscon@1c00000 {
173			compatible = "allwinner,sun50i-a64-system-controller",
174				"syscon";
175			reg = <0x01c00000 0x1000>;
176		};
177
178		dma: dma-controller@1c02000 {
179			compatible = "allwinner,sun50i-a64-dma";
180			reg = <0x01c02000 0x1000>;
181			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
182			clocks = <&ccu CLK_BUS_DMA>;
183			dma-channels = <8>;
184			dma-requests = <27>;
185			resets = <&ccu RST_BUS_DMA>;
186			#dma-cells = <1>;
187		};
188
189		mmc0: mmc@1c0f000 {
190			compatible = "allwinner,sun50i-a64-mmc";
191			reg = <0x01c0f000 0x1000>;
192			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
193			clock-names = "ahb", "mmc";
194			resets = <&ccu RST_BUS_MMC0>;
195			reset-names = "ahb";
196			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
197			max-frequency = <150000000>;
198			status = "disabled";
199			#address-cells = <1>;
200			#size-cells = <0>;
201		};
202
203		mmc1: mmc@1c10000 {
204			compatible = "allwinner,sun50i-a64-mmc";
205			reg = <0x01c10000 0x1000>;
206			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
207			clock-names = "ahb", "mmc";
208			resets = <&ccu RST_BUS_MMC1>;
209			reset-names = "ahb";
210			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
211			max-frequency = <150000000>;
212			status = "disabled";
213			#address-cells = <1>;
214			#size-cells = <0>;
215		};
216
217		mmc2: mmc@1c11000 {
218			compatible = "allwinner,sun50i-a64-emmc";
219			reg = <0x01c11000 0x1000>;
220			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
221			clock-names = "ahb", "mmc";
222			resets = <&ccu RST_BUS_MMC2>;
223			reset-names = "ahb";
224			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
225			max-frequency = <200000000>;
226			status = "disabled";
227			#address-cells = <1>;
228			#size-cells = <0>;
229		};
230
231		usb_otg: usb@1c19000 {
232			compatible = "allwinner,sun8i-a33-musb";
233			reg = <0x01c19000 0x0400>;
234			clocks = <&ccu CLK_BUS_OTG>;
235			resets = <&ccu RST_BUS_OTG>;
236			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
237			interrupt-names = "mc";
238			phys = <&usbphy 0>;
239			phy-names = "usb";
240			extcon = <&usbphy 0>;
241			status = "disabled";
242		};
243
244		usbphy: phy@1c19400 {
245			compatible = "allwinner,sun50i-a64-usb-phy";
246			reg = <0x01c19400 0x14>,
247			      <0x01c1a800 0x4>,
248			      <0x01c1b800 0x4>;
249			reg-names = "phy_ctrl",
250				    "pmu0",
251				    "pmu1";
252			clocks = <&ccu CLK_USB_PHY0>,
253				 <&ccu CLK_USB_PHY1>;
254			clock-names = "usb0_phy",
255				      "usb1_phy";
256			resets = <&ccu RST_USB_PHY0>,
257				 <&ccu RST_USB_PHY1>;
258			reset-names = "usb0_reset",
259				      "usb1_reset";
260			status = "disabled";
261			#phy-cells = <1>;
262		};
263
264		ehci0: usb@1c1a000 {
265			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
266			reg = <0x01c1a000 0x100>;
267			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
268			clocks = <&ccu CLK_BUS_OHCI0>,
269				 <&ccu CLK_BUS_EHCI0>,
270				 <&ccu CLK_USB_OHCI0>;
271			resets = <&ccu RST_BUS_OHCI0>,
272				 <&ccu RST_BUS_EHCI0>;
273			status = "disabled";
274		};
275
276		ohci0: usb@1c1a400 {
277			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
278			reg = <0x01c1a400 0x100>;
279			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
280			clocks = <&ccu CLK_BUS_OHCI0>,
281				 <&ccu CLK_USB_OHCI0>;
282			resets = <&ccu RST_BUS_OHCI0>;
283			status = "disabled";
284		};
285
286		ehci1: usb@1c1b000 {
287			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
288			reg = <0x01c1b000 0x100>;
289			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
290			clocks = <&ccu CLK_BUS_OHCI1>,
291				 <&ccu CLK_BUS_EHCI1>,
292				 <&ccu CLK_USB_OHCI1>;
293			resets = <&ccu RST_BUS_OHCI1>,
294				 <&ccu RST_BUS_EHCI1>;
295			phys = <&usbphy 1>;
296			phy-names = "usb";
297			status = "disabled";
298		};
299
300		ohci1: usb@1c1b400 {
301			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
302			reg = <0x01c1b400 0x100>;
303			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
304			clocks = <&ccu CLK_BUS_OHCI1>,
305				 <&ccu CLK_USB_OHCI1>;
306			resets = <&ccu RST_BUS_OHCI1>;
307			phys = <&usbphy 1>;
308			phy-names = "usb";
309			status = "disabled";
310		};
311
312		ccu: clock@1c20000 {
313			compatible = "allwinner,sun50i-a64-ccu";
314			reg = <0x01c20000 0x400>;
315			clocks = <&osc24M>, <&osc32k>;
316			clock-names = "hosc", "losc";
317			#clock-cells = <1>;
318			#reset-cells = <1>;
319		};
320
321		pio: pinctrl@1c20800 {
322			compatible = "allwinner,sun50i-a64-pinctrl";
323			reg = <0x01c20800 0x400>;
324			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
325				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
326				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
327			clocks = <&ccu 58>;
328			gpio-controller;
329			#gpio-cells = <3>;
330			interrupt-controller;
331			#interrupt-cells = <3>;
332
333			i2c0_pins: i2c0_pins {
334				pins = "PH0", "PH1";
335				function = "i2c0";
336			};
337
338			i2c1_pins: i2c1_pins {
339				pins = "PH2", "PH3";
340				function = "i2c1";
341			};
342
343			mmc0_pins: mmc0-pins {
344				pins = "PF0", "PF1", "PF2", "PF3",
345				       "PF4", "PF5";
346				function = "mmc0";
347				drive-strength = <30>;
348				bias-pull-up;
349			};
350
351			mmc1_pins: mmc1-pins {
352				pins = "PG0", "PG1", "PG2", "PG3",
353				       "PG4", "PG5";
354				function = "mmc1";
355				drive-strength = <30>;
356				bias-pull-up;
357			};
358
359			mmc2_pins: mmc2-pins {
360				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
361				       "PC10","PC11", "PC12", "PC13",
362				       "PC14", "PC15", "PC16";
363				function = "mmc2";
364				drive-strength = <30>;
365				bias-pull-up;
366			};
367
368			pwm_pin: pwm_pin {
369				pins = "PD22";
370				function = "pwm";
371			};
372
373			rmii_pins: rmii_pins {
374				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
375				       "PD18", "PD19", "PD20", "PD22", "PD23";
376				function = "emac";
377				drive-strength = <40>;
378			};
379
380			rgmii_pins: rgmii_pins {
381				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
382				       "PD13", "PD15", "PD16", "PD17", "PD18",
383				       "PD19", "PD20", "PD21", "PD22", "PD23";
384				function = "emac";
385				drive-strength = <40>;
386			};
387
388			spdif_tx_pin: spdif {
389				pins = "PH8";
390				function = "spdif";
391			};
392
393			spi0_pins: spi0 {
394				pins = "PC0", "PC1", "PC2", "PC3";
395				function = "spi0";
396			};
397
398			spi1_pins: spi1 {
399				pins = "PD0", "PD1", "PD2", "PD3";
400				function = "spi1";
401			};
402
403			uart0_pins_a: uart0 {
404				pins = "PB8", "PB9";
405				function = "uart0";
406			};
407
408			uart1_pins: uart1_pins {
409				pins = "PG6", "PG7";
410				function = "uart1";
411			};
412
413			uart1_rts_cts_pins: uart1_rts_cts_pins {
414				pins = "PG8", "PG9";
415				function = "uart1";
416			};
417
418			uart2_pins: uart2-pins {
419				pins = "PB0", "PB1";
420				function = "uart2";
421			};
422
423			uart3_pins: uart3-pins {
424				pins = "PD0", "PD1";
425				function = "uart3";
426			};
427
428			uart4_pins: uart4-pins {
429				pins = "PD2", "PD3";
430				function = "uart4";
431			};
432
433			uart4_rts_cts_pins: uart4-rts-cts-pins {
434				pins = "PD4", "PD5";
435				function = "uart4";
436			};
437		};
438
439		spdif: spdif@1c21000 {
440			#sound-dai-cells = <0>;
441			compatible = "allwinner,sun50i-a64-spdif",
442				     "allwinner,sun8i-h3-spdif";
443			reg = <0x01c21000 0x400>;
444			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
445			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
446			resets = <&ccu RST_BUS_SPDIF>;
447			clock-names = "apb", "spdif";
448			dmas = <&dma 2>;
449			dma-names = "tx";
450			pinctrl-names = "default";
451			pinctrl-0 = <&spdif_tx_pin>;
452			status = "disabled";
453		};
454
455		i2s0: i2s@1c22000 {
456			#sound-dai-cells = <0>;
457			compatible = "allwinner,sun50i-a64-i2s",
458				     "allwinner,sun8i-h3-i2s";
459			reg = <0x01c22000 0x400>;
460			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
461			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
462			clock-names = "apb", "mod";
463			resets = <&ccu RST_BUS_I2S0>;
464			dma-names = "rx", "tx";
465			dmas = <&dma 3>, <&dma 3>;
466			status = "disabled";
467		};
468
469		i2s1: i2s@1c22400 {
470			#sound-dai-cells = <0>;
471			compatible = "allwinner,sun50i-a64-i2s",
472				     "allwinner,sun8i-h3-i2s";
473			reg = <0x01c22400 0x400>;
474			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
475			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
476			clock-names = "apb", "mod";
477			resets = <&ccu RST_BUS_I2S1>;
478			dma-names = "rx", "tx";
479			dmas = <&dma 4>, <&dma 4>;
480			status = "disabled";
481		};
482
483		uart0: serial@1c28000 {
484			compatible = "snps,dw-apb-uart";
485			reg = <0x01c28000 0x400>;
486			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
487			reg-shift = <2>;
488			reg-io-width = <4>;
489			clocks = <&ccu CLK_BUS_UART0>;
490			resets = <&ccu RST_BUS_UART0>;
491			status = "disabled";
492		};
493
494		uart1: serial@1c28400 {
495			compatible = "snps,dw-apb-uart";
496			reg = <0x01c28400 0x400>;
497			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
498			reg-shift = <2>;
499			reg-io-width = <4>;
500			clocks = <&ccu CLK_BUS_UART1>;
501			resets = <&ccu RST_BUS_UART1>;
502			status = "disabled";
503		};
504
505		uart2: serial@1c28800 {
506			compatible = "snps,dw-apb-uart";
507			reg = <0x01c28800 0x400>;
508			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
509			reg-shift = <2>;
510			reg-io-width = <4>;
511			clocks = <&ccu CLK_BUS_UART2>;
512			resets = <&ccu RST_BUS_UART2>;
513			status = "disabled";
514		};
515
516		uart3: serial@1c28c00 {
517			compatible = "snps,dw-apb-uart";
518			reg = <0x01c28c00 0x400>;
519			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
520			reg-shift = <2>;
521			reg-io-width = <4>;
522			clocks = <&ccu CLK_BUS_UART3>;
523			resets = <&ccu RST_BUS_UART3>;
524			status = "disabled";
525		};
526
527		uart4: serial@1c29000 {
528			compatible = "snps,dw-apb-uart";
529			reg = <0x01c29000 0x400>;
530			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
531			reg-shift = <2>;
532			reg-io-width = <4>;
533			clocks = <&ccu CLK_BUS_UART4>;
534			resets = <&ccu RST_BUS_UART4>;
535			status = "disabled";
536		};
537
538		i2c0: i2c@1c2ac00 {
539			compatible = "allwinner,sun6i-a31-i2c";
540			reg = <0x01c2ac00 0x400>;
541			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
542			clocks = <&ccu CLK_BUS_I2C0>;
543			resets = <&ccu RST_BUS_I2C0>;
544			status = "disabled";
545			#address-cells = <1>;
546			#size-cells = <0>;
547		};
548
549		i2c1: i2c@1c2b000 {
550			compatible = "allwinner,sun6i-a31-i2c";
551			reg = <0x01c2b000 0x400>;
552			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
553			clocks = <&ccu CLK_BUS_I2C1>;
554			resets = <&ccu RST_BUS_I2C1>;
555			status = "disabled";
556			#address-cells = <1>;
557			#size-cells = <0>;
558		};
559
560		i2c2: i2c@1c2b400 {
561			compatible = "allwinner,sun6i-a31-i2c";
562			reg = <0x01c2b400 0x400>;
563			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
564			clocks = <&ccu CLK_BUS_I2C2>;
565			resets = <&ccu RST_BUS_I2C2>;
566			status = "disabled";
567			#address-cells = <1>;
568			#size-cells = <0>;
569		};
570
571
572		spi0: spi@1c68000 {
573			compatible = "allwinner,sun8i-h3-spi";
574			reg = <0x01c68000 0x1000>;
575			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
576			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
577			clock-names = "ahb", "mod";
578			dmas = <&dma 23>, <&dma 23>;
579			dma-names = "rx", "tx";
580			pinctrl-names = "default";
581			pinctrl-0 = <&spi0_pins>;
582			resets = <&ccu RST_BUS_SPI0>;
583			status = "disabled";
584			num-cs = <1>;
585			#address-cells = <1>;
586			#size-cells = <0>;
587		};
588
589		spi1: spi@1c69000 {
590			compatible = "allwinner,sun8i-h3-spi";
591			reg = <0x01c69000 0x1000>;
592			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
593			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
594			clock-names = "ahb", "mod";
595			dmas = <&dma 24>, <&dma 24>;
596			dma-names = "rx", "tx";
597			pinctrl-names = "default";
598			pinctrl-0 = <&spi1_pins>;
599			resets = <&ccu RST_BUS_SPI1>;
600			status = "disabled";
601			num-cs = <1>;
602			#address-cells = <1>;
603			#size-cells = <0>;
604		};
605
606		emac: ethernet@1c30000 {
607			compatible = "allwinner,sun50i-a64-emac";
608			syscon = <&syscon>;
609			reg = <0x01c30000 0x10000>;
610			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
611			interrupt-names = "macirq";
612			resets = <&ccu RST_BUS_EMAC>;
613			reset-names = "stmmaceth";
614			clocks = <&ccu CLK_BUS_EMAC>;
615			clock-names = "stmmaceth";
616			status = "disabled";
617			#address-cells = <1>;
618			#size-cells = <0>;
619
620			mdio: mdio {
621				compatible = "snps,dwmac-mdio";
622				#address-cells = <1>;
623				#size-cells = <0>;
624			};
625		};
626
627		gic: interrupt-controller@1c81000 {
628			compatible = "arm,gic-400";
629			reg = <0x01c81000 0x1000>,
630			      <0x01c82000 0x2000>,
631			      <0x01c84000 0x2000>,
632			      <0x01c86000 0x2000>;
633			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
634			interrupt-controller;
635			#interrupt-cells = <3>;
636		};
637
638		pwm: pwm@1c21400 {
639			compatible = "allwinner,sun50i-a64-pwm",
640				     "allwinner,sun5i-a13-pwm";
641			reg = <0x01c21400 0x400>;
642			clocks = <&osc24M>;
643			pinctrl-names = "default";
644			pinctrl-0 = <&pwm_pin>;
645			#pwm-cells = <3>;
646			status = "disabled";
647		};
648
649		rtc: rtc@1f00000 {
650			compatible = "allwinner,sun6i-a31-rtc";
651			reg = <0x01f00000 0x54>;
652			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
653				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
654			clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
655			clocks = <&osc32k>;
656			#clock-cells = <1>;
657		};
658
659		r_intc: interrupt-controller@1f00c00 {
660			compatible = "allwinner,sun50i-a64-r-intc",
661				     "allwinner,sun6i-a31-r-intc";
662			interrupt-controller;
663			#interrupt-cells = <2>;
664			reg = <0x01f00c00 0x400>;
665			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
666		};
667
668		r_ccu: clock@1f01400 {
669			compatible = "allwinner,sun50i-a64-r-ccu";
670			reg = <0x01f01400 0x100>;
671			clocks = <&osc24M>, <&osc32k>, <&iosc>,
672				 <&ccu 11>;
673			clock-names = "hosc", "losc", "iosc", "pll-periph";
674			#clock-cells = <1>;
675			#reset-cells = <1>;
676		};
677
678		r_i2c: i2c@1f02400 {
679			compatible = "allwinner,sun50i-a64-i2c",
680				     "allwinner,sun6i-a31-i2c";
681			reg = <0x01f02400 0x400>;
682			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
683			clocks = <&r_ccu CLK_APB0_I2C>;
684			resets = <&r_ccu RST_APB0_I2C>;
685			status = "disabled";
686			#address-cells = <1>;
687			#size-cells = <0>;
688		};
689
690		r_pwm: pwm@1f03800 {
691			compatible = "allwinner,sun50i-a64-pwm",
692				     "allwinner,sun5i-a13-pwm";
693			reg = <0x01f03800 0x400>;
694			clocks = <&osc24M>;
695			pinctrl-names = "default";
696			pinctrl-0 = <&r_pwm_pin>;
697			#pwm-cells = <3>;
698			status = "disabled";
699		};
700
701		r_pio: pinctrl@1f02c00 {
702			compatible = "allwinner,sun50i-a64-r-pinctrl";
703			reg = <0x01f02c00 0x400>;
704			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
705			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
706			clock-names = "apb", "hosc", "losc";
707			gpio-controller;
708			#gpio-cells = <3>;
709			interrupt-controller;
710			#interrupt-cells = <3>;
711
712			r_i2c_pins_a: i2c-a {
713				pins = "PL8", "PL9";
714				function = "s_i2c";
715			};
716
717			r_pwm_pin: pwm {
718				pins = "PL10";
719				function = "s_pwm";
720			};
721
722			r_rsb_pins: rsb {
723				pins = "PL0", "PL1";
724				function = "s_rsb";
725			};
726		};
727
728		r_rsb: rsb@1f03400 {
729			compatible = "allwinner,sun8i-a23-rsb";
730			reg = <0x01f03400 0x400>;
731			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
732			clocks = <&r_ccu 6>;
733			clock-frequency = <3000000>;
734			resets = <&r_ccu 2>;
735			pinctrl-names = "default";
736			pinctrl-0 = <&r_rsb_pins>;
737			status = "disabled";
738			#address-cells = <1>;
739			#size-cells = <0>;
740		};
741
742		wdt0: watchdog@1c20ca0 {
743			compatible = "allwinner,sun50i-a64-wdt",
744				     "allwinner,sun6i-a31-wdt";
745			reg = <0x01c20ca0 0x20>;
746			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
747		};
748	};
749};
750