1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 ARM Ltd. 4 * based on the Allwinner H3 dtsi: 5 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 6 */ 7 8#include <dt-bindings/clock/sun50i-a64-ccu.h> 9#include <dt-bindings/clock/sun8i-de2.h> 10#include <dt-bindings/clock/sun8i-r-ccu.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/sun50i-a64-ccu.h> 13#include <dt-bindings/reset/sun8i-de2.h> 14#include <dt-bindings/reset/sun8i-r-ccu.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 chosen { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges; 25 26 simplefb_lcd: framebuffer-lcd { 27 compatible = "allwinner,simple-framebuffer", 28 "simple-framebuffer"; 29 allwinner,pipeline = "mixer0-lcd0"; 30 clocks = <&ccu CLK_TCON0>, 31 <&display_clocks CLK_MIXER0>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "allwinner,simple-framebuffer", 37 "simple-framebuffer"; 38 allwinner,pipeline = "mixer1-lcd1-hdmi"; 39 clocks = <&display_clocks CLK_MIXER1>, 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 41 status = "disabled"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a53"; 51 device_type = "cpu"; 52 reg = <0>; 53 enable-method = "psci"; 54 next-level-cache = <&L2>; 55 }; 56 57 cpu1: cpu@1 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 reg = <1>; 61 enable-method = "psci"; 62 next-level-cache = <&L2>; 63 }; 64 65 cpu2: cpu@2 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 reg = <2>; 69 enable-method = "psci"; 70 next-level-cache = <&L2>; 71 }; 72 73 cpu3: cpu@3 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 reg = <3>; 77 enable-method = "psci"; 78 next-level-cache = <&L2>; 79 }; 80 81 L2: l2-cache { 82 compatible = "cache"; 83 cache-level = <2>; 84 }; 85 }; 86 87 de: display-engine { 88 compatible = "allwinner,sun50i-a64-display-engine"; 89 allwinner,pipelines = <&mixer0>, 90 <&mixer1>; 91 status = "disabled"; 92 }; 93 94 osc24M: osc24M_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <24000000>; 98 clock-output-names = "osc24M"; 99 }; 100 101 osc32k: osc32k_clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 clock-frequency = <32768>; 105 clock-output-names = "ext-osc32k"; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 sound: sound { 123 compatible = "simple-audio-card"; 124 simple-audio-card,name = "sun50i-a64-audio"; 125 simple-audio-card,format = "i2s"; 126 simple-audio-card,frame-master = <&cpudai>; 127 simple-audio-card,bitclock-master = <&cpudai>; 128 simple-audio-card,mclk-fs = <128>; 129 simple-audio-card,aux-devs = <&codec_analog>; 130 simple-audio-card,routing = 131 "Left DAC", "AIF1 Slot 0 Left", 132 "Right DAC", "AIF1 Slot 0 Right", 133 "AIF1 Slot 0 Left ADC", "Left ADC", 134 "AIF1 Slot 0 Right ADC", "Right ADC"; 135 status = "disabled"; 136 137 cpudai: simple-audio-card,cpu { 138 sound-dai = <&dai>; 139 }; 140 141 link_codec: simple-audio-card,codec { 142 sound-dai = <&codec>; 143 }; 144 }; 145 146 sound_spdif { 147 compatible = "simple-audio-card"; 148 simple-audio-card,name = "On-board SPDIF"; 149 150 simple-audio-card,cpu { 151 sound-dai = <&spdif>; 152 }; 153 154 simple-audio-card,codec { 155 sound-dai = <&spdif_out>; 156 }; 157 }; 158 159 spdif_out: spdif-out { 160 #sound-dai-cells = <0>; 161 compatible = "linux,spdif-dit"; 162 }; 163 164 timer { 165 compatible = "arm,armv8-timer"; 166 allwinner,erratum-unknown1; 167 interrupts = <GIC_PPI 13 168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 169 <GIC_PPI 14 170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 171 <GIC_PPI 11 172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 173 <GIC_PPI 10 174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 175 }; 176 177 soc { 178 compatible = "simple-bus"; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 ranges; 182 183 bus@1000000 { 184 compatible = "allwinner,sun50i-a64-de2"; 185 reg = <0x1000000 0x400000>; 186 allwinner,sram = <&de2_sram 1>; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 ranges = <0 0x1000000 0x400000>; 190 191 display_clocks: clock@0 { 192 compatible = "allwinner,sun50i-a64-de2-clk"; 193 reg = <0x0 0x100000>; 194 clocks = <&ccu CLK_BUS_DE>, 195 <&ccu CLK_DE>; 196 clock-names = "bus", 197 "mod"; 198 resets = <&ccu RST_BUS_DE>; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 }; 202 203 mixer0: mixer@100000 { 204 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 205 reg = <0x100000 0x100000>; 206 clocks = <&display_clocks CLK_BUS_MIXER0>, 207 <&display_clocks CLK_MIXER0>; 208 clock-names = "bus", 209 "mod"; 210 resets = <&display_clocks RST_MIXER0>; 211 212 ports { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 mixer0_out: port@1 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 reg = <1>; 220 221 mixer0_out_tcon0: endpoint@0 { 222 reg = <0>; 223 remote-endpoint = <&tcon0_in_mixer0>; 224 }; 225 226 mixer0_out_tcon1: endpoint@1 { 227 reg = <1>; 228 remote-endpoint = <&tcon1_in_mixer0>; 229 }; 230 }; 231 }; 232 }; 233 234 mixer1: mixer@200000 { 235 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 236 reg = <0x200000 0x100000>; 237 clocks = <&display_clocks CLK_BUS_MIXER1>, 238 <&display_clocks CLK_MIXER1>; 239 clock-names = "bus", 240 "mod"; 241 resets = <&display_clocks RST_MIXER1>; 242 243 ports { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 mixer1_out: port@1 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 reg = <1>; 251 252 mixer1_out_tcon0: endpoint@0 { 253 reg = <0>; 254 remote-endpoint = <&tcon0_in_mixer1>; 255 }; 256 257 mixer1_out_tcon1: endpoint@1 { 258 reg = <1>; 259 remote-endpoint = <&tcon1_in_mixer1>; 260 }; 261 }; 262 }; 263 }; 264 }; 265 266 syscon: syscon@1c00000 { 267 compatible = "allwinner,sun50i-a64-system-control"; 268 reg = <0x01c00000 0x1000>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges; 272 273 sram_c: sram@18000 { 274 compatible = "mmio-sram"; 275 reg = <0x00018000 0x28000>; 276 #address-cells = <1>; 277 #size-cells = <1>; 278 ranges = <0 0x00018000 0x28000>; 279 280 de2_sram: sram-section@0 { 281 compatible = "allwinner,sun50i-a64-sram-c"; 282 reg = <0x0000 0x28000>; 283 }; 284 }; 285 286 sram_c1: sram@1d00000 { 287 compatible = "mmio-sram"; 288 reg = <0x01d00000 0x40000>; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges = <0 0x01d00000 0x40000>; 292 293 ve_sram: sram-section@0 { 294 compatible = "allwinner,sun50i-a64-sram-c1", 295 "allwinner,sun4i-a10-sram-c1"; 296 reg = <0x000000 0x40000>; 297 }; 298 }; 299 }; 300 301 dma: dma-controller@1c02000 { 302 compatible = "allwinner,sun50i-a64-dma"; 303 reg = <0x01c02000 0x1000>; 304 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&ccu CLK_BUS_DMA>; 306 dma-channels = <8>; 307 dma-requests = <27>; 308 resets = <&ccu RST_BUS_DMA>; 309 #dma-cells = <1>; 310 }; 311 312 tcon0: lcd-controller@1c0c000 { 313 compatible = "allwinner,sun50i-a64-tcon-lcd", 314 "allwinner,sun8i-a83t-tcon-lcd"; 315 reg = <0x01c0c000 0x1000>; 316 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 318 clock-names = "ahb", "tcon-ch0"; 319 clock-output-names = "tcon-pixel-clock"; 320 #clock-cells = <0>; 321 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 322 reset-names = "lcd", "lvds"; 323 324 ports { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 328 tcon0_in: port@0 { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 reg = <0>; 332 333 tcon0_in_mixer0: endpoint@0 { 334 reg = <0>; 335 remote-endpoint = <&mixer0_out_tcon0>; 336 }; 337 338 tcon0_in_mixer1: endpoint@1 { 339 reg = <1>; 340 remote-endpoint = <&mixer1_out_tcon0>; 341 }; 342 }; 343 344 tcon0_out: port@1 { 345 #address-cells = <1>; 346 #size-cells = <0>; 347 reg = <1>; 348 }; 349 }; 350 }; 351 352 tcon1: lcd-controller@1c0d000 { 353 compatible = "allwinner,sun50i-a64-tcon-tv", 354 "allwinner,sun8i-a83t-tcon-tv"; 355 reg = <0x01c0d000 0x1000>; 356 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 358 clock-names = "ahb", "tcon-ch1"; 359 resets = <&ccu RST_BUS_TCON1>; 360 reset-names = "lcd"; 361 362 ports { 363 #address-cells = <1>; 364 #size-cells = <0>; 365 366 tcon1_in: port@0 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <0>; 370 371 tcon1_in_mixer0: endpoint@0 { 372 reg = <0>; 373 remote-endpoint = <&mixer0_out_tcon1>; 374 }; 375 376 tcon1_in_mixer1: endpoint@1 { 377 reg = <1>; 378 remote-endpoint = <&mixer1_out_tcon1>; 379 }; 380 }; 381 382 tcon1_out: port@1 { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 reg = <1>; 386 387 tcon1_out_hdmi: endpoint@1 { 388 reg = <1>; 389 remote-endpoint = <&hdmi_in_tcon1>; 390 }; 391 }; 392 }; 393 }; 394 395 video-codec@1c0e000 { 396 compatible = "allwinner,sun50i-a64-video-engine"; 397 reg = <0x01c0e000 0x1000>; 398 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 399 <&ccu CLK_DRAM_VE>; 400 clock-names = "ahb", "mod", "ram"; 401 resets = <&ccu RST_BUS_VE>; 402 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 403 allwinner,sram = <&ve_sram 1>; 404 }; 405 406 mmc0: mmc@1c0f000 { 407 compatible = "allwinner,sun50i-a64-mmc"; 408 reg = <0x01c0f000 0x1000>; 409 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 410 clock-names = "ahb", "mmc"; 411 resets = <&ccu RST_BUS_MMC0>; 412 reset-names = "ahb"; 413 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 414 max-frequency = <150000000>; 415 status = "disabled"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 }; 419 420 mmc1: mmc@1c10000 { 421 compatible = "allwinner,sun50i-a64-mmc"; 422 reg = <0x01c10000 0x1000>; 423 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 424 clock-names = "ahb", "mmc"; 425 resets = <&ccu RST_BUS_MMC1>; 426 reset-names = "ahb"; 427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 428 max-frequency = <150000000>; 429 status = "disabled"; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 }; 433 434 mmc2: mmc@1c11000 { 435 compatible = "allwinner,sun50i-a64-emmc"; 436 reg = <0x01c11000 0x1000>; 437 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 438 clock-names = "ahb", "mmc"; 439 resets = <&ccu RST_BUS_MMC2>; 440 reset-names = "ahb"; 441 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 442 max-frequency = <200000000>; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 sid: eeprom@1c14000 { 449 compatible = "allwinner,sun50i-a64-sid"; 450 reg = <0x1c14000 0x400>; 451 }; 452 453 crypto: crypto@1c15000 { 454 compatible = "allwinner,sun50i-a64-crypto"; 455 reg = <0x01c15000 0x1000>; 456 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 458 clock-names = "bus", "mod"; 459 resets = <&ccu RST_BUS_CE>; 460 }; 461 462 usb_otg: usb@1c19000 { 463 compatible = "allwinner,sun8i-a33-musb"; 464 reg = <0x01c19000 0x0400>; 465 clocks = <&ccu CLK_BUS_OTG>; 466 resets = <&ccu RST_BUS_OTG>; 467 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "mc"; 469 phys = <&usbphy 0>; 470 phy-names = "usb"; 471 extcon = <&usbphy 0>; 472 dr_mode = "otg"; 473 status = "disabled"; 474 }; 475 476 usbphy: phy@1c19400 { 477 compatible = "allwinner,sun50i-a64-usb-phy"; 478 reg = <0x01c19400 0x14>, 479 <0x01c1a800 0x4>, 480 <0x01c1b800 0x4>; 481 reg-names = "phy_ctrl", 482 "pmu0", 483 "pmu1"; 484 clocks = <&ccu CLK_USB_PHY0>, 485 <&ccu CLK_USB_PHY1>; 486 clock-names = "usb0_phy", 487 "usb1_phy"; 488 resets = <&ccu RST_USB_PHY0>, 489 <&ccu RST_USB_PHY1>; 490 reset-names = "usb0_reset", 491 "usb1_reset"; 492 status = "disabled"; 493 #phy-cells = <1>; 494 }; 495 496 ehci0: usb@1c1a000 { 497 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 498 reg = <0x01c1a000 0x100>; 499 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&ccu CLK_BUS_OHCI0>, 501 <&ccu CLK_BUS_EHCI0>, 502 <&ccu CLK_USB_OHCI0>; 503 resets = <&ccu RST_BUS_OHCI0>, 504 <&ccu RST_BUS_EHCI0>; 505 status = "disabled"; 506 }; 507 508 ohci0: usb@1c1a400 { 509 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 510 reg = <0x01c1a400 0x100>; 511 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&ccu CLK_BUS_OHCI0>, 513 <&ccu CLK_USB_OHCI0>; 514 resets = <&ccu RST_BUS_OHCI0>; 515 status = "disabled"; 516 }; 517 518 ehci1: usb@1c1b000 { 519 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 520 reg = <0x01c1b000 0x100>; 521 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&ccu CLK_BUS_OHCI1>, 523 <&ccu CLK_BUS_EHCI1>, 524 <&ccu CLK_USB_OHCI1>; 525 resets = <&ccu RST_BUS_OHCI1>, 526 <&ccu RST_BUS_EHCI1>; 527 phys = <&usbphy 1>; 528 phy-names = "usb"; 529 status = "disabled"; 530 }; 531 532 ohci1: usb@1c1b400 { 533 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 534 reg = <0x01c1b400 0x100>; 535 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&ccu CLK_BUS_OHCI1>, 537 <&ccu CLK_USB_OHCI1>; 538 resets = <&ccu RST_BUS_OHCI1>; 539 phys = <&usbphy 1>; 540 phy-names = "usb"; 541 status = "disabled"; 542 }; 543 544 ccu: clock@1c20000 { 545 compatible = "allwinner,sun50i-a64-ccu"; 546 reg = <0x01c20000 0x400>; 547 clocks = <&osc24M>, <&rtc 0>; 548 clock-names = "hosc", "losc"; 549 #clock-cells = <1>; 550 #reset-cells = <1>; 551 }; 552 553 pio: pinctrl@1c20800 { 554 compatible = "allwinner,sun50i-a64-pinctrl"; 555 reg = <0x01c20800 0x400>; 556 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 560 clock-names = "apb", "hosc", "losc"; 561 gpio-controller; 562 #gpio-cells = <3>; 563 interrupt-controller; 564 #interrupt-cells = <3>; 565 566 csi_pins: csi-pins { 567 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 568 "PE7", "PE8", "PE9", "PE10", "PE11"; 569 function = "csi"; 570 }; 571 572 /omit-if-no-ref/ 573 csi_mclk_pin: csi-mclk-pin { 574 pins = "PE1"; 575 function = "csi"; 576 }; 577 578 i2c0_pins: i2c0-pins { 579 pins = "PH0", "PH1"; 580 function = "i2c0"; 581 }; 582 583 i2c1_pins: i2c1-pins { 584 pins = "PH2", "PH3"; 585 function = "i2c1"; 586 }; 587 588 /omit-if-no-ref/ 589 lcd_rgb666_pins: lcd-rgb666-pins { 590 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 591 "PD5", "PD6", "PD7", "PD8", "PD9", 592 "PD10", "PD11", "PD12", "PD13", 593 "PD14", "PD15", "PD16", "PD17", 594 "PD18", "PD19", "PD20", "PD21"; 595 function = "lcd0"; 596 }; 597 598 mmc0_pins: mmc0-pins { 599 pins = "PF0", "PF1", "PF2", "PF3", 600 "PF4", "PF5"; 601 function = "mmc0"; 602 drive-strength = <30>; 603 bias-pull-up; 604 }; 605 606 mmc1_pins: mmc1-pins { 607 pins = "PG0", "PG1", "PG2", "PG3", 608 "PG4", "PG5"; 609 function = "mmc1"; 610 drive-strength = <30>; 611 bias-pull-up; 612 }; 613 614 mmc2_pins: mmc2-pins { 615 pins = "PC5", "PC6", "PC8", "PC9", 616 "PC10","PC11", "PC12", "PC13", 617 "PC14", "PC15", "PC16"; 618 function = "mmc2"; 619 drive-strength = <30>; 620 bias-pull-up; 621 }; 622 623 mmc2_ds_pin: mmc2-ds-pin { 624 pins = "PC1"; 625 function = "mmc2"; 626 drive-strength = <30>; 627 bias-pull-up; 628 }; 629 630 pwm_pin: pwm-pin { 631 pins = "PD22"; 632 function = "pwm"; 633 }; 634 635 rmii_pins: rmii-pins { 636 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 637 "PD18", "PD19", "PD20", "PD22", "PD23"; 638 function = "emac"; 639 drive-strength = <40>; 640 }; 641 642 rgmii_pins: rgmii-pins { 643 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 644 "PD13", "PD15", "PD16", "PD17", "PD18", 645 "PD19", "PD20", "PD21", "PD22", "PD23"; 646 function = "emac"; 647 drive-strength = <40>; 648 }; 649 650 spdif_tx_pin: spdif-tx-pin { 651 pins = "PH8"; 652 function = "spdif"; 653 }; 654 655 spi0_pins: spi0-pins { 656 pins = "PC0", "PC1", "PC2", "PC3"; 657 function = "spi0"; 658 }; 659 660 spi1_pins: spi1-pins { 661 pins = "PD0", "PD1", "PD2", "PD3"; 662 function = "spi1"; 663 }; 664 665 uart0_pb_pins: uart0-pb-pins { 666 pins = "PB8", "PB9"; 667 function = "uart0"; 668 }; 669 670 uart1_pins: uart1-pins { 671 pins = "PG6", "PG7"; 672 function = "uart1"; 673 }; 674 675 uart1_rts_cts_pins: uart1-rts-cts-pins { 676 pins = "PG8", "PG9"; 677 function = "uart1"; 678 }; 679 680 uart2_pins: uart2-pins { 681 pins = "PB0", "PB1"; 682 function = "uart2"; 683 }; 684 685 uart3_pins: uart3-pins { 686 pins = "PD0", "PD1"; 687 function = "uart3"; 688 }; 689 690 uart4_pins: uart4-pins { 691 pins = "PD2", "PD3"; 692 function = "uart4"; 693 }; 694 695 uart4_rts_cts_pins: uart4-rts-cts-pins { 696 pins = "PD4", "PD5"; 697 function = "uart4"; 698 }; 699 }; 700 701 spdif: spdif@1c21000 { 702 #sound-dai-cells = <0>; 703 compatible = "allwinner,sun50i-a64-spdif", 704 "allwinner,sun8i-h3-spdif"; 705 reg = <0x01c21000 0x400>; 706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 708 resets = <&ccu RST_BUS_SPDIF>; 709 clock-names = "apb", "spdif"; 710 dmas = <&dma 2>; 711 dma-names = "tx"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&spdif_tx_pin>; 714 status = "disabled"; 715 }; 716 717 lradc: lradc@1c21800 { 718 compatible = "allwinner,sun50i-a64-lradc", 719 "allwinner,sun8i-a83t-r-lradc"; 720 reg = <0x01c21800 0x400>; 721 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 722 status = "disabled"; 723 }; 724 725 i2s0: i2s@1c22000 { 726 #sound-dai-cells = <0>; 727 compatible = "allwinner,sun50i-a64-i2s", 728 "allwinner,sun8i-h3-i2s"; 729 reg = <0x01c22000 0x400>; 730 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 732 clock-names = "apb", "mod"; 733 resets = <&ccu RST_BUS_I2S0>; 734 dma-names = "rx", "tx"; 735 dmas = <&dma 3>, <&dma 3>; 736 status = "disabled"; 737 }; 738 739 i2s1: i2s@1c22400 { 740 #sound-dai-cells = <0>; 741 compatible = "allwinner,sun50i-a64-i2s", 742 "allwinner,sun8i-h3-i2s"; 743 reg = <0x01c22400 0x400>; 744 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 746 clock-names = "apb", "mod"; 747 resets = <&ccu RST_BUS_I2S1>; 748 dma-names = "rx", "tx"; 749 dmas = <&dma 4>, <&dma 4>; 750 status = "disabled"; 751 }; 752 753 dai: dai@1c22c00 { 754 #sound-dai-cells = <0>; 755 compatible = "allwinner,sun50i-a64-codec-i2s"; 756 reg = <0x01c22c00 0x200>; 757 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 759 clock-names = "apb", "mod"; 760 resets = <&ccu RST_BUS_CODEC>; 761 dmas = <&dma 15>, <&dma 15>; 762 dma-names = "rx", "tx"; 763 status = "disabled"; 764 }; 765 766 codec: codec@1c22e00 { 767 #sound-dai-cells = <0>; 768 compatible = "allwinner,sun8i-a33-codec"; 769 reg = <0x01c22e00 0x600>; 770 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 772 clock-names = "bus", "mod"; 773 status = "disabled"; 774 }; 775 776 uart0: serial@1c28000 { 777 compatible = "snps,dw-apb-uart"; 778 reg = <0x01c28000 0x400>; 779 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 780 reg-shift = <2>; 781 reg-io-width = <4>; 782 clocks = <&ccu CLK_BUS_UART0>; 783 resets = <&ccu RST_BUS_UART0>; 784 status = "disabled"; 785 }; 786 787 uart1: serial@1c28400 { 788 compatible = "snps,dw-apb-uart"; 789 reg = <0x01c28400 0x400>; 790 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 791 reg-shift = <2>; 792 reg-io-width = <4>; 793 clocks = <&ccu CLK_BUS_UART1>; 794 resets = <&ccu RST_BUS_UART1>; 795 status = "disabled"; 796 }; 797 798 uart2: serial@1c28800 { 799 compatible = "snps,dw-apb-uart"; 800 reg = <0x01c28800 0x400>; 801 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 802 reg-shift = <2>; 803 reg-io-width = <4>; 804 clocks = <&ccu CLK_BUS_UART2>; 805 resets = <&ccu RST_BUS_UART2>; 806 status = "disabled"; 807 }; 808 809 uart3: serial@1c28c00 { 810 compatible = "snps,dw-apb-uart"; 811 reg = <0x01c28c00 0x400>; 812 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 813 reg-shift = <2>; 814 reg-io-width = <4>; 815 clocks = <&ccu CLK_BUS_UART3>; 816 resets = <&ccu RST_BUS_UART3>; 817 status = "disabled"; 818 }; 819 820 uart4: serial@1c29000 { 821 compatible = "snps,dw-apb-uart"; 822 reg = <0x01c29000 0x400>; 823 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 824 reg-shift = <2>; 825 reg-io-width = <4>; 826 clocks = <&ccu CLK_BUS_UART4>; 827 resets = <&ccu RST_BUS_UART4>; 828 status = "disabled"; 829 }; 830 831 i2c0: i2c@1c2ac00 { 832 compatible = "allwinner,sun6i-a31-i2c"; 833 reg = <0x01c2ac00 0x400>; 834 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&ccu CLK_BUS_I2C0>; 836 resets = <&ccu RST_BUS_I2C0>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&i2c0_pins>; 839 status = "disabled"; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 }; 843 844 i2c1: i2c@1c2b000 { 845 compatible = "allwinner,sun6i-a31-i2c"; 846 reg = <0x01c2b000 0x400>; 847 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&ccu CLK_BUS_I2C1>; 849 resets = <&ccu RST_BUS_I2C1>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&i2c1_pins>; 852 status = "disabled"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 }; 856 857 i2c2: i2c@1c2b400 { 858 compatible = "allwinner,sun6i-a31-i2c"; 859 reg = <0x01c2b400 0x400>; 860 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&ccu CLK_BUS_I2C2>; 862 resets = <&ccu RST_BUS_I2C2>; 863 status = "disabled"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 }; 867 868 869 spi0: spi@1c68000 { 870 compatible = "allwinner,sun8i-h3-spi"; 871 reg = <0x01c68000 0x1000>; 872 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 874 clock-names = "ahb", "mod"; 875 dmas = <&dma 23>, <&dma 23>; 876 dma-names = "rx", "tx"; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&spi0_pins>; 879 resets = <&ccu RST_BUS_SPI0>; 880 status = "disabled"; 881 num-cs = <1>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 }; 885 886 spi1: spi@1c69000 { 887 compatible = "allwinner,sun8i-h3-spi"; 888 reg = <0x01c69000 0x1000>; 889 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 891 clock-names = "ahb", "mod"; 892 dmas = <&dma 24>, <&dma 24>; 893 dma-names = "rx", "tx"; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&spi1_pins>; 896 resets = <&ccu RST_BUS_SPI1>; 897 status = "disabled"; 898 num-cs = <1>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 }; 902 903 emac: ethernet@1c30000 { 904 compatible = "allwinner,sun50i-a64-emac"; 905 syscon = <&syscon>; 906 reg = <0x01c30000 0x10000>; 907 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "macirq"; 909 resets = <&ccu RST_BUS_EMAC>; 910 reset-names = "stmmaceth"; 911 clocks = <&ccu CLK_BUS_EMAC>; 912 clock-names = "stmmaceth"; 913 status = "disabled"; 914 915 mdio: mdio { 916 compatible = "snps,dwmac-mdio"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 }; 920 }; 921 922 mali: gpu@1c40000 { 923 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 924 reg = <0x01c40000 0x10000>; 925 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 932 interrupt-names = "gp", 933 "gpmmu", 934 "pp0", 935 "ppmmu0", 936 "pp1", 937 "ppmmu1", 938 "pmu"; 939 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 940 clock-names = "bus", "core"; 941 resets = <&ccu RST_BUS_GPU>; 942 }; 943 944 gic: interrupt-controller@1c81000 { 945 compatible = "arm,gic-400"; 946 reg = <0x01c81000 0x1000>, 947 <0x01c82000 0x2000>, 948 <0x01c84000 0x2000>, 949 <0x01c86000 0x2000>; 950 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 951 interrupt-controller; 952 #interrupt-cells = <3>; 953 }; 954 955 pwm: pwm@1c21400 { 956 compatible = "allwinner,sun50i-a64-pwm", 957 "allwinner,sun5i-a13-pwm"; 958 reg = <0x01c21400 0x400>; 959 clocks = <&osc24M>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&pwm_pin>; 962 #pwm-cells = <3>; 963 status = "disabled"; 964 }; 965 966 csi: csi@1cb0000 { 967 compatible = "allwinner,sun50i-a64-csi"; 968 reg = <0x01cb0000 0x1000>; 969 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&ccu CLK_BUS_CSI>, 971 <&ccu CLK_CSI_SCLK>, 972 <&ccu CLK_DRAM_CSI>; 973 clock-names = "bus", "mod", "ram"; 974 resets = <&ccu RST_BUS_CSI>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&csi_pins>; 977 status = "disabled"; 978 }; 979 980 hdmi: hdmi@1ee0000 { 981 compatible = "allwinner,sun50i-a64-dw-hdmi", 982 "allwinner,sun8i-a83t-dw-hdmi"; 983 reg = <0x01ee0000 0x10000>; 984 reg-io-width = <1>; 985 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 987 <&ccu CLK_HDMI>; 988 clock-names = "iahb", "isfr", "tmds"; 989 resets = <&ccu RST_BUS_HDMI1>; 990 reset-names = "ctrl"; 991 phys = <&hdmi_phy>; 992 phy-names = "phy"; 993 status = "disabled"; 994 995 ports { 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 hdmi_in: port@0 { 1000 reg = <0>; 1001 1002 hdmi_in_tcon1: endpoint { 1003 remote-endpoint = <&tcon1_out_hdmi>; 1004 }; 1005 }; 1006 1007 hdmi_out: port@1 { 1008 reg = <1>; 1009 }; 1010 }; 1011 }; 1012 1013 hdmi_phy: hdmi-phy@1ef0000 { 1014 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1015 reg = <0x01ef0000 0x10000>; 1016 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1017 <&ccu 7>; 1018 clock-names = "bus", "mod", "pll-0"; 1019 resets = <&ccu RST_BUS_HDMI0>; 1020 reset-names = "phy"; 1021 #phy-cells = <0>; 1022 }; 1023 1024 rtc: rtc@1f00000 { 1025 compatible = "allwinner,sun50i-a64-rtc", 1026 "allwinner,sun8i-h3-rtc"; 1027 reg = <0x01f00000 0x400>; 1028 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1030 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1031 clocks = <&osc32k>; 1032 #clock-cells = <1>; 1033 }; 1034 1035 r_intc: interrupt-controller@1f00c00 { 1036 compatible = "allwinner,sun50i-a64-r-intc", 1037 "allwinner,sun6i-a31-r-intc"; 1038 interrupt-controller; 1039 #interrupt-cells = <2>; 1040 reg = <0x01f00c00 0x400>; 1041 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1042 }; 1043 1044 r_ccu: clock@1f01400 { 1045 compatible = "allwinner,sun50i-a64-r-ccu"; 1046 reg = <0x01f01400 0x100>; 1047 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1048 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1049 #clock-cells = <1>; 1050 #reset-cells = <1>; 1051 }; 1052 1053 codec_analog: codec-analog@1f015c0 { 1054 compatible = "allwinner,sun50i-a64-codec-analog"; 1055 reg = <0x01f015c0 0x4>; 1056 status = "disabled"; 1057 }; 1058 1059 r_i2c: i2c@1f02400 { 1060 compatible = "allwinner,sun50i-a64-i2c", 1061 "allwinner,sun6i-a31-i2c"; 1062 reg = <0x01f02400 0x400>; 1063 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&r_ccu CLK_APB0_I2C>; 1065 resets = <&r_ccu RST_APB0_I2C>; 1066 status = "disabled"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 }; 1070 1071 r_ir: ir@1f02000 { 1072 compatible = "allwinner,sun50i-a64-ir", 1073 "allwinner,sun6i-a31-ir"; 1074 reg = <0x01f02000 0x400>; 1075 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1076 clock-names = "apb", "ir"; 1077 resets = <&r_ccu RST_APB0_IR>; 1078 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&r_ir_rx_pin>; 1081 status = "disabled"; 1082 }; 1083 1084 r_pwm: pwm@1f03800 { 1085 compatible = "allwinner,sun50i-a64-pwm", 1086 "allwinner,sun5i-a13-pwm"; 1087 reg = <0x01f03800 0x400>; 1088 clocks = <&osc24M>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&r_pwm_pin>; 1091 #pwm-cells = <3>; 1092 status = "disabled"; 1093 }; 1094 1095 r_pio: pinctrl@1f02c00 { 1096 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1097 reg = <0x01f02c00 0x400>; 1098 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1100 clock-names = "apb", "hosc", "losc"; 1101 gpio-controller; 1102 #gpio-cells = <3>; 1103 interrupt-controller; 1104 #interrupt-cells = <3>; 1105 1106 r_i2c_pl89_pins: r-i2c-pl89-pins { 1107 pins = "PL8", "PL9"; 1108 function = "s_i2c"; 1109 }; 1110 1111 r_ir_rx_pin: r-ir-rx-pin { 1112 pins = "PL11"; 1113 function = "s_cir_rx"; 1114 }; 1115 1116 r_pwm_pin: r-pwm-pin { 1117 pins = "PL10"; 1118 function = "s_pwm"; 1119 }; 1120 1121 r_rsb_pins: r-rsb-pins { 1122 pins = "PL0", "PL1"; 1123 function = "s_rsb"; 1124 }; 1125 }; 1126 1127 r_rsb: rsb@1f03400 { 1128 compatible = "allwinner,sun8i-a23-rsb"; 1129 reg = <0x01f03400 0x400>; 1130 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&r_ccu 6>; 1132 clock-frequency = <3000000>; 1133 resets = <&r_ccu 2>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&r_rsb_pins>; 1136 status = "disabled"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 }; 1140 1141 wdt0: watchdog@1c20ca0 { 1142 compatible = "allwinner,sun50i-a64-wdt", 1143 "allwinner,sun6i-a31-wdt"; 1144 reg = <0x01c20ca0 0x20>; 1145 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&osc24M>; 1147 }; 1148 }; 1149}; 1150