1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 }; 92 93 cpu1: cpu@1 { 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <1>; 97 enable-method = "psci"; 98 }; 99 100 cpu2: cpu@2 { 101 compatible = "arm,cortex-a53", "arm,armv8"; 102 device_type = "cpu"; 103 reg = <2>; 104 enable-method = "psci"; 105 }; 106 107 cpu3: cpu@3 { 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 device_type = "cpu"; 110 reg = <3>; 111 enable-method = "psci"; 112 }; 113 }; 114 115 osc24M: osc24M_clk { 116 #clock-cells = <0>; 117 compatible = "fixed-clock"; 118 clock-frequency = <24000000>; 119 clock-output-names = "osc24M"; 120 }; 121 122 osc32k: osc32k_clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 clock-frequency = <32768>; 126 clock-output-names = "osc32k"; 127 }; 128 129 iosc: internal-osc-clk { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 clock-frequency = <16000000>; 133 clock-accuracy = <300000000>; 134 clock-output-names = "iosc"; 135 }; 136 137 psci { 138 compatible = "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 sound_spdif { 143 compatible = "simple-audio-card"; 144 simple-audio-card,name = "On-board SPDIF"; 145 146 simple-audio-card,cpu { 147 sound-dai = <&spdif>; 148 }; 149 150 simple-audio-card,codec { 151 sound-dai = <&spdif_out>; 152 }; 153 }; 154 155 spdif_out: spdif-out { 156 #sound-dai-cells = <0>; 157 compatible = "linux,spdif-dit"; 158 }; 159 160 timer { 161 compatible = "arm,armv8-timer"; 162 interrupts = <GIC_PPI 13 163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 164 <GIC_PPI 14 165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 166 <GIC_PPI 11 167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 168 <GIC_PPI 10 169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 170 }; 171 172 soc { 173 compatible = "simple-bus"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 178 de2@1000000 { 179 compatible = "allwinner,sun50i-a64-de2"; 180 reg = <0x1000000 0x400000>; 181 allwinner,sram = <&de2_sram 1>; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 ranges = <0 0x1000000 0x400000>; 185 186 display_clocks: clock@0 { 187 compatible = "allwinner,sun50i-a64-de2-clk"; 188 reg = <0x0 0x100000>; 189 clocks = <&ccu CLK_DE>, 190 <&ccu CLK_BUS_DE>; 191 clock-names = "mod", 192 "bus"; 193 resets = <&ccu RST_BUS_DE>; 194 #clock-cells = <1>; 195 #reset-cells = <1>; 196 }; 197 }; 198 199 syscon: syscon@1c00000 { 200 compatible = "allwinner,sun50i-a64-system-control"; 201 reg = <0x01c00000 0x1000>; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges; 205 206 sram_c: sram@18000 { 207 compatible = "mmio-sram"; 208 reg = <0x00018000 0x28000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0 0x00018000 0x28000>; 212 213 de2_sram: sram-section@0 { 214 compatible = "allwinner,sun50i-a64-sram-c"; 215 reg = <0x0000 0x28000>; 216 }; 217 }; 218 }; 219 220 dma: dma-controller@1c02000 { 221 compatible = "allwinner,sun50i-a64-dma"; 222 reg = <0x01c02000 0x1000>; 223 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&ccu CLK_BUS_DMA>; 225 dma-channels = <8>; 226 dma-requests = <27>; 227 resets = <&ccu RST_BUS_DMA>; 228 #dma-cells = <1>; 229 }; 230 231 mmc0: mmc@1c0f000 { 232 compatible = "allwinner,sun50i-a64-mmc"; 233 reg = <0x01c0f000 0x1000>; 234 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 235 clock-names = "ahb", "mmc"; 236 resets = <&ccu RST_BUS_MMC0>; 237 reset-names = "ahb"; 238 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 239 max-frequency = <150000000>; 240 status = "disabled"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 }; 244 245 mmc1: mmc@1c10000 { 246 compatible = "allwinner,sun50i-a64-mmc"; 247 reg = <0x01c10000 0x1000>; 248 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 249 clock-names = "ahb", "mmc"; 250 resets = <&ccu RST_BUS_MMC1>; 251 reset-names = "ahb"; 252 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 253 max-frequency = <150000000>; 254 status = "disabled"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 mmc2: mmc@1c11000 { 260 compatible = "allwinner,sun50i-a64-emmc"; 261 reg = <0x01c11000 0x1000>; 262 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 263 clock-names = "ahb", "mmc"; 264 resets = <&ccu RST_BUS_MMC2>; 265 reset-names = "ahb"; 266 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 267 max-frequency = <200000000>; 268 status = "disabled"; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 }; 272 273 sid: eeprom@1c14000 { 274 compatible = "allwinner,sun50i-a64-sid"; 275 reg = <0x1c14000 0x400>; 276 }; 277 278 usb_otg: usb@1c19000 { 279 compatible = "allwinner,sun8i-a33-musb"; 280 reg = <0x01c19000 0x0400>; 281 clocks = <&ccu CLK_BUS_OTG>; 282 resets = <&ccu RST_BUS_OTG>; 283 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-names = "mc"; 285 phys = <&usbphy 0>; 286 phy-names = "usb"; 287 extcon = <&usbphy 0>; 288 status = "disabled"; 289 }; 290 291 usbphy: phy@1c19400 { 292 compatible = "allwinner,sun50i-a64-usb-phy"; 293 reg = <0x01c19400 0x14>, 294 <0x01c1a800 0x4>, 295 <0x01c1b800 0x4>; 296 reg-names = "phy_ctrl", 297 "pmu0", 298 "pmu1"; 299 clocks = <&ccu CLK_USB_PHY0>, 300 <&ccu CLK_USB_PHY1>; 301 clock-names = "usb0_phy", 302 "usb1_phy"; 303 resets = <&ccu RST_USB_PHY0>, 304 <&ccu RST_USB_PHY1>; 305 reset-names = "usb0_reset", 306 "usb1_reset"; 307 status = "disabled"; 308 #phy-cells = <1>; 309 }; 310 311 ehci0: usb@1c1a000 { 312 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 313 reg = <0x01c1a000 0x100>; 314 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&ccu CLK_BUS_OHCI0>, 316 <&ccu CLK_BUS_EHCI0>, 317 <&ccu CLK_USB_OHCI0>; 318 resets = <&ccu RST_BUS_OHCI0>, 319 <&ccu RST_BUS_EHCI0>; 320 status = "disabled"; 321 }; 322 323 ohci0: usb@1c1a400 { 324 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 325 reg = <0x01c1a400 0x100>; 326 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&ccu CLK_BUS_OHCI0>, 328 <&ccu CLK_USB_OHCI0>; 329 resets = <&ccu RST_BUS_OHCI0>; 330 status = "disabled"; 331 }; 332 333 ehci1: usb@1c1b000 { 334 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 335 reg = <0x01c1b000 0x100>; 336 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&ccu CLK_BUS_OHCI1>, 338 <&ccu CLK_BUS_EHCI1>, 339 <&ccu CLK_USB_OHCI1>; 340 resets = <&ccu RST_BUS_OHCI1>, 341 <&ccu RST_BUS_EHCI1>; 342 phys = <&usbphy 1>; 343 phy-names = "usb"; 344 status = "disabled"; 345 }; 346 347 ohci1: usb@1c1b400 { 348 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 349 reg = <0x01c1b400 0x100>; 350 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&ccu CLK_BUS_OHCI1>, 352 <&ccu CLK_USB_OHCI1>; 353 resets = <&ccu RST_BUS_OHCI1>; 354 phys = <&usbphy 1>; 355 phy-names = "usb"; 356 status = "disabled"; 357 }; 358 359 ccu: clock@1c20000 { 360 compatible = "allwinner,sun50i-a64-ccu"; 361 reg = <0x01c20000 0x400>; 362 clocks = <&osc24M>, <&osc32k>; 363 clock-names = "hosc", "losc"; 364 #clock-cells = <1>; 365 #reset-cells = <1>; 366 }; 367 368 pio: pinctrl@1c20800 { 369 compatible = "allwinner,sun50i-a64-pinctrl"; 370 reg = <0x01c20800 0x400>; 371 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&ccu 58>; 375 gpio-controller; 376 #gpio-cells = <3>; 377 interrupt-controller; 378 #interrupt-cells = <3>; 379 380 i2c0_pins: i2c0_pins { 381 pins = "PH0", "PH1"; 382 function = "i2c0"; 383 }; 384 385 i2c1_pins: i2c1_pins { 386 pins = "PH2", "PH3"; 387 function = "i2c1"; 388 }; 389 390 mmc0_pins: mmc0-pins { 391 pins = "PF0", "PF1", "PF2", "PF3", 392 "PF4", "PF5"; 393 function = "mmc0"; 394 drive-strength = <30>; 395 bias-pull-up; 396 }; 397 398 mmc1_pins: mmc1-pins { 399 pins = "PG0", "PG1", "PG2", "PG3", 400 "PG4", "PG5"; 401 function = "mmc1"; 402 drive-strength = <30>; 403 bias-pull-up; 404 }; 405 406 mmc2_pins: mmc2-pins { 407 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 408 "PC10","PC11", "PC12", "PC13", 409 "PC14", "PC15", "PC16"; 410 function = "mmc2"; 411 drive-strength = <30>; 412 bias-pull-up; 413 }; 414 415 pwm_pin: pwm_pin { 416 pins = "PD22"; 417 function = "pwm"; 418 }; 419 420 rmii_pins: rmii_pins { 421 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 422 "PD18", "PD19", "PD20", "PD22", "PD23"; 423 function = "emac"; 424 drive-strength = <40>; 425 }; 426 427 rgmii_pins: rgmii_pins { 428 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 429 "PD13", "PD15", "PD16", "PD17", "PD18", 430 "PD19", "PD20", "PD21", "PD22", "PD23"; 431 function = "emac"; 432 drive-strength = <40>; 433 }; 434 435 spdif_tx_pin: spdif { 436 pins = "PH8"; 437 function = "spdif"; 438 }; 439 440 spi0_pins: spi0 { 441 pins = "PC0", "PC1", "PC2", "PC3"; 442 function = "spi0"; 443 }; 444 445 spi1_pins: spi1 { 446 pins = "PD0", "PD1", "PD2", "PD3"; 447 function = "spi1"; 448 }; 449 450 uart0_pins_a: uart0 { 451 pins = "PB8", "PB9"; 452 function = "uart0"; 453 }; 454 455 uart1_pins: uart1_pins { 456 pins = "PG6", "PG7"; 457 function = "uart1"; 458 }; 459 460 uart1_rts_cts_pins: uart1_rts_cts_pins { 461 pins = "PG8", "PG9"; 462 function = "uart1"; 463 }; 464 465 uart2_pins: uart2-pins { 466 pins = "PB0", "PB1"; 467 function = "uart2"; 468 }; 469 470 uart3_pins: uart3-pins { 471 pins = "PD0", "PD1"; 472 function = "uart3"; 473 }; 474 475 uart4_pins: uart4-pins { 476 pins = "PD2", "PD3"; 477 function = "uart4"; 478 }; 479 480 uart4_rts_cts_pins: uart4-rts-cts-pins { 481 pins = "PD4", "PD5"; 482 function = "uart4"; 483 }; 484 }; 485 486 spdif: spdif@1c21000 { 487 #sound-dai-cells = <0>; 488 compatible = "allwinner,sun50i-a64-spdif", 489 "allwinner,sun8i-h3-spdif"; 490 reg = <0x01c21000 0x400>; 491 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 493 resets = <&ccu RST_BUS_SPDIF>; 494 clock-names = "apb", "spdif"; 495 dmas = <&dma 2>; 496 dma-names = "tx"; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&spdif_tx_pin>; 499 status = "disabled"; 500 }; 501 502 i2s0: i2s@1c22000 { 503 #sound-dai-cells = <0>; 504 compatible = "allwinner,sun50i-a64-i2s", 505 "allwinner,sun8i-h3-i2s"; 506 reg = <0x01c22000 0x400>; 507 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 509 clock-names = "apb", "mod"; 510 resets = <&ccu RST_BUS_I2S0>; 511 dma-names = "rx", "tx"; 512 dmas = <&dma 3>, <&dma 3>; 513 status = "disabled"; 514 }; 515 516 i2s1: i2s@1c22400 { 517 #sound-dai-cells = <0>; 518 compatible = "allwinner,sun50i-a64-i2s", 519 "allwinner,sun8i-h3-i2s"; 520 reg = <0x01c22400 0x400>; 521 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 523 clock-names = "apb", "mod"; 524 resets = <&ccu RST_BUS_I2S1>; 525 dma-names = "rx", "tx"; 526 dmas = <&dma 4>, <&dma 4>; 527 status = "disabled"; 528 }; 529 530 uart0: serial@1c28000 { 531 compatible = "snps,dw-apb-uart"; 532 reg = <0x01c28000 0x400>; 533 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 534 reg-shift = <2>; 535 reg-io-width = <4>; 536 clocks = <&ccu CLK_BUS_UART0>; 537 resets = <&ccu RST_BUS_UART0>; 538 status = "disabled"; 539 }; 540 541 uart1: serial@1c28400 { 542 compatible = "snps,dw-apb-uart"; 543 reg = <0x01c28400 0x400>; 544 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 545 reg-shift = <2>; 546 reg-io-width = <4>; 547 clocks = <&ccu CLK_BUS_UART1>; 548 resets = <&ccu RST_BUS_UART1>; 549 status = "disabled"; 550 }; 551 552 uart2: serial@1c28800 { 553 compatible = "snps,dw-apb-uart"; 554 reg = <0x01c28800 0x400>; 555 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 556 reg-shift = <2>; 557 reg-io-width = <4>; 558 clocks = <&ccu CLK_BUS_UART2>; 559 resets = <&ccu RST_BUS_UART2>; 560 status = "disabled"; 561 }; 562 563 uart3: serial@1c28c00 { 564 compatible = "snps,dw-apb-uart"; 565 reg = <0x01c28c00 0x400>; 566 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 567 reg-shift = <2>; 568 reg-io-width = <4>; 569 clocks = <&ccu CLK_BUS_UART3>; 570 resets = <&ccu RST_BUS_UART3>; 571 status = "disabled"; 572 }; 573 574 uart4: serial@1c29000 { 575 compatible = "snps,dw-apb-uart"; 576 reg = <0x01c29000 0x400>; 577 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 578 reg-shift = <2>; 579 reg-io-width = <4>; 580 clocks = <&ccu CLK_BUS_UART4>; 581 resets = <&ccu RST_BUS_UART4>; 582 status = "disabled"; 583 }; 584 585 i2c0: i2c@1c2ac00 { 586 compatible = "allwinner,sun6i-a31-i2c"; 587 reg = <0x01c2ac00 0x400>; 588 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&ccu CLK_BUS_I2C0>; 590 resets = <&ccu RST_BUS_I2C0>; 591 status = "disabled"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 }; 595 596 i2c1: i2c@1c2b000 { 597 compatible = "allwinner,sun6i-a31-i2c"; 598 reg = <0x01c2b000 0x400>; 599 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&ccu CLK_BUS_I2C1>; 601 resets = <&ccu RST_BUS_I2C1>; 602 status = "disabled"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 }; 606 607 i2c2: i2c@1c2b400 { 608 compatible = "allwinner,sun6i-a31-i2c"; 609 reg = <0x01c2b400 0x400>; 610 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&ccu CLK_BUS_I2C2>; 612 resets = <&ccu RST_BUS_I2C2>; 613 status = "disabled"; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 }; 617 618 619 spi0: spi@1c68000 { 620 compatible = "allwinner,sun8i-h3-spi"; 621 reg = <0x01c68000 0x1000>; 622 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 624 clock-names = "ahb", "mod"; 625 dmas = <&dma 23>, <&dma 23>; 626 dma-names = "rx", "tx"; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&spi0_pins>; 629 resets = <&ccu RST_BUS_SPI0>; 630 status = "disabled"; 631 num-cs = <1>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 }; 635 636 spi1: spi@1c69000 { 637 compatible = "allwinner,sun8i-h3-spi"; 638 reg = <0x01c69000 0x1000>; 639 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 641 clock-names = "ahb", "mod"; 642 dmas = <&dma 24>, <&dma 24>; 643 dma-names = "rx", "tx"; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&spi1_pins>; 646 resets = <&ccu RST_BUS_SPI1>; 647 status = "disabled"; 648 num-cs = <1>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 }; 652 653 emac: ethernet@1c30000 { 654 compatible = "allwinner,sun50i-a64-emac"; 655 syscon = <&syscon>; 656 reg = <0x01c30000 0x10000>; 657 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 658 interrupt-names = "macirq"; 659 resets = <&ccu RST_BUS_EMAC>; 660 reset-names = "stmmaceth"; 661 clocks = <&ccu CLK_BUS_EMAC>; 662 clock-names = "stmmaceth"; 663 status = "disabled"; 664 665 mdio: mdio { 666 compatible = "snps,dwmac-mdio"; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 }; 670 }; 671 672 gic: interrupt-controller@1c81000 { 673 compatible = "arm,gic-400"; 674 reg = <0x01c81000 0x1000>, 675 <0x01c82000 0x2000>, 676 <0x01c84000 0x2000>, 677 <0x01c86000 0x2000>; 678 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 679 interrupt-controller; 680 #interrupt-cells = <3>; 681 }; 682 683 pwm: pwm@1c21400 { 684 compatible = "allwinner,sun50i-a64-pwm", 685 "allwinner,sun5i-a13-pwm"; 686 reg = <0x01c21400 0x400>; 687 clocks = <&osc24M>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pwm_pin>; 690 #pwm-cells = <3>; 691 status = "disabled"; 692 }; 693 694 rtc: rtc@1f00000 { 695 compatible = "allwinner,sun6i-a31-rtc"; 696 reg = <0x01f00000 0x54>; 697 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 699 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 700 clocks = <&osc32k>; 701 #clock-cells = <1>; 702 }; 703 704 r_intc: interrupt-controller@1f00c00 { 705 compatible = "allwinner,sun50i-a64-r-intc", 706 "allwinner,sun6i-a31-r-intc"; 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 reg = <0x01f00c00 0x400>; 710 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 711 }; 712 713 r_ccu: clock@1f01400 { 714 compatible = "allwinner,sun50i-a64-r-ccu"; 715 reg = <0x01f01400 0x100>; 716 clocks = <&osc24M>, <&osc32k>, <&iosc>, 717 <&ccu 11>; 718 clock-names = "hosc", "losc", "iosc", "pll-periph"; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 }; 722 723 r_i2c: i2c@1f02400 { 724 compatible = "allwinner,sun50i-a64-i2c", 725 "allwinner,sun6i-a31-i2c"; 726 reg = <0x01f02400 0x400>; 727 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&r_ccu CLK_APB0_I2C>; 729 resets = <&r_ccu RST_APB0_I2C>; 730 status = "disabled"; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 }; 734 735 r_pwm: pwm@1f03800 { 736 compatible = "allwinner,sun50i-a64-pwm", 737 "allwinner,sun5i-a13-pwm"; 738 reg = <0x01f03800 0x400>; 739 clocks = <&osc24M>; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&r_pwm_pin>; 742 #pwm-cells = <3>; 743 status = "disabled"; 744 }; 745 746 r_pio: pinctrl@1f02c00 { 747 compatible = "allwinner,sun50i-a64-r-pinctrl"; 748 reg = <0x01f02c00 0x400>; 749 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 751 clock-names = "apb", "hosc", "losc"; 752 gpio-controller; 753 #gpio-cells = <3>; 754 interrupt-controller; 755 #interrupt-cells = <3>; 756 757 r_i2c_pins_a: i2c-a { 758 pins = "PL8", "PL9"; 759 function = "s_i2c"; 760 }; 761 762 r_pwm_pin: pwm { 763 pins = "PL10"; 764 function = "s_pwm"; 765 }; 766 767 r_rsb_pins: rsb { 768 pins = "PL0", "PL1"; 769 function = "s_rsb"; 770 }; 771 }; 772 773 r_rsb: rsb@1f03400 { 774 compatible = "allwinner,sun8i-a23-rsb"; 775 reg = <0x01f03400 0x400>; 776 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&r_ccu 6>; 778 clock-frequency = <3000000>; 779 resets = <&r_ccu 2>; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&r_rsb_pins>; 782 status = "disabled"; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 }; 786 787 wdt0: watchdog@1c20ca0 { 788 compatible = "allwinner,sun50i-a64-wdt", 789 "allwinner,sun6i-a31-wdt"; 790 reg = <0x01c20ca0 0x20>; 791 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 792 }; 793 }; 794}; 795