1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 de2@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_DE>, 232 <&ccu CLK_BUS_DE>; 233 clock-names = "mod", 234 "bus"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <1>; 257 258 mixer0_out_tcon0: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&tcon0_in_mixer0>; 261 }; 262 263 mixer0_out_tcon1: endpoint@1 { 264 reg = <1>; 265 remote-endpoint = <&tcon1_in_mixer0>; 266 }; 267 }; 268 }; 269 }; 270 271 mixer1: mixer@200000 { 272 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273 reg = <0x200000 0x100000>; 274 clocks = <&display_clocks CLK_BUS_MIXER1>, 275 <&display_clocks CLK_MIXER1>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&display_clocks RST_MIXER1>; 279 280 ports { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 mixer1_out: port@1 { 285 reg = <1>; 286 287 mixer1_out_tcon0: endpoint@0 { 288 reg = <0>; 289 remote-endpoint = <&tcon0_in_mixer1>; 290 }; 291 292 mixer1_out_tcon1: endpoint@1 { 293 reg = <1>; 294 remote-endpoint = <&tcon1_in_mixer1>; 295 }; 296 }; 297 }; 298 }; 299 }; 300 301 syscon: syscon@1c00000 { 302 compatible = "allwinner,sun50i-a64-system-control"; 303 reg = <0x01c00000 0x1000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges; 307 308 sram_c: sram@18000 { 309 compatible = "mmio-sram"; 310 reg = <0x00018000 0x28000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0 0x00018000 0x28000>; 314 315 de2_sram: sram-section@0 { 316 compatible = "allwinner,sun50i-a64-sram-c"; 317 reg = <0x0000 0x28000>; 318 }; 319 }; 320 321 sram_c1: sram@1d00000 { 322 compatible = "mmio-sram"; 323 reg = <0x01d00000 0x40000>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges = <0 0x01d00000 0x40000>; 327 328 ve_sram: sram-section@0 { 329 compatible = "allwinner,sun50i-a64-sram-c1", 330 "allwinner,sun4i-a10-sram-c1"; 331 reg = <0x000000 0x40000>; 332 }; 333 }; 334 }; 335 336 dma: dma-controller@1c02000 { 337 compatible = "allwinner,sun50i-a64-dma"; 338 reg = <0x01c02000 0x1000>; 339 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&ccu CLK_BUS_DMA>; 341 dma-channels = <8>; 342 dma-requests = <27>; 343 resets = <&ccu RST_BUS_DMA>; 344 #dma-cells = <1>; 345 }; 346 347 tcon0: lcd-controller@1c0c000 { 348 compatible = "allwinner,sun50i-a64-tcon-lcd", 349 "allwinner,sun8i-a83t-tcon-lcd"; 350 reg = <0x01c0c000 0x1000>; 351 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 353 clock-names = "ahb", "tcon-ch0"; 354 clock-output-names = "tcon-pixel-clock"; 355 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 356 reset-names = "lcd", "lvds"; 357 358 ports { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 362 tcon0_in: port@0 { 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <0>; 366 367 tcon0_in_mixer0: endpoint@0 { 368 reg = <0>; 369 remote-endpoint = <&mixer0_out_tcon0>; 370 }; 371 372 tcon0_in_mixer1: endpoint@1 { 373 reg = <1>; 374 remote-endpoint = <&mixer1_out_tcon1>; 375 }; 376 }; 377 378 tcon0_out: port@1 { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 reg = <1>; 382 }; 383 }; 384 }; 385 386 tcon1: lcd-controller@1c0d000 { 387 compatible = "allwinner,sun50i-a64-tcon-tv", 388 "allwinner,sun8i-a83t-tcon-tv"; 389 reg = <0x01c0d000 0x1000>; 390 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 392 clock-names = "ahb", "tcon-ch1"; 393 resets = <&ccu RST_BUS_TCON1>; 394 reset-names = "lcd"; 395 396 ports { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 400 tcon1_in: port@0 { 401 #address-cells = <1>; 402 #size-cells = <0>; 403 reg = <0>; 404 405 tcon1_in_mixer0: endpoint@0 { 406 reg = <0>; 407 remote-endpoint = <&mixer0_out_tcon1>; 408 }; 409 410 tcon1_in_mixer1: endpoint@1 { 411 reg = <1>; 412 remote-endpoint = <&mixer1_out_tcon1>; 413 }; 414 }; 415 416 tcon1_out: port@1 { 417 #address-cells = <1>; 418 #size-cells = <0>; 419 reg = <1>; 420 421 tcon1_out_hdmi: endpoint@1 { 422 reg = <1>; 423 remote-endpoint = <&hdmi_in_tcon1>; 424 }; 425 }; 426 }; 427 }; 428 429 video-codec@1c0e000 { 430 compatible = "allwinner,sun50i-a64-video-engine"; 431 reg = <0x01c0e000 0x1000>; 432 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 433 <&ccu CLK_DRAM_VE>; 434 clock-names = "ahb", "mod", "ram"; 435 resets = <&ccu RST_BUS_VE>; 436 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 437 allwinner,sram = <&ve_sram 1>; 438 }; 439 440 mmc0: mmc@1c0f000 { 441 compatible = "allwinner,sun50i-a64-mmc"; 442 reg = <0x01c0f000 0x1000>; 443 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 444 clock-names = "ahb", "mmc"; 445 resets = <&ccu RST_BUS_MMC0>; 446 reset-names = "ahb"; 447 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 448 max-frequency = <150000000>; 449 status = "disabled"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 }; 453 454 mmc1: mmc@1c10000 { 455 compatible = "allwinner,sun50i-a64-mmc"; 456 reg = <0x01c10000 0x1000>; 457 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 458 clock-names = "ahb", "mmc"; 459 resets = <&ccu RST_BUS_MMC1>; 460 reset-names = "ahb"; 461 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 462 max-frequency = <150000000>; 463 status = "disabled"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 }; 467 468 mmc2: mmc@1c11000 { 469 compatible = "allwinner,sun50i-a64-emmc"; 470 reg = <0x01c11000 0x1000>; 471 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 472 clock-names = "ahb", "mmc"; 473 resets = <&ccu RST_BUS_MMC2>; 474 reset-names = "ahb"; 475 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 476 max-frequency = <200000000>; 477 status = "disabled"; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 }; 481 482 sid: eeprom@1c14000 { 483 compatible = "allwinner,sun50i-a64-sid"; 484 reg = <0x1c14000 0x400>; 485 }; 486 487 usb_otg: usb@1c19000 { 488 compatible = "allwinner,sun8i-a33-musb"; 489 reg = <0x01c19000 0x0400>; 490 clocks = <&ccu CLK_BUS_OTG>; 491 resets = <&ccu RST_BUS_OTG>; 492 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "mc"; 494 phys = <&usbphy 0>; 495 phy-names = "usb"; 496 extcon = <&usbphy 0>; 497 status = "disabled"; 498 }; 499 500 usbphy: phy@1c19400 { 501 compatible = "allwinner,sun50i-a64-usb-phy"; 502 reg = <0x01c19400 0x14>, 503 <0x01c1a800 0x4>, 504 <0x01c1b800 0x4>; 505 reg-names = "phy_ctrl", 506 "pmu0", 507 "pmu1"; 508 clocks = <&ccu CLK_USB_PHY0>, 509 <&ccu CLK_USB_PHY1>; 510 clock-names = "usb0_phy", 511 "usb1_phy"; 512 resets = <&ccu RST_USB_PHY0>, 513 <&ccu RST_USB_PHY1>; 514 reset-names = "usb0_reset", 515 "usb1_reset"; 516 status = "disabled"; 517 #phy-cells = <1>; 518 }; 519 520 ehci0: usb@1c1a000 { 521 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 522 reg = <0x01c1a000 0x100>; 523 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&ccu CLK_BUS_OHCI0>, 525 <&ccu CLK_BUS_EHCI0>, 526 <&ccu CLK_USB_OHCI0>; 527 resets = <&ccu RST_BUS_OHCI0>, 528 <&ccu RST_BUS_EHCI0>; 529 status = "disabled"; 530 }; 531 532 ohci0: usb@1c1a400 { 533 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 534 reg = <0x01c1a400 0x100>; 535 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&ccu CLK_BUS_OHCI0>, 537 <&ccu CLK_USB_OHCI0>; 538 resets = <&ccu RST_BUS_OHCI0>; 539 status = "disabled"; 540 }; 541 542 ehci1: usb@1c1b000 { 543 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 544 reg = <0x01c1b000 0x100>; 545 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&ccu CLK_BUS_OHCI1>, 547 <&ccu CLK_BUS_EHCI1>, 548 <&ccu CLK_USB_OHCI1>; 549 resets = <&ccu RST_BUS_OHCI1>, 550 <&ccu RST_BUS_EHCI1>; 551 phys = <&usbphy 1>; 552 phy-names = "usb"; 553 status = "disabled"; 554 }; 555 556 ohci1: usb@1c1b400 { 557 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 558 reg = <0x01c1b400 0x100>; 559 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&ccu CLK_BUS_OHCI1>, 561 <&ccu CLK_USB_OHCI1>; 562 resets = <&ccu RST_BUS_OHCI1>; 563 phys = <&usbphy 1>; 564 phy-names = "usb"; 565 status = "disabled"; 566 }; 567 568 ccu: clock@1c20000 { 569 compatible = "allwinner,sun50i-a64-ccu"; 570 reg = <0x01c20000 0x400>; 571 clocks = <&osc24M>, <&rtc 0>; 572 clock-names = "hosc", "losc"; 573 #clock-cells = <1>; 574 #reset-cells = <1>; 575 }; 576 577 pio: pinctrl@1c20800 { 578 compatible = "allwinner,sun50i-a64-pinctrl"; 579 reg = <0x01c20800 0x400>; 580 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&ccu 58>; 584 gpio-controller; 585 #gpio-cells = <3>; 586 interrupt-controller; 587 #interrupt-cells = <3>; 588 589 csi_pins: csi-pins { 590 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 591 "PE7", "PE8", "PE9", "PE10", "PE11"; 592 function = "csi"; 593 }; 594 595 i2c0_pins: i2c0_pins { 596 pins = "PH0", "PH1"; 597 function = "i2c0"; 598 }; 599 600 i2c1_pins: i2c1_pins { 601 pins = "PH2", "PH3"; 602 function = "i2c1"; 603 }; 604 605 mmc0_pins: mmc0-pins { 606 pins = "PF0", "PF1", "PF2", "PF3", 607 "PF4", "PF5"; 608 function = "mmc0"; 609 drive-strength = <30>; 610 bias-pull-up; 611 }; 612 613 mmc1_pins: mmc1-pins { 614 pins = "PG0", "PG1", "PG2", "PG3", 615 "PG4", "PG5"; 616 function = "mmc1"; 617 drive-strength = <30>; 618 bias-pull-up; 619 }; 620 621 mmc2_pins: mmc2-pins { 622 pins = "PC5", "PC6", "PC8", "PC9", 623 "PC10","PC11", "PC12", "PC13", 624 "PC14", "PC15", "PC16"; 625 function = "mmc2"; 626 drive-strength = <30>; 627 bias-pull-up; 628 }; 629 630 mmc2_ds_pin: mmc2-ds-pin { 631 pins = "PC1"; 632 function = "mmc2"; 633 drive-strength = <30>; 634 bias-pull-up; 635 }; 636 637 pwm_pin: pwm_pin { 638 pins = "PD22"; 639 function = "pwm"; 640 }; 641 642 rmii_pins: rmii_pins { 643 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 644 "PD18", "PD19", "PD20", "PD22", "PD23"; 645 function = "emac"; 646 drive-strength = <40>; 647 }; 648 649 rgmii_pins: rgmii_pins { 650 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 651 "PD13", "PD15", "PD16", "PD17", "PD18", 652 "PD19", "PD20", "PD21", "PD22", "PD23"; 653 function = "emac"; 654 drive-strength = <40>; 655 }; 656 657 spdif_tx_pin: spdif { 658 pins = "PH8"; 659 function = "spdif"; 660 }; 661 662 spi0_pins: spi0 { 663 pins = "PC0", "PC1", "PC2", "PC3"; 664 function = "spi0"; 665 }; 666 667 spi1_pins: spi1 { 668 pins = "PD0", "PD1", "PD2", "PD3"; 669 function = "spi1"; 670 }; 671 672 uart0_pb_pins: uart0-pb-pins { 673 pins = "PB8", "PB9"; 674 function = "uart0"; 675 }; 676 677 uart1_pins: uart1_pins { 678 pins = "PG6", "PG7"; 679 function = "uart1"; 680 }; 681 682 uart1_rts_cts_pins: uart1_rts_cts_pins { 683 pins = "PG8", "PG9"; 684 function = "uart1"; 685 }; 686 687 uart2_pins: uart2-pins { 688 pins = "PB0", "PB1"; 689 function = "uart2"; 690 }; 691 692 uart3_pins: uart3-pins { 693 pins = "PD0", "PD1"; 694 function = "uart3"; 695 }; 696 697 uart4_pins: uart4-pins { 698 pins = "PD2", "PD3"; 699 function = "uart4"; 700 }; 701 702 uart4_rts_cts_pins: uart4-rts-cts-pins { 703 pins = "PD4", "PD5"; 704 function = "uart4"; 705 }; 706 }; 707 708 spdif: spdif@1c21000 { 709 #sound-dai-cells = <0>; 710 compatible = "allwinner,sun50i-a64-spdif", 711 "allwinner,sun8i-h3-spdif"; 712 reg = <0x01c21000 0x400>; 713 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 715 resets = <&ccu RST_BUS_SPDIF>; 716 clock-names = "apb", "spdif"; 717 dmas = <&dma 2>; 718 dma-names = "tx"; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&spdif_tx_pin>; 721 status = "disabled"; 722 }; 723 724 i2s0: i2s@1c22000 { 725 #sound-dai-cells = <0>; 726 compatible = "allwinner,sun50i-a64-i2s", 727 "allwinner,sun8i-h3-i2s"; 728 reg = <0x01c22000 0x400>; 729 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 731 clock-names = "apb", "mod"; 732 resets = <&ccu RST_BUS_I2S0>; 733 dma-names = "rx", "tx"; 734 dmas = <&dma 3>, <&dma 3>; 735 status = "disabled"; 736 }; 737 738 i2s1: i2s@1c22400 { 739 #sound-dai-cells = <0>; 740 compatible = "allwinner,sun50i-a64-i2s", 741 "allwinner,sun8i-h3-i2s"; 742 reg = <0x01c22400 0x400>; 743 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 745 clock-names = "apb", "mod"; 746 resets = <&ccu RST_BUS_I2S1>; 747 dma-names = "rx", "tx"; 748 dmas = <&dma 4>, <&dma 4>; 749 status = "disabled"; 750 }; 751 752 dai: dai@1c22c00 { 753 #sound-dai-cells = <0>; 754 compatible = "allwinner,sun50i-a64-codec-i2s"; 755 reg = <0x01c22c00 0x200>; 756 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 758 clock-names = "apb", "mod"; 759 resets = <&ccu RST_BUS_CODEC>; 760 reset-names = "rst"; 761 dmas = <&dma 15>, <&dma 15>; 762 dma-names = "rx", "tx"; 763 status = "disabled"; 764 }; 765 766 codec: codec@1c22e00 { 767 #sound-dai-cells = <0>; 768 compatible = "allwinner,sun8i-a33-codec"; 769 reg = <0x01c22e00 0x600>; 770 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 772 clock-names = "bus", "mod"; 773 status = "disabled"; 774 }; 775 776 uart0: serial@1c28000 { 777 compatible = "snps,dw-apb-uart"; 778 reg = <0x01c28000 0x400>; 779 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 780 reg-shift = <2>; 781 reg-io-width = <4>; 782 clocks = <&ccu CLK_BUS_UART0>; 783 resets = <&ccu RST_BUS_UART0>; 784 status = "disabled"; 785 }; 786 787 uart1: serial@1c28400 { 788 compatible = "snps,dw-apb-uart"; 789 reg = <0x01c28400 0x400>; 790 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 791 reg-shift = <2>; 792 reg-io-width = <4>; 793 clocks = <&ccu CLK_BUS_UART1>; 794 resets = <&ccu RST_BUS_UART1>; 795 status = "disabled"; 796 }; 797 798 uart2: serial@1c28800 { 799 compatible = "snps,dw-apb-uart"; 800 reg = <0x01c28800 0x400>; 801 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 802 reg-shift = <2>; 803 reg-io-width = <4>; 804 clocks = <&ccu CLK_BUS_UART2>; 805 resets = <&ccu RST_BUS_UART2>; 806 status = "disabled"; 807 }; 808 809 uart3: serial@1c28c00 { 810 compatible = "snps,dw-apb-uart"; 811 reg = <0x01c28c00 0x400>; 812 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 813 reg-shift = <2>; 814 reg-io-width = <4>; 815 clocks = <&ccu CLK_BUS_UART3>; 816 resets = <&ccu RST_BUS_UART3>; 817 status = "disabled"; 818 }; 819 820 uart4: serial@1c29000 { 821 compatible = "snps,dw-apb-uart"; 822 reg = <0x01c29000 0x400>; 823 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 824 reg-shift = <2>; 825 reg-io-width = <4>; 826 clocks = <&ccu CLK_BUS_UART4>; 827 resets = <&ccu RST_BUS_UART4>; 828 status = "disabled"; 829 }; 830 831 i2c0: i2c@1c2ac00 { 832 compatible = "allwinner,sun6i-a31-i2c"; 833 reg = <0x01c2ac00 0x400>; 834 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&ccu CLK_BUS_I2C0>; 836 resets = <&ccu RST_BUS_I2C0>; 837 status = "disabled"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 }; 841 842 i2c1: i2c@1c2b000 { 843 compatible = "allwinner,sun6i-a31-i2c"; 844 reg = <0x01c2b000 0x400>; 845 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&ccu CLK_BUS_I2C1>; 847 resets = <&ccu RST_BUS_I2C1>; 848 status = "disabled"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 }; 852 853 i2c2: i2c@1c2b400 { 854 compatible = "allwinner,sun6i-a31-i2c"; 855 reg = <0x01c2b400 0x400>; 856 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&ccu CLK_BUS_I2C2>; 858 resets = <&ccu RST_BUS_I2C2>; 859 status = "disabled"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 }; 863 864 865 spi0: spi@1c68000 { 866 compatible = "allwinner,sun8i-h3-spi"; 867 reg = <0x01c68000 0x1000>; 868 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 870 clock-names = "ahb", "mod"; 871 dmas = <&dma 23>, <&dma 23>; 872 dma-names = "rx", "tx"; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&spi0_pins>; 875 resets = <&ccu RST_BUS_SPI0>; 876 status = "disabled"; 877 num-cs = <1>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 }; 881 882 spi1: spi@1c69000 { 883 compatible = "allwinner,sun8i-h3-spi"; 884 reg = <0x01c69000 0x1000>; 885 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 887 clock-names = "ahb", "mod"; 888 dmas = <&dma 24>, <&dma 24>; 889 dma-names = "rx", "tx"; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&spi1_pins>; 892 resets = <&ccu RST_BUS_SPI1>; 893 status = "disabled"; 894 num-cs = <1>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 }; 898 899 emac: ethernet@1c30000 { 900 compatible = "allwinner,sun50i-a64-emac"; 901 syscon = <&syscon>; 902 reg = <0x01c30000 0x10000>; 903 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "macirq"; 905 resets = <&ccu RST_BUS_EMAC>; 906 reset-names = "stmmaceth"; 907 clocks = <&ccu CLK_BUS_EMAC>; 908 clock-names = "stmmaceth"; 909 status = "disabled"; 910 911 mdio: mdio { 912 compatible = "snps,dwmac-mdio"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 }; 916 }; 917 918 mali: gpu@1c40000 { 919 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 920 reg = <0x01c40000 0x10000>; 921 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 928 interrupt-names = "gp", 929 "gpmmu", 930 "pp0", 931 "ppmmu0", 932 "pp1", 933 "ppmmu1", 934 "pmu"; 935 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 936 clock-names = "bus", "core"; 937 resets = <&ccu RST_BUS_GPU>; 938 }; 939 940 gic: interrupt-controller@1c81000 { 941 compatible = "arm,gic-400"; 942 reg = <0x01c81000 0x1000>, 943 <0x01c82000 0x2000>, 944 <0x01c84000 0x2000>, 945 <0x01c86000 0x2000>; 946 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 947 interrupt-controller; 948 #interrupt-cells = <3>; 949 }; 950 951 pwm: pwm@1c21400 { 952 compatible = "allwinner,sun50i-a64-pwm", 953 "allwinner,sun5i-a13-pwm"; 954 reg = <0x01c21400 0x400>; 955 clocks = <&osc24M>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&pwm_pin>; 958 #pwm-cells = <3>; 959 status = "disabled"; 960 }; 961 962 csi: csi@1cb0000 { 963 compatible = "allwinner,sun50i-a64-csi"; 964 reg = <0x01cb0000 0x1000>; 965 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&ccu CLK_BUS_CSI>, 967 <&ccu CLK_CSI_SCLK>, 968 <&ccu CLK_DRAM_CSI>; 969 clock-names = "bus", "mod", "ram"; 970 resets = <&ccu RST_BUS_CSI>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&csi_pins>; 973 status = "disabled"; 974 }; 975 976 hdmi: hdmi@1ee0000 { 977 compatible = "allwinner,sun50i-a64-dw-hdmi", 978 "allwinner,sun8i-a83t-dw-hdmi"; 979 reg = <0x01ee0000 0x10000>; 980 reg-io-width = <1>; 981 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 983 <&ccu CLK_HDMI>; 984 clock-names = "iahb", "isfr", "tmds"; 985 resets = <&ccu RST_BUS_HDMI1>; 986 reset-names = "ctrl"; 987 phys = <&hdmi_phy>; 988 phy-names = "hdmi-phy"; 989 status = "disabled"; 990 991 ports { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 995 hdmi_in: port@0 { 996 reg = <0>; 997 998 hdmi_in_tcon1: endpoint { 999 remote-endpoint = <&tcon1_out_hdmi>; 1000 }; 1001 }; 1002 1003 hdmi_out: port@1 { 1004 reg = <1>; 1005 }; 1006 }; 1007 }; 1008 1009 hdmi_phy: hdmi-phy@1ef0000 { 1010 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1011 reg = <0x01ef0000 0x10000>; 1012 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1013 <&ccu 7>; 1014 clock-names = "bus", "mod", "pll-0"; 1015 resets = <&ccu RST_BUS_HDMI0>; 1016 reset-names = "phy"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 rtc: rtc@1f00000 { 1021 compatible = "allwinner,sun50i-a64-rtc", 1022 "allwinner,sun8i-h3-rtc"; 1023 reg = <0x01f00000 0x400>; 1024 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1026 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1027 clocks = <&osc32k>; 1028 #clock-cells = <1>; 1029 }; 1030 1031 r_intc: interrupt-controller@1f00c00 { 1032 compatible = "allwinner,sun50i-a64-r-intc", 1033 "allwinner,sun6i-a31-r-intc"; 1034 interrupt-controller; 1035 #interrupt-cells = <2>; 1036 reg = <0x01f00c00 0x400>; 1037 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1038 }; 1039 1040 r_ccu: clock@1f01400 { 1041 compatible = "allwinner,sun50i-a64-r-ccu"; 1042 reg = <0x01f01400 0x100>; 1043 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1044 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1045 #clock-cells = <1>; 1046 #reset-cells = <1>; 1047 }; 1048 1049 codec_analog: codec-analog@1f015c0 { 1050 compatible = "allwinner,sun50i-a64-codec-analog"; 1051 reg = <0x01f015c0 0x4>; 1052 status = "disabled"; 1053 }; 1054 1055 r_i2c: i2c@1f02400 { 1056 compatible = "allwinner,sun50i-a64-i2c", 1057 "allwinner,sun6i-a31-i2c"; 1058 reg = <0x01f02400 0x400>; 1059 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&r_ccu CLK_APB0_I2C>; 1061 resets = <&r_ccu RST_APB0_I2C>; 1062 status = "disabled"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 }; 1066 1067 r_pwm: pwm@1f03800 { 1068 compatible = "allwinner,sun50i-a64-pwm", 1069 "allwinner,sun5i-a13-pwm"; 1070 reg = <0x01f03800 0x400>; 1071 clocks = <&osc24M>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&r_pwm_pin>; 1074 #pwm-cells = <3>; 1075 status = "disabled"; 1076 }; 1077 1078 r_pio: pinctrl@1f02c00 { 1079 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1080 reg = <0x01f02c00 0x400>; 1081 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1083 clock-names = "apb", "hosc", "losc"; 1084 gpio-controller; 1085 #gpio-cells = <3>; 1086 interrupt-controller; 1087 #interrupt-cells = <3>; 1088 1089 r_i2c_pl89_pins: r-i2c-pl89-pins { 1090 pins = "PL8", "PL9"; 1091 function = "s_i2c"; 1092 }; 1093 1094 r_pwm_pin: pwm { 1095 pins = "PL10"; 1096 function = "s_pwm"; 1097 }; 1098 1099 r_rsb_pins: rsb { 1100 pins = "PL0", "PL1"; 1101 function = "s_rsb"; 1102 }; 1103 }; 1104 1105 r_rsb: rsb@1f03400 { 1106 compatible = "allwinner,sun8i-a23-rsb"; 1107 reg = <0x01f03400 0x400>; 1108 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&r_ccu 6>; 1110 clock-frequency = <3000000>; 1111 resets = <&r_ccu 2>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&r_rsb_pins>; 1114 status = "disabled"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 }; 1118 1119 wdt0: watchdog@1c20ca0 { 1120 compatible = "allwinner,sun50i-a64-wdt", 1121 "allwinner,sun6i-a31-wdt"; 1122 reg = <0x01c20ca0 0x20>; 1123 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1124 }; 1125 }; 1126}; 1127