1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun50i-a64-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <3>; 83 enable-method = "psci"; 84 }; 85 }; 86 87 osc24M: osc24M_clk { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-output-names = "osc32k"; 99 }; 100 101 psci { 102 compatible = "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 110 <GIC_PPI 14 111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 112 <GIC_PPI 11 113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 114 <GIC_PPI 10 115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 mmc0: mmc@1c0f000 { 125 compatible = "allwinner,sun50i-a64-mmc"; 126 reg = <0x01c0f000 0x1000>; 127 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 128 clock-names = "ahb", "mmc"; 129 resets = <&ccu RST_BUS_MMC0>; 130 reset-names = "ahb"; 131 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 132 status = "disabled"; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 }; 136 137 mmc1: mmc@1c10000 { 138 compatible = "allwinner,sun50i-a64-mmc"; 139 reg = <0x01c10000 0x1000>; 140 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 141 clock-names = "ahb", "mmc"; 142 resets = <&ccu RST_BUS_MMC1>; 143 reset-names = "ahb"; 144 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 145 status = "disabled"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 }; 149 150 mmc2: mmc@1c11000 { 151 compatible = "allwinner,sun50i-a64-emmc"; 152 reg = <0x01c11000 0x1000>; 153 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 154 clock-names = "ahb", "mmc"; 155 resets = <&ccu RST_BUS_MMC2>; 156 reset-names = "ahb"; 157 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 158 status = "disabled"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 }; 162 163 usb_otg: usb@01c19000 { 164 compatible = "allwinner,sun8i-a33-musb"; 165 reg = <0x01c19000 0x0400>; 166 clocks = <&ccu CLK_BUS_OTG>; 167 resets = <&ccu RST_BUS_OTG>; 168 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-names = "mc"; 170 phys = <&usbphy 0>; 171 phy-names = "usb"; 172 extcon = <&usbphy 0>; 173 status = "disabled"; 174 }; 175 176 usbphy: phy@01c19400 { 177 compatible = "allwinner,sun50i-a64-usb-phy"; 178 reg = <0x01c19400 0x14>, 179 <0x01c1b800 0x4>; 180 reg-names = "phy_ctrl", 181 "pmu1"; 182 clocks = <&ccu CLK_USB_PHY0>, 183 <&ccu CLK_USB_PHY1>; 184 clock-names = "usb0_phy", 185 "usb1_phy"; 186 resets = <&ccu RST_USB_PHY0>, 187 <&ccu RST_USB_PHY1>; 188 reset-names = "usb0_reset", 189 "usb1_reset"; 190 status = "disabled"; 191 #phy-cells = <1>; 192 }; 193 194 ehci1: usb@01c1b000 { 195 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 196 reg = <0x01c1b000 0x100>; 197 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&ccu CLK_BUS_OHCI1>, 199 <&ccu CLK_BUS_EHCI1>, 200 <&ccu CLK_USB_OHCI1>; 201 resets = <&ccu RST_BUS_OHCI1>, 202 <&ccu RST_BUS_EHCI1>; 203 phys = <&usbphy 1>; 204 phy-names = "usb"; 205 status = "disabled"; 206 }; 207 208 ohci1: usb@01c1b400 { 209 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 210 reg = <0x01c1b400 0x100>; 211 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&ccu CLK_BUS_OHCI1>, 213 <&ccu CLK_USB_OHCI1>; 214 resets = <&ccu RST_BUS_OHCI1>; 215 phys = <&usbphy 1>; 216 phy-names = "usb"; 217 status = "disabled"; 218 }; 219 220 ccu: clock@01c20000 { 221 compatible = "allwinner,sun50i-a64-ccu"; 222 reg = <0x01c20000 0x400>; 223 clocks = <&osc24M>, <&osc32k>; 224 clock-names = "hosc", "losc"; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 }; 228 229 pio: pinctrl@1c20800 { 230 compatible = "allwinner,sun50i-a64-pinctrl"; 231 reg = <0x01c20800 0x400>; 232 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&ccu 58>; 236 gpio-controller; 237 #gpio-cells = <3>; 238 interrupt-controller; 239 #interrupt-cells = <3>; 240 241 i2c1_pins: i2c1_pins { 242 pins = "PH2", "PH3"; 243 function = "i2c1"; 244 }; 245 246 mmc0_pins: mmc0-pins { 247 pins = "PF0", "PF1", "PF2", "PF3", 248 "PF4", "PF5"; 249 function = "mmc0"; 250 drive-strength = <30>; 251 bias-pull-up; 252 }; 253 254 mmc1_pins: mmc1-pins { 255 pins = "PG0", "PG1", "PG2", "PG3", 256 "PG4", "PG5"; 257 function = "mmc1"; 258 drive-strength = <30>; 259 bias-pull-up; 260 }; 261 262 mmc2_pins: mmc2-pins { 263 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 264 "PC10","PC11", "PC12", "PC13", 265 "PC14", "PC15", "PC16"; 266 function = "mmc2"; 267 drive-strength = <30>; 268 bias-pull-up; 269 }; 270 271 uart0_pins_a: uart0@0 { 272 pins = "PB8", "PB9"; 273 function = "uart0"; 274 }; 275 }; 276 277 uart0: serial@1c28000 { 278 compatible = "snps,dw-apb-uart"; 279 reg = <0x01c28000 0x400>; 280 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 281 reg-shift = <2>; 282 reg-io-width = <4>; 283 clocks = <&ccu 67>; 284 resets = <&ccu 46>; 285 status = "disabled"; 286 }; 287 288 uart1: serial@1c28400 { 289 compatible = "snps,dw-apb-uart"; 290 reg = <0x01c28400 0x400>; 291 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 292 reg-shift = <2>; 293 reg-io-width = <4>; 294 clocks = <&ccu 68>; 295 resets = <&ccu 47>; 296 status = "disabled"; 297 }; 298 299 uart2: serial@1c28800 { 300 compatible = "snps,dw-apb-uart"; 301 reg = <0x01c28800 0x400>; 302 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 303 reg-shift = <2>; 304 reg-io-width = <4>; 305 clocks = <&ccu 69>; 306 resets = <&ccu 48>; 307 status = "disabled"; 308 }; 309 310 uart3: serial@1c28c00 { 311 compatible = "snps,dw-apb-uart"; 312 reg = <0x01c28c00 0x400>; 313 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 314 reg-shift = <2>; 315 reg-io-width = <4>; 316 clocks = <&ccu 70>; 317 resets = <&ccu 49>; 318 status = "disabled"; 319 }; 320 321 uart4: serial@1c29000 { 322 compatible = "snps,dw-apb-uart"; 323 reg = <0x01c29000 0x400>; 324 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 325 reg-shift = <2>; 326 reg-io-width = <4>; 327 clocks = <&ccu 71>; 328 resets = <&ccu 50>; 329 status = "disabled"; 330 }; 331 332 i2c0: i2c@1c2ac00 { 333 compatible = "allwinner,sun6i-a31-i2c"; 334 reg = <0x01c2ac00 0x400>; 335 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&ccu 63>; 337 resets = <&ccu 42>; 338 status = "disabled"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 }; 342 343 i2c1: i2c@1c2b000 { 344 compatible = "allwinner,sun6i-a31-i2c"; 345 reg = <0x01c2b000 0x400>; 346 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&ccu 64>; 348 resets = <&ccu 43>; 349 status = "disabled"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 }; 353 354 i2c2: i2c@1c2b400 { 355 compatible = "allwinner,sun6i-a31-i2c"; 356 reg = <0x01c2b400 0x400>; 357 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&ccu 65>; 359 resets = <&ccu 44>; 360 status = "disabled"; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 }; 364 365 gic: interrupt-controller@1c81000 { 366 compatible = "arm,gic-400"; 367 reg = <0x01c81000 0x1000>, 368 <0x01c82000 0x2000>, 369 <0x01c84000 0x2000>, 370 <0x01c86000 0x2000>; 371 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 372 interrupt-controller; 373 #interrupt-cells = <3>; 374 }; 375 376 rtc: rtc@1f00000 { 377 compatible = "allwinner,sun6i-a31-rtc"; 378 reg = <0x01f00000 0x54>; 379 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 }; 383}; 384