1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/sun4i-a10.h> 48#include <dt-bindings/reset/sun50i-a64-ccu.h> 49 50/ { 51 interrupt-parent = <&gic>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 device_type = "cpu"; 62 reg = <0>; 63 enable-method = "psci"; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <1>; 70 enable-method = "psci"; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53", "arm,armv8"; 75 device_type = "cpu"; 76 reg = <2>; 77 enable-method = "psci"; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <3>; 84 enable-method = "psci"; 85 }; 86 }; 87 88 osc24M: osc24M_clk { 89 #clock-cells = <0>; 90 compatible = "fixed-clock"; 91 clock-frequency = <24000000>; 92 clock-output-names = "osc24M"; 93 }; 94 95 osc32k: osc32k_clk { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <32768>; 99 clock-output-names = "osc32k"; 100 }; 101 102 psci { 103 compatible = "arm,psci-0.2"; 104 method = "smc"; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <GIC_PPI 13 110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 111 <GIC_PPI 14 112 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 11 114 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 115 <GIC_PPI 10 116 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges; 124 125 usb_otg: usb@01c19000 { 126 compatible = "allwinner,sun8i-a33-musb"; 127 reg = <0x01c19000 0x0400>; 128 clocks = <&ccu CLK_BUS_OTG>; 129 resets = <&ccu RST_BUS_OTG>; 130 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-names = "mc"; 132 phys = <&usbphy 0>; 133 phy-names = "usb"; 134 extcon = <&usbphy 0>; 135 status = "disabled"; 136 }; 137 138 usbphy: phy@01c19400 { 139 compatible = "allwinner,sun50i-a64-usb-phy"; 140 reg = <0x01c19400 0x14>, 141 <0x01c1b800 0x4>; 142 reg-names = "phy_ctrl", 143 "pmu1"; 144 clocks = <&ccu CLK_USB_PHY0>, 145 <&ccu CLK_USB_PHY1>; 146 clock-names = "usb0_phy", 147 "usb1_phy"; 148 resets = <&ccu RST_USB_PHY0>, 149 <&ccu RST_USB_PHY1>; 150 reset-names = "usb0_reset", 151 "usb1_reset"; 152 status = "disabled"; 153 #phy-cells = <1>; 154 }; 155 156 ehci1: usb@01c1b000 { 157 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 158 reg = <0x01c1b000 0x100>; 159 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&ccu CLK_BUS_OHCI1>, 161 <&ccu CLK_BUS_EHCI1>, 162 <&ccu CLK_USB_OHCI1>; 163 resets = <&ccu RST_BUS_OHCI1>, 164 <&ccu RST_BUS_EHCI1>; 165 phys = <&usbphy 1>; 166 phy-names = "usb"; 167 status = "disabled"; 168 }; 169 170 ohci1: usb@01c1b400 { 171 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 172 reg = <0x01c1b400 0x100>; 173 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&ccu CLK_BUS_OHCI1>, 175 <&ccu CLK_USB_OHCI1>; 176 resets = <&ccu RST_BUS_OHCI1>; 177 phys = <&usbphy 1>; 178 phy-names = "usb"; 179 status = "disabled"; 180 }; 181 182 ccu: clock@01c20000 { 183 compatible = "allwinner,sun50i-a64-ccu"; 184 reg = <0x01c20000 0x400>; 185 clocks = <&osc24M>, <&osc32k>; 186 clock-names = "hosc", "losc"; 187 #clock-cells = <1>; 188 #reset-cells = <1>; 189 }; 190 191 pio: pinctrl@1c20800 { 192 compatible = "allwinner,sun50i-a64-pinctrl"; 193 reg = <0x01c20800 0x400>; 194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&ccu 58>; 198 gpio-controller; 199 #gpio-cells = <3>; 200 interrupt-controller; 201 #interrupt-cells = <3>; 202 203 i2c1_pins: i2c1_pins { 204 pins = "PH2", "PH3"; 205 function = "i2c1"; 206 }; 207 208 uart0_pins_a: uart0@0 { 209 pins = "PB8", "PB9"; 210 function = "uart0"; 211 }; 212 }; 213 214 uart0: serial@1c28000 { 215 compatible = "snps,dw-apb-uart"; 216 reg = <0x01c28000 0x400>; 217 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 218 reg-shift = <2>; 219 reg-io-width = <4>; 220 clocks = <&ccu 67>; 221 resets = <&ccu 46>; 222 status = "disabled"; 223 }; 224 225 uart1: serial@1c28400 { 226 compatible = "snps,dw-apb-uart"; 227 reg = <0x01c28400 0x400>; 228 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 229 reg-shift = <2>; 230 reg-io-width = <4>; 231 clocks = <&ccu 68>; 232 resets = <&ccu 47>; 233 status = "disabled"; 234 }; 235 236 uart2: serial@1c28800 { 237 compatible = "snps,dw-apb-uart"; 238 reg = <0x01c28800 0x400>; 239 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 240 reg-shift = <2>; 241 reg-io-width = <4>; 242 clocks = <&ccu 69>; 243 resets = <&ccu 48>; 244 status = "disabled"; 245 }; 246 247 uart3: serial@1c28c00 { 248 compatible = "snps,dw-apb-uart"; 249 reg = <0x01c28c00 0x400>; 250 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 251 reg-shift = <2>; 252 reg-io-width = <4>; 253 clocks = <&ccu 70>; 254 resets = <&ccu 49>; 255 status = "disabled"; 256 }; 257 258 uart4: serial@1c29000 { 259 compatible = "snps,dw-apb-uart"; 260 reg = <0x01c29000 0x400>; 261 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clocks = <&ccu 71>; 265 resets = <&ccu 50>; 266 status = "disabled"; 267 }; 268 269 i2c0: i2c@1c2ac00 { 270 compatible = "allwinner,sun6i-a31-i2c"; 271 reg = <0x01c2ac00 0x400>; 272 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&ccu 63>; 274 resets = <&ccu 42>; 275 status = "disabled"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 }; 279 280 i2c1: i2c@1c2b000 { 281 compatible = "allwinner,sun6i-a31-i2c"; 282 reg = <0x01c2b000 0x400>; 283 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&ccu 64>; 285 resets = <&ccu 43>; 286 status = "disabled"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 }; 290 291 i2c2: i2c@1c2b400 { 292 compatible = "allwinner,sun6i-a31-i2c"; 293 reg = <0x01c2b400 0x400>; 294 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&ccu 65>; 296 resets = <&ccu 44>; 297 status = "disabled"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 }; 301 302 gic: interrupt-controller@1c81000 { 303 compatible = "arm,gic-400"; 304 reg = <0x01c81000 0x1000>, 305 <0x01c82000 0x2000>, 306 <0x01c84000 0x2000>, 307 <0x01c86000 0x2000>; 308 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 309 interrupt-controller; 310 #interrupt-cells = <3>; 311 }; 312 313 rtc: rtc@1f00000 { 314 compatible = "allwinner,sun6i-a31-rtc"; 315 reg = <0x01f00000 0x54>; 316 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 318 }; 319 }; 320}; 321