1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-de2.h>
47#include <dt-bindings/clock/sun8i-r-ccu.h>
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include <dt-bindings/reset/sun50i-a64-ccu.h>
50#include <dt-bindings/reset/sun8i-de2.h>
51#include <dt-bindings/reset/sun8i-r-ccu.h>
52
53/ {
54	interrupt-parent = <&gic>;
55	#address-cells = <1>;
56	#size-cells = <1>;
57
58	chosen {
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges;
62
63		simplefb_lcd: framebuffer-lcd {
64			compatible = "allwinner,simple-framebuffer",
65				     "simple-framebuffer";
66			allwinner,pipeline = "mixer0-lcd0";
67			clocks = <&ccu CLK_TCON0>,
68				 <&display_clocks CLK_MIXER0>;
69			status = "disabled";
70		};
71
72		simplefb_hdmi: framebuffer-hdmi {
73			compatible = "allwinner,simple-framebuffer",
74				     "simple-framebuffer";
75			allwinner,pipeline = "mixer1-lcd1-hdmi";
76			clocks = <&display_clocks CLK_MIXER1>,
77				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
78			status = "disabled";
79		};
80	};
81
82	cpus {
83		#address-cells = <1>;
84		#size-cells = <0>;
85
86		cpu0: cpu@0 {
87			compatible = "arm,cortex-a53";
88			device_type = "cpu";
89			reg = <0>;
90			enable-method = "psci";
91			next-level-cache = <&L2>;
92		};
93
94		cpu1: cpu@1 {
95			compatible = "arm,cortex-a53";
96			device_type = "cpu";
97			reg = <1>;
98			enable-method = "psci";
99			next-level-cache = <&L2>;
100		};
101
102		cpu2: cpu@2 {
103			compatible = "arm,cortex-a53";
104			device_type = "cpu";
105			reg = <2>;
106			enable-method = "psci";
107			next-level-cache = <&L2>;
108		};
109
110		cpu3: cpu@3 {
111			compatible = "arm,cortex-a53";
112			device_type = "cpu";
113			reg = <3>;
114			enable-method = "psci";
115			next-level-cache = <&L2>;
116		};
117
118		L2: l2-cache {
119			compatible = "cache";
120			cache-level = <2>;
121		};
122	};
123
124	de: display-engine {
125		compatible = "allwinner,sun50i-a64-display-engine";
126		allwinner,pipelines = <&mixer0>,
127				      <&mixer1>;
128		status = "disabled";
129	};
130
131	osc24M: osc24M_clk {
132		#clock-cells = <0>;
133		compatible = "fixed-clock";
134		clock-frequency = <24000000>;
135		clock-output-names = "osc24M";
136	};
137
138	osc32k: osc32k_clk {
139		#clock-cells = <0>;
140		compatible = "fixed-clock";
141		clock-frequency = <32768>;
142		clock-output-names = "ext-osc32k";
143	};
144
145	pmu {
146		compatible = "arm,cortex-a53-pmu";
147		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
148			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
149			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
150			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
151		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152	};
153
154	psci {
155		compatible = "arm,psci-0.2";
156		method = "smc";
157	};
158
159	sound: sound {
160		compatible = "simple-audio-card";
161		simple-audio-card,name = "sun50i-a64-audio";
162		simple-audio-card,format = "i2s";
163		simple-audio-card,frame-master = <&cpudai>;
164		simple-audio-card,bitclock-master = <&cpudai>;
165		simple-audio-card,mclk-fs = <128>;
166		simple-audio-card,aux-devs = <&codec_analog>;
167		simple-audio-card,routing =
168				"Left DAC", "AIF1 Slot 0 Left",
169				"Right DAC", "AIF1 Slot 0 Right",
170				"AIF1 Slot 0 Left ADC", "Left ADC",
171				"AIF1 Slot 0 Right ADC", "Right ADC";
172		status = "disabled";
173
174		cpudai: simple-audio-card,cpu {
175			sound-dai = <&dai>;
176		};
177
178		link_codec: simple-audio-card,codec {
179			sound-dai = <&codec>;
180		};
181	};
182
183	sound_spdif {
184		compatible = "simple-audio-card";
185		simple-audio-card,name = "On-board SPDIF";
186
187		simple-audio-card,cpu {
188			sound-dai = <&spdif>;
189		};
190
191		simple-audio-card,codec {
192			sound-dai = <&spdif_out>;
193		};
194	};
195
196	spdif_out: spdif-out {
197		#sound-dai-cells = <0>;
198		compatible = "linux,spdif-dit";
199	};
200
201	timer {
202		compatible = "arm,armv8-timer";
203		allwinner,erratum-unknown1;
204		interrupts = <GIC_PPI 13
205			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
206			     <GIC_PPI 14
207			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
208			     <GIC_PPI 11
209			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
210			     <GIC_PPI 10
211			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
212	};
213
214	soc {
215		compatible = "simple-bus";
216		#address-cells = <1>;
217		#size-cells = <1>;
218		ranges;
219
220		bus@1000000 {
221			compatible = "allwinner,sun50i-a64-de2";
222			reg = <0x1000000 0x400000>;
223			allwinner,sram = <&de2_sram 1>;
224			#address-cells = <1>;
225			#size-cells = <1>;
226			ranges = <0 0x1000000 0x400000>;
227
228			display_clocks: clock@0 {
229				compatible = "allwinner,sun50i-a64-de2-clk";
230				reg = <0x0 0x100000>;
231				clocks = <&ccu CLK_DE>,
232					 <&ccu CLK_BUS_DE>;
233				clock-names = "mod",
234					      "bus";
235				resets = <&ccu RST_BUS_DE>;
236				#clock-cells = <1>;
237				#reset-cells = <1>;
238			};
239
240			mixer0: mixer@100000 {
241				compatible = "allwinner,sun50i-a64-de2-mixer-0";
242				reg = <0x100000 0x100000>;
243				clocks = <&display_clocks CLK_BUS_MIXER0>,
244					 <&display_clocks CLK_MIXER0>;
245				clock-names = "bus",
246					      "mod";
247				resets = <&display_clocks RST_MIXER0>;
248
249				ports {
250					#address-cells = <1>;
251					#size-cells = <0>;
252
253					mixer0_out: port@1 {
254						#address-cells = <1>;
255						#size-cells = <0>;
256						reg = <1>;
257
258						mixer0_out_tcon0: endpoint@0 {
259							reg = <0>;
260							remote-endpoint = <&tcon0_in_mixer0>;
261						};
262
263						mixer0_out_tcon1: endpoint@1 {
264							reg = <1>;
265							remote-endpoint = <&tcon1_in_mixer0>;
266						};
267					};
268				};
269			};
270
271			mixer1: mixer@200000 {
272				compatible = "allwinner,sun50i-a64-de2-mixer-1";
273				reg = <0x200000 0x100000>;
274				clocks = <&display_clocks CLK_BUS_MIXER1>,
275					 <&display_clocks CLK_MIXER1>;
276				clock-names = "bus",
277					      "mod";
278				resets = <&display_clocks RST_MIXER1>;
279
280				ports {
281					#address-cells = <1>;
282					#size-cells = <0>;
283
284					mixer1_out: port@1 {
285						#address-cells = <1>;
286						#size-cells = <0>;
287						reg = <1>;
288
289						mixer1_out_tcon0: endpoint@0 {
290							reg = <0>;
291							remote-endpoint = <&tcon0_in_mixer1>;
292						};
293
294						mixer1_out_tcon1: endpoint@1 {
295							reg = <1>;
296							remote-endpoint = <&tcon1_in_mixer1>;
297						};
298					};
299				};
300			};
301		};
302
303		syscon: syscon@1c00000 {
304			compatible = "allwinner,sun50i-a64-system-control";
305			reg = <0x01c00000 0x1000>;
306			#address-cells = <1>;
307			#size-cells = <1>;
308			ranges;
309
310			sram_c: sram@18000 {
311				compatible = "mmio-sram";
312				reg = <0x00018000 0x28000>;
313				#address-cells = <1>;
314				#size-cells = <1>;
315				ranges = <0 0x00018000 0x28000>;
316
317				de2_sram: sram-section@0 {
318					compatible = "allwinner,sun50i-a64-sram-c";
319					reg = <0x0000 0x28000>;
320				};
321			};
322
323			sram_c1: sram@1d00000 {
324				compatible = "mmio-sram";
325				reg = <0x01d00000 0x40000>;
326				#address-cells = <1>;
327				#size-cells = <1>;
328				ranges = <0 0x01d00000 0x40000>;
329
330				ve_sram: sram-section@0 {
331					compatible = "allwinner,sun50i-a64-sram-c1",
332						     "allwinner,sun4i-a10-sram-c1";
333					reg = <0x000000 0x40000>;
334				};
335			};
336		};
337
338		dma: dma-controller@1c02000 {
339			compatible = "allwinner,sun50i-a64-dma";
340			reg = <0x01c02000 0x1000>;
341			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
342			clocks = <&ccu CLK_BUS_DMA>;
343			dma-channels = <8>;
344			dma-requests = <27>;
345			resets = <&ccu RST_BUS_DMA>;
346			#dma-cells = <1>;
347		};
348
349		tcon0: lcd-controller@1c0c000 {
350			compatible = "allwinner,sun50i-a64-tcon-lcd",
351				     "allwinner,sun8i-a83t-tcon-lcd";
352			reg = <0x01c0c000 0x1000>;
353			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
354			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
355			clock-names = "ahb", "tcon-ch0";
356			clock-output-names = "tcon-pixel-clock";
357			#clock-cells = <0>;
358			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
359			reset-names = "lcd", "lvds";
360
361			ports {
362				#address-cells = <1>;
363				#size-cells = <0>;
364
365				tcon0_in: port@0 {
366					#address-cells = <1>;
367					#size-cells = <0>;
368					reg = <0>;
369
370					tcon0_in_mixer0: endpoint@0 {
371						reg = <0>;
372						remote-endpoint = <&mixer0_out_tcon0>;
373					};
374
375					tcon0_in_mixer1: endpoint@1 {
376						reg = <1>;
377						remote-endpoint = <&mixer1_out_tcon0>;
378					};
379				};
380
381				tcon0_out: port@1 {
382					#address-cells = <1>;
383					#size-cells = <0>;
384					reg = <1>;
385				};
386			};
387		};
388
389		tcon1: lcd-controller@1c0d000 {
390			compatible = "allwinner,sun50i-a64-tcon-tv",
391				     "allwinner,sun8i-a83t-tcon-tv";
392			reg = <0x01c0d000 0x1000>;
393			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
394			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
395			clock-names = "ahb", "tcon-ch1";
396			resets = <&ccu RST_BUS_TCON1>;
397			reset-names = "lcd";
398
399			ports {
400				#address-cells = <1>;
401				#size-cells = <0>;
402
403				tcon1_in: port@0 {
404					#address-cells = <1>;
405					#size-cells = <0>;
406					reg = <0>;
407
408					tcon1_in_mixer0: endpoint@0 {
409						reg = <0>;
410						remote-endpoint = <&mixer0_out_tcon1>;
411					};
412
413					tcon1_in_mixer1: endpoint@1 {
414						reg = <1>;
415						remote-endpoint = <&mixer1_out_tcon1>;
416					};
417				};
418
419				tcon1_out: port@1 {
420					#address-cells = <1>;
421					#size-cells = <0>;
422					reg = <1>;
423
424					tcon1_out_hdmi: endpoint@1 {
425						reg = <1>;
426						remote-endpoint = <&hdmi_in_tcon1>;
427					};
428				};
429			};
430		};
431
432		video-codec@1c0e000 {
433			compatible = "allwinner,sun50i-a64-video-engine";
434			reg = <0x01c0e000 0x1000>;
435			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
436				 <&ccu CLK_DRAM_VE>;
437			clock-names = "ahb", "mod", "ram";
438			resets = <&ccu RST_BUS_VE>;
439			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440			allwinner,sram = <&ve_sram 1>;
441		};
442
443		mmc0: mmc@1c0f000 {
444			compatible = "allwinner,sun50i-a64-mmc";
445			reg = <0x01c0f000 0x1000>;
446			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
447			clock-names = "ahb", "mmc";
448			resets = <&ccu RST_BUS_MMC0>;
449			reset-names = "ahb";
450			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
451			max-frequency = <150000000>;
452			status = "disabled";
453			#address-cells = <1>;
454			#size-cells = <0>;
455		};
456
457		mmc1: mmc@1c10000 {
458			compatible = "allwinner,sun50i-a64-mmc";
459			reg = <0x01c10000 0x1000>;
460			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
461			clock-names = "ahb", "mmc";
462			resets = <&ccu RST_BUS_MMC1>;
463			reset-names = "ahb";
464			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
465			max-frequency = <150000000>;
466			status = "disabled";
467			#address-cells = <1>;
468			#size-cells = <0>;
469		};
470
471		mmc2: mmc@1c11000 {
472			compatible = "allwinner,sun50i-a64-emmc";
473			reg = <0x01c11000 0x1000>;
474			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
475			clock-names = "ahb", "mmc";
476			resets = <&ccu RST_BUS_MMC2>;
477			reset-names = "ahb";
478			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
479			max-frequency = <200000000>;
480			status = "disabled";
481			#address-cells = <1>;
482			#size-cells = <0>;
483		};
484
485		sid: eeprom@1c14000 {
486			compatible = "allwinner,sun50i-a64-sid";
487			reg = <0x1c14000 0x400>;
488		};
489
490		usb_otg: usb@1c19000 {
491			compatible = "allwinner,sun8i-a33-musb";
492			reg = <0x01c19000 0x0400>;
493			clocks = <&ccu CLK_BUS_OTG>;
494			resets = <&ccu RST_BUS_OTG>;
495			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
496			interrupt-names = "mc";
497			phys = <&usbphy 0>;
498			phy-names = "usb";
499			extcon = <&usbphy 0>;
500			dr_mode = "otg";
501			status = "disabled";
502		};
503
504		usbphy: phy@1c19400 {
505			compatible = "allwinner,sun50i-a64-usb-phy";
506			reg = <0x01c19400 0x14>,
507			      <0x01c1a800 0x4>,
508			      <0x01c1b800 0x4>;
509			reg-names = "phy_ctrl",
510				    "pmu0",
511				    "pmu1";
512			clocks = <&ccu CLK_USB_PHY0>,
513				 <&ccu CLK_USB_PHY1>;
514			clock-names = "usb0_phy",
515				      "usb1_phy";
516			resets = <&ccu RST_USB_PHY0>,
517				 <&ccu RST_USB_PHY1>;
518			reset-names = "usb0_reset",
519				      "usb1_reset";
520			status = "disabled";
521			#phy-cells = <1>;
522		};
523
524		ehci0: usb@1c1a000 {
525			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
526			reg = <0x01c1a000 0x100>;
527			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
528			clocks = <&ccu CLK_BUS_OHCI0>,
529				 <&ccu CLK_BUS_EHCI0>,
530				 <&ccu CLK_USB_OHCI0>;
531			resets = <&ccu RST_BUS_OHCI0>,
532				 <&ccu RST_BUS_EHCI0>;
533			status = "disabled";
534		};
535
536		ohci0: usb@1c1a400 {
537			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
538			reg = <0x01c1a400 0x100>;
539			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
540			clocks = <&ccu CLK_BUS_OHCI0>,
541				 <&ccu CLK_USB_OHCI0>;
542			resets = <&ccu RST_BUS_OHCI0>;
543			status = "disabled";
544		};
545
546		ehci1: usb@1c1b000 {
547			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
548			reg = <0x01c1b000 0x100>;
549			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
550			clocks = <&ccu CLK_BUS_OHCI1>,
551				 <&ccu CLK_BUS_EHCI1>,
552				 <&ccu CLK_USB_OHCI1>;
553			resets = <&ccu RST_BUS_OHCI1>,
554				 <&ccu RST_BUS_EHCI1>;
555			phys = <&usbphy 1>;
556			status = "disabled";
557		};
558
559		ohci1: usb@1c1b400 {
560			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
561			reg = <0x01c1b400 0x100>;
562			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
563			clocks = <&ccu CLK_BUS_OHCI1>,
564				 <&ccu CLK_USB_OHCI1>;
565			resets = <&ccu RST_BUS_OHCI1>;
566			phys = <&usbphy 1>;
567			status = "disabled";
568		};
569
570		ccu: clock@1c20000 {
571			compatible = "allwinner,sun50i-a64-ccu";
572			reg = <0x01c20000 0x400>;
573			clocks = <&osc24M>, <&rtc 0>;
574			clock-names = "hosc", "losc";
575			#clock-cells = <1>;
576			#reset-cells = <1>;
577		};
578
579		pio: pinctrl@1c20800 {
580			compatible = "allwinner,sun50i-a64-pinctrl";
581			reg = <0x01c20800 0x400>;
582			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
583				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
584				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
585			clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
586			clock-names = "apb", "hosc", "losc";
587			gpio-controller;
588			#gpio-cells = <3>;
589			interrupt-controller;
590			#interrupt-cells = <3>;
591
592			csi_pins: csi-pins {
593				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
594				       "PE7", "PE8", "PE9", "PE10", "PE11";
595				function = "csi";
596			};
597
598			/omit-if-no-ref/
599			csi_mclk_pin: csi-mclk-pin {
600				pins = "PE1";
601				function = "csi";
602			};
603
604			i2c0_pins: i2c0-pins {
605				pins = "PH0", "PH1";
606				function = "i2c0";
607			};
608
609			i2c1_pins: i2c1-pins {
610				pins = "PH2", "PH3";
611				function = "i2c1";
612			};
613
614			/omit-if-no-ref/
615			lcd_rgb666_pins: lcd-rgb666-pins {
616				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
617				       "PD5", "PD6", "PD7", "PD8", "PD9",
618				       "PD10", "PD11", "PD12", "PD13",
619				       "PD14", "PD15", "PD16", "PD17",
620				       "PD18", "PD19", "PD20", "PD21";
621				function = "lcd0";
622			};
623
624			mmc0_pins: mmc0-pins {
625				pins = "PF0", "PF1", "PF2", "PF3",
626				       "PF4", "PF5";
627				function = "mmc0";
628				drive-strength = <30>;
629				bias-pull-up;
630			};
631
632			mmc1_pins: mmc1-pins {
633				pins = "PG0", "PG1", "PG2", "PG3",
634				       "PG4", "PG5";
635				function = "mmc1";
636				drive-strength = <30>;
637				bias-pull-up;
638			};
639
640			mmc2_pins: mmc2-pins {
641				pins = "PC5", "PC6", "PC8", "PC9",
642				       "PC10","PC11", "PC12", "PC13",
643				       "PC14", "PC15", "PC16";
644				function = "mmc2";
645				drive-strength = <30>;
646				bias-pull-up;
647			};
648
649			mmc2_ds_pin: mmc2-ds-pin {
650				pins = "PC1";
651				function = "mmc2";
652				drive-strength = <30>;
653				bias-pull-up;
654			};
655
656			pwm_pin: pwm-pin {
657				pins = "PD22";
658				function = "pwm";
659			};
660
661			rmii_pins: rmii-pins {
662				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
663				       "PD18", "PD19", "PD20", "PD22", "PD23";
664				function = "emac";
665				drive-strength = <40>;
666			};
667
668			rgmii_pins: rgmii-pins {
669				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
670				       "PD13", "PD15", "PD16", "PD17", "PD18",
671				       "PD19", "PD20", "PD21", "PD22", "PD23";
672				function = "emac";
673				drive-strength = <40>;
674			};
675
676			spdif_tx_pin: spdif-tx-pin {
677				pins = "PH8";
678				function = "spdif";
679			};
680
681			spi0_pins: spi0-pins {
682				pins = "PC0", "PC1", "PC2", "PC3";
683				function = "spi0";
684			};
685
686			spi1_pins: spi1-pins {
687				pins = "PD0", "PD1", "PD2", "PD3";
688				function = "spi1";
689			};
690
691			uart0_pb_pins: uart0-pb-pins {
692				pins = "PB8", "PB9";
693				function = "uart0";
694			};
695
696			uart1_pins: uart1-pins {
697				pins = "PG6", "PG7";
698				function = "uart1";
699			};
700
701			uart1_rts_cts_pins: uart1-rts-cts-pins {
702				pins = "PG8", "PG9";
703				function = "uart1";
704			};
705
706			uart2_pins: uart2-pins {
707				pins = "PB0", "PB1";
708				function = "uart2";
709			};
710
711			uart3_pins: uart3-pins {
712				pins = "PD0", "PD1";
713				function = "uart3";
714			};
715
716			uart4_pins: uart4-pins {
717				pins = "PD2", "PD3";
718				function = "uart4";
719			};
720
721			uart4_rts_cts_pins: uart4-rts-cts-pins {
722				pins = "PD4", "PD5";
723				function = "uart4";
724			};
725		};
726
727		spdif: spdif@1c21000 {
728			#sound-dai-cells = <0>;
729			compatible = "allwinner,sun50i-a64-spdif",
730				     "allwinner,sun8i-h3-spdif";
731			reg = <0x01c21000 0x400>;
732			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
733			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
734			resets = <&ccu RST_BUS_SPDIF>;
735			clock-names = "apb", "spdif";
736			dmas = <&dma 2>;
737			dma-names = "tx";
738			pinctrl-names = "default";
739			pinctrl-0 = <&spdif_tx_pin>;
740			status = "disabled";
741		};
742
743		lradc: lradc@1c21800 {
744			compatible = "allwinner,sun50i-a64-lradc",
745				     "allwinner,sun8i-a83t-r-lradc";
746			reg = <0x01c21800 0x400>;
747			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
748			status = "disabled";
749		};
750
751		i2s0: i2s@1c22000 {
752			#sound-dai-cells = <0>;
753			compatible = "allwinner,sun50i-a64-i2s",
754				     "allwinner,sun8i-h3-i2s";
755			reg = <0x01c22000 0x400>;
756			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
757			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
758			clock-names = "apb", "mod";
759			resets = <&ccu RST_BUS_I2S0>;
760			dma-names = "rx", "tx";
761			dmas = <&dma 3>, <&dma 3>;
762			status = "disabled";
763		};
764
765		i2s1: i2s@1c22400 {
766			#sound-dai-cells = <0>;
767			compatible = "allwinner,sun50i-a64-i2s",
768				     "allwinner,sun8i-h3-i2s";
769			reg = <0x01c22400 0x400>;
770			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
771			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
772			clock-names = "apb", "mod";
773			resets = <&ccu RST_BUS_I2S1>;
774			dma-names = "rx", "tx";
775			dmas = <&dma 4>, <&dma 4>;
776			status = "disabled";
777		};
778
779		dai: dai@1c22c00 {
780			#sound-dai-cells = <0>;
781			compatible = "allwinner,sun50i-a64-codec-i2s";
782			reg = <0x01c22c00 0x200>;
783			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
784			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
785			clock-names = "apb", "mod";
786			resets = <&ccu RST_BUS_CODEC>;
787			dmas = <&dma 15>, <&dma 15>;
788			dma-names = "rx", "tx";
789			status = "disabled";
790		};
791
792		codec: codec@1c22e00 {
793			#sound-dai-cells = <0>;
794			compatible = "allwinner,sun8i-a33-codec";
795			reg = <0x01c22e00 0x600>;
796			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
797			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
798			clock-names = "bus", "mod";
799			status = "disabled";
800		};
801
802		uart0: serial@1c28000 {
803			compatible = "snps,dw-apb-uart";
804			reg = <0x01c28000 0x400>;
805			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
806			reg-shift = <2>;
807			reg-io-width = <4>;
808			clocks = <&ccu CLK_BUS_UART0>;
809			resets = <&ccu RST_BUS_UART0>;
810			status = "disabled";
811		};
812
813		uart1: serial@1c28400 {
814			compatible = "snps,dw-apb-uart";
815			reg = <0x01c28400 0x400>;
816			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
817			reg-shift = <2>;
818			reg-io-width = <4>;
819			clocks = <&ccu CLK_BUS_UART1>;
820			resets = <&ccu RST_BUS_UART1>;
821			status = "disabled";
822		};
823
824		uart2: serial@1c28800 {
825			compatible = "snps,dw-apb-uart";
826			reg = <0x01c28800 0x400>;
827			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
828			reg-shift = <2>;
829			reg-io-width = <4>;
830			clocks = <&ccu CLK_BUS_UART2>;
831			resets = <&ccu RST_BUS_UART2>;
832			status = "disabled";
833		};
834
835		uart3: serial@1c28c00 {
836			compatible = "snps,dw-apb-uart";
837			reg = <0x01c28c00 0x400>;
838			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
839			reg-shift = <2>;
840			reg-io-width = <4>;
841			clocks = <&ccu CLK_BUS_UART3>;
842			resets = <&ccu RST_BUS_UART3>;
843			status = "disabled";
844		};
845
846		uart4: serial@1c29000 {
847			compatible = "snps,dw-apb-uart";
848			reg = <0x01c29000 0x400>;
849			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
850			reg-shift = <2>;
851			reg-io-width = <4>;
852			clocks = <&ccu CLK_BUS_UART4>;
853			resets = <&ccu RST_BUS_UART4>;
854			status = "disabled";
855		};
856
857		i2c0: i2c@1c2ac00 {
858			compatible = "allwinner,sun6i-a31-i2c";
859			reg = <0x01c2ac00 0x400>;
860			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
861			clocks = <&ccu CLK_BUS_I2C0>;
862			resets = <&ccu RST_BUS_I2C0>;
863			pinctrl-names = "default";
864			pinctrl-0 = <&i2c0_pins>;
865			status = "disabled";
866			#address-cells = <1>;
867			#size-cells = <0>;
868		};
869
870		i2c1: i2c@1c2b000 {
871			compatible = "allwinner,sun6i-a31-i2c";
872			reg = <0x01c2b000 0x400>;
873			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
874			clocks = <&ccu CLK_BUS_I2C1>;
875			resets = <&ccu RST_BUS_I2C1>;
876			pinctrl-names = "default";
877			pinctrl-0 = <&i2c1_pins>;
878			status = "disabled";
879			#address-cells = <1>;
880			#size-cells = <0>;
881		};
882
883		i2c2: i2c@1c2b400 {
884			compatible = "allwinner,sun6i-a31-i2c";
885			reg = <0x01c2b400 0x400>;
886			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
887			clocks = <&ccu CLK_BUS_I2C2>;
888			resets = <&ccu RST_BUS_I2C2>;
889			status = "disabled";
890			#address-cells = <1>;
891			#size-cells = <0>;
892		};
893
894
895		spi0: spi@1c68000 {
896			compatible = "allwinner,sun8i-h3-spi";
897			reg = <0x01c68000 0x1000>;
898			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
899			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
900			clock-names = "ahb", "mod";
901			dmas = <&dma 23>, <&dma 23>;
902			dma-names = "rx", "tx";
903			pinctrl-names = "default";
904			pinctrl-0 = <&spi0_pins>;
905			resets = <&ccu RST_BUS_SPI0>;
906			status = "disabled";
907			num-cs = <1>;
908			#address-cells = <1>;
909			#size-cells = <0>;
910		};
911
912		spi1: spi@1c69000 {
913			compatible = "allwinner,sun8i-h3-spi";
914			reg = <0x01c69000 0x1000>;
915			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
916			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
917			clock-names = "ahb", "mod";
918			dmas = <&dma 24>, <&dma 24>;
919			dma-names = "rx", "tx";
920			pinctrl-names = "default";
921			pinctrl-0 = <&spi1_pins>;
922			resets = <&ccu RST_BUS_SPI1>;
923			status = "disabled";
924			num-cs = <1>;
925			#address-cells = <1>;
926			#size-cells = <0>;
927		};
928
929		emac: ethernet@1c30000 {
930			compatible = "allwinner,sun50i-a64-emac";
931			syscon = <&syscon>;
932			reg = <0x01c30000 0x10000>;
933			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
934			interrupt-names = "macirq";
935			resets = <&ccu RST_BUS_EMAC>;
936			reset-names = "stmmaceth";
937			clocks = <&ccu CLK_BUS_EMAC>;
938			clock-names = "stmmaceth";
939			status = "disabled";
940
941			mdio: mdio {
942				compatible = "snps,dwmac-mdio";
943				#address-cells = <1>;
944				#size-cells = <0>;
945			};
946		};
947
948		mali: gpu@1c40000 {
949			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
950			reg = <0x01c40000 0x10000>;
951			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
952				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
953				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
954				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
955				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
956				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
957				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
958			interrupt-names = "gp",
959					  "gpmmu",
960					  "pp0",
961					  "ppmmu0",
962					  "pp1",
963					  "ppmmu1",
964					  "pmu";
965			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
966			clock-names = "bus", "core";
967			resets = <&ccu RST_BUS_GPU>;
968		};
969
970		gic: interrupt-controller@1c81000 {
971			compatible = "arm,gic-400";
972			reg = <0x01c81000 0x1000>,
973			      <0x01c82000 0x2000>,
974			      <0x01c84000 0x2000>,
975			      <0x01c86000 0x2000>;
976			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
977			interrupt-controller;
978			#interrupt-cells = <3>;
979		};
980
981		pwm: pwm@1c21400 {
982			compatible = "allwinner,sun50i-a64-pwm",
983				     "allwinner,sun5i-a13-pwm";
984			reg = <0x01c21400 0x400>;
985			clocks = <&osc24M>;
986			pinctrl-names = "default";
987			pinctrl-0 = <&pwm_pin>;
988			#pwm-cells = <3>;
989			status = "disabled";
990		};
991
992		csi: csi@1cb0000 {
993			compatible = "allwinner,sun50i-a64-csi";
994			reg = <0x01cb0000 0x1000>;
995			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
996			clocks = <&ccu CLK_BUS_CSI>,
997				 <&ccu CLK_CSI_SCLK>,
998				 <&ccu CLK_DRAM_CSI>;
999			clock-names = "bus", "mod", "ram";
1000			resets = <&ccu RST_BUS_CSI>;
1001			pinctrl-names = "default";
1002			pinctrl-0 = <&csi_pins>;
1003			status = "disabled";
1004		};
1005
1006		hdmi: hdmi@1ee0000 {
1007			compatible = "allwinner,sun50i-a64-dw-hdmi",
1008				     "allwinner,sun8i-a83t-dw-hdmi";
1009			reg = <0x01ee0000 0x10000>;
1010			reg-io-width = <1>;
1011			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1012			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1013				 <&ccu CLK_HDMI>;
1014			clock-names = "iahb", "isfr", "tmds";
1015			resets = <&ccu RST_BUS_HDMI1>;
1016			reset-names = "ctrl";
1017			phys = <&hdmi_phy>;
1018			phy-names = "hdmi-phy";
1019			status = "disabled";
1020
1021			ports {
1022				#address-cells = <1>;
1023				#size-cells = <0>;
1024
1025				hdmi_in: port@0 {
1026					reg = <0>;
1027
1028					hdmi_in_tcon1: endpoint {
1029						remote-endpoint = <&tcon1_out_hdmi>;
1030					};
1031				};
1032
1033				hdmi_out: port@1 {
1034					reg = <1>;
1035				};
1036			};
1037		};
1038
1039		hdmi_phy: hdmi-phy@1ef0000 {
1040			compatible = "allwinner,sun50i-a64-hdmi-phy";
1041			reg = <0x01ef0000 0x10000>;
1042			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1043				 <&ccu 7>;
1044			clock-names = "bus", "mod", "pll-0";
1045			resets = <&ccu RST_BUS_HDMI0>;
1046			reset-names = "phy";
1047			#phy-cells = <0>;
1048		};
1049
1050		rtc: rtc@1f00000 {
1051			compatible = "allwinner,sun50i-a64-rtc",
1052				     "allwinner,sun8i-h3-rtc";
1053			reg = <0x01f00000 0x400>;
1054			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1055				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1056			clock-output-names = "osc32k", "osc32k-out", "iosc";
1057			clocks = <&osc32k>;
1058			#clock-cells = <1>;
1059		};
1060
1061		r_intc: interrupt-controller@1f00c00 {
1062			compatible = "allwinner,sun50i-a64-r-intc",
1063				     "allwinner,sun6i-a31-r-intc";
1064			interrupt-controller;
1065			#interrupt-cells = <2>;
1066			reg = <0x01f00c00 0x400>;
1067			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1068		};
1069
1070		r_ccu: clock@1f01400 {
1071			compatible = "allwinner,sun50i-a64-r-ccu";
1072			reg = <0x01f01400 0x100>;
1073			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>;
1074			clock-names = "hosc", "losc", "iosc", "pll-periph";
1075			#clock-cells = <1>;
1076			#reset-cells = <1>;
1077		};
1078
1079		codec_analog: codec-analog@1f015c0 {
1080			compatible = "allwinner,sun50i-a64-codec-analog";
1081			reg = <0x01f015c0 0x4>;
1082			status = "disabled";
1083		};
1084
1085		r_i2c: i2c@1f02400 {
1086			compatible = "allwinner,sun50i-a64-i2c",
1087				     "allwinner,sun6i-a31-i2c";
1088			reg = <0x01f02400 0x400>;
1089			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1090			clocks = <&r_ccu CLK_APB0_I2C>;
1091			resets = <&r_ccu RST_APB0_I2C>;
1092			status = "disabled";
1093			#address-cells = <1>;
1094			#size-cells = <0>;
1095		};
1096
1097		r_pwm: pwm@1f03800 {
1098			compatible = "allwinner,sun50i-a64-pwm",
1099				     "allwinner,sun5i-a13-pwm";
1100			reg = <0x01f03800 0x400>;
1101			clocks = <&osc24M>;
1102			pinctrl-names = "default";
1103			pinctrl-0 = <&r_pwm_pin>;
1104			#pwm-cells = <3>;
1105			status = "disabled";
1106		};
1107
1108		r_pio: pinctrl@1f02c00 {
1109			compatible = "allwinner,sun50i-a64-r-pinctrl";
1110			reg = <0x01f02c00 0x400>;
1111			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1112			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1113			clock-names = "apb", "hosc", "losc";
1114			gpio-controller;
1115			#gpio-cells = <3>;
1116			interrupt-controller;
1117			#interrupt-cells = <3>;
1118
1119			r_i2c_pl89_pins: r-i2c-pl89-pins {
1120				pins = "PL8", "PL9";
1121				function = "s_i2c";
1122			};
1123
1124			r_pwm_pin: r-pwm-pin {
1125				pins = "PL10";
1126				function = "s_pwm";
1127			};
1128
1129			r_rsb_pins: r-rsb-pins {
1130				pins = "PL0", "PL1";
1131				function = "s_rsb";
1132			};
1133		};
1134
1135		r_rsb: rsb@1f03400 {
1136			compatible = "allwinner,sun8i-a23-rsb";
1137			reg = <0x01f03400 0x400>;
1138			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1139			clocks = <&r_ccu 6>;
1140			clock-frequency = <3000000>;
1141			resets = <&r_ccu 2>;
1142			pinctrl-names = "default";
1143			pinctrl-0 = <&r_rsb_pins>;
1144			status = "disabled";
1145			#address-cells = <1>;
1146			#size-cells = <0>;
1147		};
1148
1149		wdt0: watchdog@1c20ca0 {
1150			compatible = "allwinner,sun50i-a64-wdt",
1151				     "allwinner,sun6i-a31-wdt";
1152			reg = <0x01c20ca0 0x20>;
1153			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1154		};
1155	};
1156};
1157