1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2016 ARM Ltd.
3// based on the Allwinner H3 dtsi:
4//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6#include <dt-bindings/clock/sun50i-a64-ccu.h>
7#include <dt-bindings/clock/sun8i-de2.h>
8#include <dt-bindings/clock/sun8i-r-ccu.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/sun50i-a64-ccu.h>
11#include <dt-bindings/reset/sun8i-de2.h>
12#include <dt-bindings/reset/sun8i-r-ccu.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	chosen {
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges;
24
25		simplefb_lcd: framebuffer-lcd {
26			compatible = "allwinner,simple-framebuffer",
27				     "simple-framebuffer";
28			allwinner,pipeline = "mixer0-lcd0";
29			clocks = <&ccu CLK_TCON0>,
30				 <&display_clocks CLK_MIXER0>;
31			status = "disabled";
32		};
33
34		simplefb_hdmi: framebuffer-hdmi {
35			compatible = "allwinner,simple-framebuffer",
36				     "simple-framebuffer";
37			allwinner,pipeline = "mixer1-lcd1-hdmi";
38			clocks = <&display_clocks CLK_MIXER1>,
39				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40			status = "disabled";
41		};
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		cpu0: cpu@0 {
49			compatible = "arm,cortex-a53";
50			device_type = "cpu";
51			reg = <0>;
52			enable-method = "psci";
53			next-level-cache = <&L2>;
54			clocks = <&ccu CLK_CPUX>;
55			clock-names = "cpu";
56			#cooling-cells = <2>;
57		};
58
59		cpu1: cpu@1 {
60			compatible = "arm,cortex-a53";
61			device_type = "cpu";
62			reg = <1>;
63			enable-method = "psci";
64			next-level-cache = <&L2>;
65			clocks = <&ccu CLK_CPUX>;
66			clock-names = "cpu";
67			#cooling-cells = <2>;
68		};
69
70		cpu2: cpu@2 {
71			compatible = "arm,cortex-a53";
72			device_type = "cpu";
73			reg = <2>;
74			enable-method = "psci";
75			next-level-cache = <&L2>;
76			clocks = <&ccu CLK_CPUX>;
77			clock-names = "cpu";
78			#cooling-cells = <2>;
79		};
80
81		cpu3: cpu@3 {
82			compatible = "arm,cortex-a53";
83			device_type = "cpu";
84			reg = <3>;
85			enable-method = "psci";
86			next-level-cache = <&L2>;
87			clocks = <&ccu CLK_CPUX>;
88			clock-names = "cpu";
89			#cooling-cells = <2>;
90		};
91
92		L2: l2-cache {
93			compatible = "cache";
94			cache-level = <2>;
95		};
96	};
97
98	de: display-engine {
99		compatible = "allwinner,sun50i-a64-display-engine";
100		allwinner,pipelines = <&mixer0>,
101				      <&mixer1>;
102		status = "disabled";
103	};
104
105	osc24M: osc24M_clk {
106		#clock-cells = <0>;
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "osc24M";
110	};
111
112	osc32k: osc32k_clk {
113		#clock-cells = <0>;
114		compatible = "fixed-clock";
115		clock-frequency = <32768>;
116		clock-output-names = "ext-osc32k";
117	};
118
119	pmu {
120		compatible = "arm,cortex-a53-pmu";
121		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126	};
127
128	psci {
129		compatible = "arm,psci-0.2";
130		method = "smc";
131	};
132
133	sound: sound {
134		compatible = "simple-audio-card";
135		simple-audio-card,name = "sun50i-a64-audio";
136		simple-audio-card,format = "i2s";
137		simple-audio-card,frame-master = <&cpudai>;
138		simple-audio-card,bitclock-master = <&cpudai>;
139		simple-audio-card,mclk-fs = <128>;
140		simple-audio-card,aux-devs = <&codec_analog>;
141		simple-audio-card,routing =
142				"Left DAC", "DACL",
143				"Right DAC", "DACR",
144				"ADCL", "Left ADC",
145				"ADCR", "Right ADC";
146		status = "disabled";
147
148		cpudai: simple-audio-card,cpu {
149			sound-dai = <&dai>;
150		};
151
152		link_codec: simple-audio-card,codec {
153			sound-dai = <&codec>;
154		};
155	};
156
157	timer {
158		compatible = "arm,armv8-timer";
159		allwinner,erratum-unknown1;
160		arm,no-tick-in-suspend;
161		interrupts = <GIC_PPI 13
162			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
163			     <GIC_PPI 14
164			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
165			     <GIC_PPI 11
166			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167			     <GIC_PPI 10
168			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
169	};
170
171	thermal-zones {
172		cpu_thermal: cpu0-thermal {
173			/* milliseconds */
174			polling-delay-passive = <0>;
175			polling-delay = <0>;
176			thermal-sensors = <&ths 0>;
177
178			cooling-maps {
179				map0 {
180					trip = <&cpu_alert0>;
181					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
183							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
184							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185				};
186				map1 {
187					trip = <&cpu_alert1>;
188					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
192				};
193			};
194
195			trips {
196				cpu_alert0: cpu_alert0 {
197					/* milliCelsius */
198					temperature = <75000>;
199					hysteresis = <2000>;
200					type = "passive";
201				};
202
203				cpu_alert1: cpu_alert1 {
204					/* milliCelsius */
205					temperature = <90000>;
206					hysteresis = <2000>;
207					type = "hot";
208				};
209
210				cpu_crit: cpu_crit {
211					/* milliCelsius */
212					temperature = <110000>;
213					hysteresis = <2000>;
214					type = "critical";
215				};
216			};
217		};
218
219		gpu0_thermal: gpu0-thermal {
220			/* milliseconds */
221			polling-delay-passive = <0>;
222			polling-delay = <0>;
223			thermal-sensors = <&ths 1>;
224		};
225
226		gpu1_thermal: gpu1-thermal {
227			/* milliseconds */
228			polling-delay-passive = <0>;
229			polling-delay = <0>;
230			thermal-sensors = <&ths 2>;
231		};
232	};
233
234	soc {
235		compatible = "simple-bus";
236		#address-cells = <1>;
237		#size-cells = <1>;
238		ranges;
239
240		bus@1000000 {
241			compatible = "allwinner,sun50i-a64-de2";
242			reg = <0x1000000 0x400000>;
243			allwinner,sram = <&de2_sram 1>;
244			#address-cells = <1>;
245			#size-cells = <1>;
246			ranges = <0 0x1000000 0x400000>;
247
248			display_clocks: clock@0 {
249				compatible = "allwinner,sun50i-a64-de2-clk";
250				reg = <0x0 0x10000>;
251				clocks = <&ccu CLK_BUS_DE>,
252					 <&ccu CLK_DE>;
253				clock-names = "bus",
254					      "mod";
255				resets = <&ccu RST_BUS_DE>;
256				#clock-cells = <1>;
257				#reset-cells = <1>;
258			};
259
260			rotate: rotate@20000 {
261				compatible = "allwinner,sun50i-a64-de2-rotate",
262					     "allwinner,sun8i-a83t-de2-rotate";
263				reg = <0x20000 0x10000>;
264				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
265				clocks = <&display_clocks CLK_BUS_ROT>,
266					 <&display_clocks CLK_ROT>;
267				clock-names = "bus",
268					      "mod";
269				resets = <&display_clocks RST_ROT>;
270			};
271
272			mixer0: mixer@100000 {
273				compatible = "allwinner,sun50i-a64-de2-mixer-0";
274				reg = <0x100000 0x100000>;
275				clocks = <&display_clocks CLK_BUS_MIXER0>,
276					 <&display_clocks CLK_MIXER0>;
277				clock-names = "bus",
278					      "mod";
279				resets = <&display_clocks RST_MIXER0>;
280
281				ports {
282					#address-cells = <1>;
283					#size-cells = <0>;
284
285					mixer0_out: port@1 {
286						#address-cells = <1>;
287						#size-cells = <0>;
288						reg = <1>;
289
290						mixer0_out_tcon0: endpoint@0 {
291							reg = <0>;
292							remote-endpoint = <&tcon0_in_mixer0>;
293						};
294
295						mixer0_out_tcon1: endpoint@1 {
296							reg = <1>;
297							remote-endpoint = <&tcon1_in_mixer0>;
298						};
299					};
300				};
301			};
302
303			mixer1: mixer@200000 {
304				compatible = "allwinner,sun50i-a64-de2-mixer-1";
305				reg = <0x200000 0x100000>;
306				clocks = <&display_clocks CLK_BUS_MIXER1>,
307					 <&display_clocks CLK_MIXER1>;
308				clock-names = "bus",
309					      "mod";
310				resets = <&display_clocks RST_MIXER1>;
311
312				ports {
313					#address-cells = <1>;
314					#size-cells = <0>;
315
316					mixer1_out: port@1 {
317						#address-cells = <1>;
318						#size-cells = <0>;
319						reg = <1>;
320
321						mixer1_out_tcon0: endpoint@0 {
322							reg = <0>;
323							remote-endpoint = <&tcon0_in_mixer1>;
324						};
325
326						mixer1_out_tcon1: endpoint@1 {
327							reg = <1>;
328							remote-endpoint = <&tcon1_in_mixer1>;
329						};
330					};
331				};
332			};
333		};
334
335		syscon: syscon@1c00000 {
336			compatible = "allwinner,sun50i-a64-system-control";
337			reg = <0x01c00000 0x1000>;
338			#address-cells = <1>;
339			#size-cells = <1>;
340			ranges;
341
342			sram_c: sram@18000 {
343				compatible = "mmio-sram";
344				reg = <0x00018000 0x28000>;
345				#address-cells = <1>;
346				#size-cells = <1>;
347				ranges = <0 0x00018000 0x28000>;
348
349				de2_sram: sram-section@0 {
350					compatible = "allwinner,sun50i-a64-sram-c";
351					reg = <0x0000 0x28000>;
352				};
353			};
354
355			sram_c1: sram@1d00000 {
356				compatible = "mmio-sram";
357				reg = <0x01d00000 0x40000>;
358				#address-cells = <1>;
359				#size-cells = <1>;
360				ranges = <0 0x01d00000 0x40000>;
361
362				ve_sram: sram-section@0 {
363					compatible = "allwinner,sun50i-a64-sram-c1",
364						     "allwinner,sun4i-a10-sram-c1";
365					reg = <0x000000 0x40000>;
366				};
367			};
368		};
369
370		dma: dma-controller@1c02000 {
371			compatible = "allwinner,sun50i-a64-dma";
372			reg = <0x01c02000 0x1000>;
373			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
374			clocks = <&ccu CLK_BUS_DMA>;
375			dma-channels = <8>;
376			dma-requests = <27>;
377			resets = <&ccu RST_BUS_DMA>;
378			#dma-cells = <1>;
379		};
380
381		tcon0: lcd-controller@1c0c000 {
382			compatible = "allwinner,sun50i-a64-tcon-lcd",
383				     "allwinner,sun8i-a83t-tcon-lcd";
384			reg = <0x01c0c000 0x1000>;
385			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
386			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
387			clock-names = "ahb", "tcon-ch0";
388			clock-output-names = "tcon-pixel-clock";
389			#clock-cells = <0>;
390			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
391			reset-names = "lcd", "lvds";
392
393			ports {
394				#address-cells = <1>;
395				#size-cells = <0>;
396
397				tcon0_in: port@0 {
398					#address-cells = <1>;
399					#size-cells = <0>;
400					reg = <0>;
401
402					tcon0_in_mixer0: endpoint@0 {
403						reg = <0>;
404						remote-endpoint = <&mixer0_out_tcon0>;
405					};
406
407					tcon0_in_mixer1: endpoint@1 {
408						reg = <1>;
409						remote-endpoint = <&mixer1_out_tcon0>;
410					};
411				};
412
413				tcon0_out: port@1 {
414					#address-cells = <1>;
415					#size-cells = <0>;
416					reg = <1>;
417
418					tcon0_out_dsi: endpoint@1 {
419						reg = <1>;
420						remote-endpoint = <&dsi_in_tcon0>;
421						allwinner,tcon-channel = <1>;
422					};
423				};
424			};
425		};
426
427		tcon1: lcd-controller@1c0d000 {
428			compatible = "allwinner,sun50i-a64-tcon-tv",
429				     "allwinner,sun8i-a83t-tcon-tv";
430			reg = <0x01c0d000 0x1000>;
431			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
432			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
433			clock-names = "ahb", "tcon-ch1";
434			resets = <&ccu RST_BUS_TCON1>;
435			reset-names = "lcd";
436
437			ports {
438				#address-cells = <1>;
439				#size-cells = <0>;
440
441				tcon1_in: port@0 {
442					#address-cells = <1>;
443					#size-cells = <0>;
444					reg = <0>;
445
446					tcon1_in_mixer0: endpoint@0 {
447						reg = <0>;
448						remote-endpoint = <&mixer0_out_tcon1>;
449					};
450
451					tcon1_in_mixer1: endpoint@1 {
452						reg = <1>;
453						remote-endpoint = <&mixer1_out_tcon1>;
454					};
455				};
456
457				tcon1_out: port@1 {
458					#address-cells = <1>;
459					#size-cells = <0>;
460					reg = <1>;
461
462					tcon1_out_hdmi: endpoint@1 {
463						reg = <1>;
464						remote-endpoint = <&hdmi_in_tcon1>;
465					};
466				};
467			};
468		};
469
470		video-codec@1c0e000 {
471			compatible = "allwinner,sun50i-a64-video-engine";
472			reg = <0x01c0e000 0x1000>;
473			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
474				 <&ccu CLK_DRAM_VE>;
475			clock-names = "ahb", "mod", "ram";
476			resets = <&ccu RST_BUS_VE>;
477			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
478			allwinner,sram = <&ve_sram 1>;
479		};
480
481		mmc0: mmc@1c0f000 {
482			compatible = "allwinner,sun50i-a64-mmc";
483			reg = <0x01c0f000 0x1000>;
484			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
485			clock-names = "ahb", "mmc";
486			resets = <&ccu RST_BUS_MMC0>;
487			reset-names = "ahb";
488			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
489			max-frequency = <150000000>;
490			status = "disabled";
491			#address-cells = <1>;
492			#size-cells = <0>;
493		};
494
495		mmc1: mmc@1c10000 {
496			compatible = "allwinner,sun50i-a64-mmc";
497			reg = <0x01c10000 0x1000>;
498			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
499			clock-names = "ahb", "mmc";
500			resets = <&ccu RST_BUS_MMC1>;
501			reset-names = "ahb";
502			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
503			max-frequency = <150000000>;
504			status = "disabled";
505			#address-cells = <1>;
506			#size-cells = <0>;
507		};
508
509		mmc2: mmc@1c11000 {
510			compatible = "allwinner,sun50i-a64-emmc";
511			reg = <0x01c11000 0x1000>;
512			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
513			clock-names = "ahb", "mmc";
514			resets = <&ccu RST_BUS_MMC2>;
515			reset-names = "ahb";
516			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
517			max-frequency = <150000000>;
518			status = "disabled";
519			#address-cells = <1>;
520			#size-cells = <0>;
521		};
522
523		sid: eeprom@1c14000 {
524			compatible = "allwinner,sun50i-a64-sid";
525			reg = <0x1c14000 0x400>;
526			#address-cells = <1>;
527			#size-cells = <1>;
528
529			ths_calibration: thermal-sensor-calibration@34 {
530				reg = <0x34 0x8>;
531			};
532		};
533
534		crypto: crypto@1c15000 {
535			compatible = "allwinner,sun50i-a64-crypto";
536			reg = <0x01c15000 0x1000>;
537			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
538			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
539			clock-names = "bus", "mod";
540			resets = <&ccu RST_BUS_CE>;
541		};
542
543		msgbox: mailbox@1c17000 {
544			compatible = "allwinner,sun50i-a64-msgbox",
545				     "allwinner,sun6i-a31-msgbox";
546			reg = <0x01c17000 0x1000>;
547			clocks = <&ccu CLK_BUS_MSGBOX>;
548			resets = <&ccu RST_BUS_MSGBOX>;
549			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
550			#mbox-cells = <1>;
551		};
552
553		usb_otg: usb@1c19000 {
554			compatible = "allwinner,sun8i-a33-musb";
555			reg = <0x01c19000 0x0400>;
556			clocks = <&ccu CLK_BUS_OTG>;
557			resets = <&ccu RST_BUS_OTG>;
558			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
559			interrupt-names = "mc";
560			phys = <&usbphy 0>;
561			phy-names = "usb";
562			extcon = <&usbphy 0>;
563			dr_mode = "otg";
564			status = "disabled";
565		};
566
567		usbphy: phy@1c19400 {
568			compatible = "allwinner,sun50i-a64-usb-phy";
569			reg = <0x01c19400 0x14>,
570			      <0x01c1a800 0x4>,
571			      <0x01c1b800 0x4>;
572			reg-names = "phy_ctrl",
573				    "pmu0",
574				    "pmu1";
575			clocks = <&ccu CLK_USB_PHY0>,
576				 <&ccu CLK_USB_PHY1>;
577			clock-names = "usb0_phy",
578				      "usb1_phy";
579			resets = <&ccu RST_USB_PHY0>,
580				 <&ccu RST_USB_PHY1>;
581			reset-names = "usb0_reset",
582				      "usb1_reset";
583			status = "disabled";
584			#phy-cells = <1>;
585		};
586
587		ehci0: usb@1c1a000 {
588			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
589			reg = <0x01c1a000 0x100>;
590			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
591			clocks = <&ccu CLK_BUS_OHCI0>,
592				 <&ccu CLK_BUS_EHCI0>,
593				 <&ccu CLK_USB_OHCI0>;
594			resets = <&ccu RST_BUS_OHCI0>,
595				 <&ccu RST_BUS_EHCI0>;
596			phys = <&usbphy 0>;
597			phy-names = "usb";
598			status = "disabled";
599		};
600
601		ohci0: usb@1c1a400 {
602			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
603			reg = <0x01c1a400 0x100>;
604			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
605			clocks = <&ccu CLK_BUS_OHCI0>,
606				 <&ccu CLK_USB_OHCI0>;
607			resets = <&ccu RST_BUS_OHCI0>;
608			phys = <&usbphy 0>;
609			phy-names = "usb";
610			status = "disabled";
611		};
612
613		ehci1: usb@1c1b000 {
614			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
615			reg = <0x01c1b000 0x100>;
616			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
617			clocks = <&ccu CLK_BUS_OHCI1>,
618				 <&ccu CLK_BUS_EHCI1>,
619				 <&ccu CLK_USB_OHCI1>;
620			resets = <&ccu RST_BUS_OHCI1>,
621				 <&ccu RST_BUS_EHCI1>;
622			phys = <&usbphy 1>;
623			phy-names = "usb";
624			status = "disabled";
625		};
626
627		ohci1: usb@1c1b400 {
628			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
629			reg = <0x01c1b400 0x100>;
630			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
631			clocks = <&ccu CLK_BUS_OHCI1>,
632				 <&ccu CLK_USB_OHCI1>;
633			resets = <&ccu RST_BUS_OHCI1>;
634			phys = <&usbphy 1>;
635			phy-names = "usb";
636			status = "disabled";
637		};
638
639		ccu: clock@1c20000 {
640			compatible = "allwinner,sun50i-a64-ccu";
641			reg = <0x01c20000 0x400>;
642			clocks = <&osc24M>, <&rtc 0>;
643			clock-names = "hosc", "losc";
644			#clock-cells = <1>;
645			#reset-cells = <1>;
646		};
647
648		pio: pinctrl@1c20800 {
649			compatible = "allwinner,sun50i-a64-pinctrl";
650			reg = <0x01c20800 0x400>;
651			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
652				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
653				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
654			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
655			clock-names = "apb", "hosc", "losc";
656			gpio-controller;
657			#gpio-cells = <3>;
658			interrupt-controller;
659			#interrupt-cells = <3>;
660
661			csi_pins: csi-pins {
662				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
663				       "PE7", "PE8", "PE9", "PE10", "PE11";
664				function = "csi";
665			};
666
667			/omit-if-no-ref/
668			csi_mclk_pin: csi-mclk-pin {
669				pins = "PE1";
670				function = "csi";
671			};
672
673			i2c0_pins: i2c0-pins {
674				pins = "PH0", "PH1";
675				function = "i2c0";
676			};
677
678			i2c1_pins: i2c1-pins {
679				pins = "PH2", "PH3";
680				function = "i2c1";
681			};
682
683			i2c2_pins: i2c2-pins {
684				pins = "PE14", "PE15";
685				function = "i2c2";
686			};
687
688			/omit-if-no-ref/
689			lcd_rgb666_pins: lcd-rgb666-pins {
690				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
691				       "PD5", "PD6", "PD7", "PD8", "PD9",
692				       "PD10", "PD11", "PD12", "PD13",
693				       "PD14", "PD15", "PD16", "PD17",
694				       "PD18", "PD19", "PD20", "PD21";
695				function = "lcd0";
696			};
697
698			mmc0_pins: mmc0-pins {
699				pins = "PF0", "PF1", "PF2", "PF3",
700				       "PF4", "PF5";
701				function = "mmc0";
702				drive-strength = <30>;
703				bias-pull-up;
704			};
705
706			mmc1_pins: mmc1-pins {
707				pins = "PG0", "PG1", "PG2", "PG3",
708				       "PG4", "PG5";
709				function = "mmc1";
710				drive-strength = <30>;
711				bias-pull-up;
712			};
713
714			mmc2_pins: mmc2-pins {
715				pins = "PC5", "PC6", "PC8", "PC9",
716				       "PC10","PC11", "PC12", "PC13",
717				       "PC14", "PC15", "PC16";
718				function = "mmc2";
719				drive-strength = <30>;
720				bias-pull-up;
721			};
722
723			mmc2_ds_pin: mmc2-ds-pin {
724				pins = "PC1";
725				function = "mmc2";
726				drive-strength = <30>;
727				bias-pull-up;
728			};
729
730			pwm_pin: pwm-pin {
731				pins = "PD22";
732				function = "pwm";
733			};
734
735			rmii_pins: rmii-pins {
736				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
737				       "PD18", "PD19", "PD20", "PD22", "PD23";
738				function = "emac";
739				drive-strength = <40>;
740			};
741
742			rgmii_pins: rgmii-pins {
743				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
744				       "PD13", "PD15", "PD16", "PD17", "PD18",
745				       "PD19", "PD20", "PD21", "PD22", "PD23";
746				function = "emac";
747				drive-strength = <40>;
748			};
749
750			spdif_tx_pin: spdif-tx-pin {
751				pins = "PH8";
752				function = "spdif";
753			};
754
755			spi0_pins: spi0-pins {
756				pins = "PC0", "PC1", "PC2", "PC3";
757				function = "spi0";
758			};
759
760			spi1_pins: spi1-pins {
761				pins = "PD0", "PD1", "PD2", "PD3";
762				function = "spi1";
763			};
764
765			uart0_pb_pins: uart0-pb-pins {
766				pins = "PB8", "PB9";
767				function = "uart0";
768			};
769
770			uart1_pins: uart1-pins {
771				pins = "PG6", "PG7";
772				function = "uart1";
773			};
774
775			uart1_rts_cts_pins: uart1-rts-cts-pins {
776				pins = "PG8", "PG9";
777				function = "uart1";
778			};
779
780			uart2_pins: uart2-pins {
781				pins = "PB0", "PB1";
782				function = "uart2";
783			};
784
785			uart3_pins: uart3-pins {
786				pins = "PD0", "PD1";
787				function = "uart3";
788			};
789
790			uart4_pins: uart4-pins {
791				pins = "PD2", "PD3";
792				function = "uart4";
793			};
794
795			uart4_rts_cts_pins: uart4-rts-cts-pins {
796				pins = "PD4", "PD5";
797				function = "uart4";
798			};
799		};
800
801		spdif: spdif@1c21000 {
802			#sound-dai-cells = <0>;
803			compatible = "allwinner,sun50i-a64-spdif",
804				     "allwinner,sun8i-h3-spdif";
805			reg = <0x01c21000 0x400>;
806			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
807			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
808			resets = <&ccu RST_BUS_SPDIF>;
809			clock-names = "apb", "spdif";
810			dmas = <&dma 2>;
811			dma-names = "tx";
812			pinctrl-names = "default";
813			pinctrl-0 = <&spdif_tx_pin>;
814			status = "disabled";
815		};
816
817		lradc: lradc@1c21800 {
818			compatible = "allwinner,sun50i-a64-lradc",
819				     "allwinner,sun8i-a83t-r-lradc";
820			reg = <0x01c21800 0x400>;
821			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
822			status = "disabled";
823		};
824
825		i2s0: i2s@1c22000 {
826			#sound-dai-cells = <0>;
827			compatible = "allwinner,sun50i-a64-i2s",
828				     "allwinner,sun8i-h3-i2s";
829			reg = <0x01c22000 0x400>;
830			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
831			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
832			clock-names = "apb", "mod";
833			resets = <&ccu RST_BUS_I2S0>;
834			dma-names = "rx", "tx";
835			dmas = <&dma 3>, <&dma 3>;
836			status = "disabled";
837		};
838
839		i2s1: i2s@1c22400 {
840			#sound-dai-cells = <0>;
841			compatible = "allwinner,sun50i-a64-i2s",
842				     "allwinner,sun8i-h3-i2s";
843			reg = <0x01c22400 0x400>;
844			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
845			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
846			clock-names = "apb", "mod";
847			resets = <&ccu RST_BUS_I2S1>;
848			dma-names = "rx", "tx";
849			dmas = <&dma 4>, <&dma 4>;
850			status = "disabled";
851		};
852
853		dai: dai@1c22c00 {
854			#sound-dai-cells = <0>;
855			compatible = "allwinner,sun50i-a64-codec-i2s";
856			reg = <0x01c22c00 0x200>;
857			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
858			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
859			clock-names = "apb", "mod";
860			resets = <&ccu RST_BUS_CODEC>;
861			dmas = <&dma 15>, <&dma 15>;
862			dma-names = "rx", "tx";
863			status = "disabled";
864		};
865
866		codec: codec@1c22e00 {
867			#sound-dai-cells = <0>;
868			compatible = "allwinner,sun50i-a64-codec",
869				     "allwinner,sun8i-a33-codec";
870			reg = <0x01c22e00 0x600>;
871			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
872			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
873			clock-names = "bus", "mod";
874			status = "disabled";
875		};
876
877		ths: thermal-sensor@1c25000 {
878			compatible = "allwinner,sun50i-a64-ths";
879			reg = <0x01c25000 0x100>;
880			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
881			clock-names = "bus", "mod";
882			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
883			resets = <&ccu RST_BUS_THS>;
884			nvmem-cells = <&ths_calibration>;
885			nvmem-cell-names = "calibration";
886			#thermal-sensor-cells = <1>;
887		};
888
889		uart0: serial@1c28000 {
890			compatible = "snps,dw-apb-uart";
891			reg = <0x01c28000 0x400>;
892			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
893			reg-shift = <2>;
894			reg-io-width = <4>;
895			clocks = <&ccu CLK_BUS_UART0>;
896			resets = <&ccu RST_BUS_UART0>;
897			status = "disabled";
898		};
899
900		uart1: serial@1c28400 {
901			compatible = "snps,dw-apb-uart";
902			reg = <0x01c28400 0x400>;
903			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
904			reg-shift = <2>;
905			reg-io-width = <4>;
906			clocks = <&ccu CLK_BUS_UART1>;
907			resets = <&ccu RST_BUS_UART1>;
908			status = "disabled";
909		};
910
911		uart2: serial@1c28800 {
912			compatible = "snps,dw-apb-uart";
913			reg = <0x01c28800 0x400>;
914			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
915			reg-shift = <2>;
916			reg-io-width = <4>;
917			clocks = <&ccu CLK_BUS_UART2>;
918			resets = <&ccu RST_BUS_UART2>;
919			status = "disabled";
920		};
921
922		uart3: serial@1c28c00 {
923			compatible = "snps,dw-apb-uart";
924			reg = <0x01c28c00 0x400>;
925			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
926			reg-shift = <2>;
927			reg-io-width = <4>;
928			clocks = <&ccu CLK_BUS_UART3>;
929			resets = <&ccu RST_BUS_UART3>;
930			status = "disabled";
931		};
932
933		uart4: serial@1c29000 {
934			compatible = "snps,dw-apb-uart";
935			reg = <0x01c29000 0x400>;
936			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
937			reg-shift = <2>;
938			reg-io-width = <4>;
939			clocks = <&ccu CLK_BUS_UART4>;
940			resets = <&ccu RST_BUS_UART4>;
941			status = "disabled";
942		};
943
944		i2c0: i2c@1c2ac00 {
945			compatible = "allwinner,sun6i-a31-i2c";
946			reg = <0x01c2ac00 0x400>;
947			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
948			clocks = <&ccu CLK_BUS_I2C0>;
949			resets = <&ccu RST_BUS_I2C0>;
950			pinctrl-names = "default";
951			pinctrl-0 = <&i2c0_pins>;
952			status = "disabled";
953			#address-cells = <1>;
954			#size-cells = <0>;
955		};
956
957		i2c1: i2c@1c2b000 {
958			compatible = "allwinner,sun6i-a31-i2c";
959			reg = <0x01c2b000 0x400>;
960			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
961			clocks = <&ccu CLK_BUS_I2C1>;
962			resets = <&ccu RST_BUS_I2C1>;
963			pinctrl-names = "default";
964			pinctrl-0 = <&i2c1_pins>;
965			status = "disabled";
966			#address-cells = <1>;
967			#size-cells = <0>;
968		};
969
970		i2c2: i2c@1c2b400 {
971			compatible = "allwinner,sun6i-a31-i2c";
972			reg = <0x01c2b400 0x400>;
973			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
974			clocks = <&ccu CLK_BUS_I2C2>;
975			resets = <&ccu RST_BUS_I2C2>;
976			pinctrl-names = "default";
977			pinctrl-0 = <&i2c2_pins>;
978			status = "disabled";
979			#address-cells = <1>;
980			#size-cells = <0>;
981		};
982
983		spi0: spi@1c68000 {
984			compatible = "allwinner,sun8i-h3-spi";
985			reg = <0x01c68000 0x1000>;
986			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
987			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
988			clock-names = "ahb", "mod";
989			dmas = <&dma 23>, <&dma 23>;
990			dma-names = "rx", "tx";
991			pinctrl-names = "default";
992			pinctrl-0 = <&spi0_pins>;
993			resets = <&ccu RST_BUS_SPI0>;
994			status = "disabled";
995			num-cs = <1>;
996			#address-cells = <1>;
997			#size-cells = <0>;
998		};
999
1000		spi1: spi@1c69000 {
1001			compatible = "allwinner,sun8i-h3-spi";
1002			reg = <0x01c69000 0x1000>;
1003			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1004			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1005			clock-names = "ahb", "mod";
1006			dmas = <&dma 24>, <&dma 24>;
1007			dma-names = "rx", "tx";
1008			pinctrl-names = "default";
1009			pinctrl-0 = <&spi1_pins>;
1010			resets = <&ccu RST_BUS_SPI1>;
1011			status = "disabled";
1012			num-cs = <1>;
1013			#address-cells = <1>;
1014			#size-cells = <0>;
1015		};
1016
1017		emac: ethernet@1c30000 {
1018			compatible = "allwinner,sun50i-a64-emac";
1019			syscon = <&syscon>;
1020			reg = <0x01c30000 0x10000>;
1021			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1022			interrupt-names = "macirq";
1023			resets = <&ccu RST_BUS_EMAC>;
1024			reset-names = "stmmaceth";
1025			clocks = <&ccu CLK_BUS_EMAC>;
1026			clock-names = "stmmaceth";
1027			status = "disabled";
1028
1029			mdio: mdio {
1030				compatible = "snps,dwmac-mdio";
1031				#address-cells = <1>;
1032				#size-cells = <0>;
1033			};
1034		};
1035
1036		mali: gpu@1c40000 {
1037			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1038			reg = <0x01c40000 0x10000>;
1039			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1040				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1041				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1042				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1043				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1044				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1045				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1046			interrupt-names = "gp",
1047					  "gpmmu",
1048					  "pp0",
1049					  "ppmmu0",
1050					  "pp1",
1051					  "ppmmu1",
1052					  "pmu";
1053			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1054			clock-names = "bus", "core";
1055			resets = <&ccu RST_BUS_GPU>;
1056		};
1057
1058		gic: interrupt-controller@1c81000 {
1059			compatible = "arm,gic-400";
1060			reg = <0x01c81000 0x1000>,
1061			      <0x01c82000 0x2000>,
1062			      <0x01c84000 0x2000>,
1063			      <0x01c86000 0x2000>;
1064			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1065			interrupt-controller;
1066			#interrupt-cells = <3>;
1067		};
1068
1069		pwm: pwm@1c21400 {
1070			compatible = "allwinner,sun50i-a64-pwm",
1071				     "allwinner,sun5i-a13-pwm";
1072			reg = <0x01c21400 0x400>;
1073			clocks = <&osc24M>;
1074			pinctrl-names = "default";
1075			pinctrl-0 = <&pwm_pin>;
1076			#pwm-cells = <3>;
1077			status = "disabled";
1078		};
1079
1080		mbus: dram-controller@1c62000 {
1081			compatible = "allwinner,sun50i-a64-mbus";
1082			reg = <0x01c62000 0x1000>;
1083			clocks = <&ccu 112>;
1084			#address-cells = <1>;
1085			#size-cells = <1>;
1086			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1087			#interconnect-cells = <1>;
1088		};
1089
1090		csi: csi@1cb0000 {
1091			compatible = "allwinner,sun50i-a64-csi";
1092			reg = <0x01cb0000 0x1000>;
1093			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1094			clocks = <&ccu CLK_BUS_CSI>,
1095				 <&ccu CLK_CSI_SCLK>,
1096				 <&ccu CLK_DRAM_CSI>;
1097			clock-names = "bus", "mod", "ram";
1098			resets = <&ccu RST_BUS_CSI>;
1099			pinctrl-names = "default";
1100			pinctrl-0 = <&csi_pins>;
1101			status = "disabled";
1102		};
1103
1104		dsi: dsi@1ca0000 {
1105			compatible = "allwinner,sun50i-a64-mipi-dsi";
1106			reg = <0x01ca0000 0x1000>;
1107			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1108			clocks = <&ccu CLK_BUS_MIPI_DSI>;
1109			resets = <&ccu RST_BUS_MIPI_DSI>;
1110			phys = <&dphy>;
1111			phy-names = "dphy";
1112			status = "disabled";
1113			#address-cells = <1>;
1114			#size-cells = <0>;
1115
1116			port {
1117				dsi_in_tcon0: endpoint {
1118					remote-endpoint = <&tcon0_out_dsi>;
1119				};
1120			};
1121		};
1122
1123		dphy: d-phy@1ca1000 {
1124			compatible = "allwinner,sun50i-a64-mipi-dphy",
1125				     "allwinner,sun6i-a31-mipi-dphy";
1126			reg = <0x01ca1000 0x1000>;
1127			clocks = <&ccu CLK_BUS_MIPI_DSI>,
1128				 <&ccu CLK_DSI_DPHY>;
1129			clock-names = "bus", "mod";
1130			resets = <&ccu RST_BUS_MIPI_DSI>;
1131			status = "disabled";
1132			#phy-cells = <0>;
1133		};
1134
1135		deinterlace: deinterlace@1e00000 {
1136			compatible = "allwinner,sun50i-a64-deinterlace",
1137				     "allwinner,sun8i-h3-deinterlace";
1138			reg = <0x01e00000 0x20000>;
1139			clocks = <&ccu CLK_BUS_DEINTERLACE>,
1140				 <&ccu CLK_DEINTERLACE>,
1141				 <&ccu CLK_DRAM_DEINTERLACE>;
1142			clock-names = "bus", "mod", "ram";
1143			resets = <&ccu RST_BUS_DEINTERLACE>;
1144			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1145			interconnects = <&mbus 9>;
1146			interconnect-names = "dma-mem";
1147		};
1148
1149		hdmi: hdmi@1ee0000 {
1150			compatible = "allwinner,sun50i-a64-dw-hdmi",
1151				     "allwinner,sun8i-a83t-dw-hdmi";
1152			reg = <0x01ee0000 0x10000>;
1153			reg-io-width = <1>;
1154			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1155			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1156				 <&ccu CLK_HDMI>;
1157			clock-names = "iahb", "isfr", "tmds";
1158			resets = <&ccu RST_BUS_HDMI1>;
1159			reset-names = "ctrl";
1160			phys = <&hdmi_phy>;
1161			phy-names = "phy";
1162			status = "disabled";
1163
1164			ports {
1165				#address-cells = <1>;
1166				#size-cells = <0>;
1167
1168				hdmi_in: port@0 {
1169					reg = <0>;
1170
1171					hdmi_in_tcon1: endpoint {
1172						remote-endpoint = <&tcon1_out_hdmi>;
1173					};
1174				};
1175
1176				hdmi_out: port@1 {
1177					reg = <1>;
1178				};
1179			};
1180		};
1181
1182		hdmi_phy: hdmi-phy@1ef0000 {
1183			compatible = "allwinner,sun50i-a64-hdmi-phy";
1184			reg = <0x01ef0000 0x10000>;
1185			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1186				 <&ccu CLK_PLL_VIDEO0>;
1187			clock-names = "bus", "mod", "pll-0";
1188			resets = <&ccu RST_BUS_HDMI0>;
1189			reset-names = "phy";
1190			#phy-cells = <0>;
1191		};
1192
1193		rtc: rtc@1f00000 {
1194			compatible = "allwinner,sun50i-a64-rtc",
1195				     "allwinner,sun8i-h3-rtc";
1196			reg = <0x01f00000 0x400>;
1197			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1198				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1199			clock-output-names = "osc32k", "osc32k-out", "iosc";
1200			clocks = <&osc32k>;
1201			#clock-cells = <1>;
1202		};
1203
1204		r_intc: interrupt-controller@1f00c00 {
1205			compatible = "allwinner,sun50i-a64-r-intc",
1206				     "allwinner,sun6i-a31-r-intc";
1207			interrupt-controller;
1208			#interrupt-cells = <2>;
1209			reg = <0x01f00c00 0x400>;
1210			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1211		};
1212
1213		r_ccu: clock@1f01400 {
1214			compatible = "allwinner,sun50i-a64-r-ccu";
1215			reg = <0x01f01400 0x100>;
1216			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1217				 <&ccu CLK_PLL_PERIPH0>;
1218			clock-names = "hosc", "losc", "iosc", "pll-periph";
1219			#clock-cells = <1>;
1220			#reset-cells = <1>;
1221		};
1222
1223		codec_analog: codec-analog@1f015c0 {
1224			compatible = "allwinner,sun50i-a64-codec-analog";
1225			reg = <0x01f015c0 0x4>;
1226			status = "disabled";
1227		};
1228
1229		r_i2c: i2c@1f02400 {
1230			compatible = "allwinner,sun50i-a64-i2c",
1231				     "allwinner,sun6i-a31-i2c";
1232			reg = <0x01f02400 0x400>;
1233			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1234			clocks = <&r_ccu CLK_APB0_I2C>;
1235			resets = <&r_ccu RST_APB0_I2C>;
1236			status = "disabled";
1237			#address-cells = <1>;
1238			#size-cells = <0>;
1239		};
1240
1241		r_ir: ir@1f02000 {
1242			compatible = "allwinner,sun50i-a64-ir",
1243				     "allwinner,sun6i-a31-ir";
1244			reg = <0x01f02000 0x400>;
1245			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1246			clock-names = "apb", "ir";
1247			resets = <&r_ccu RST_APB0_IR>;
1248			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1249			pinctrl-names = "default";
1250			pinctrl-0 = <&r_ir_rx_pin>;
1251			status = "disabled";
1252		};
1253
1254		r_pwm: pwm@1f03800 {
1255			compatible = "allwinner,sun50i-a64-pwm",
1256				     "allwinner,sun5i-a13-pwm";
1257			reg = <0x01f03800 0x400>;
1258			clocks = <&osc24M>;
1259			pinctrl-names = "default";
1260			pinctrl-0 = <&r_pwm_pin>;
1261			#pwm-cells = <3>;
1262			status = "disabled";
1263		};
1264
1265		r_pio: pinctrl@1f02c00 {
1266			compatible = "allwinner,sun50i-a64-r-pinctrl";
1267			reg = <0x01f02c00 0x400>;
1268			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1269			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1270			clock-names = "apb", "hosc", "losc";
1271			gpio-controller;
1272			#gpio-cells = <3>;
1273			interrupt-controller;
1274			#interrupt-cells = <3>;
1275
1276			r_i2c_pl89_pins: r-i2c-pl89-pins {
1277				pins = "PL8", "PL9";
1278				function = "s_i2c";
1279			};
1280
1281			r_ir_rx_pin: r-ir-rx-pin {
1282				pins = "PL11";
1283				function = "s_cir_rx";
1284			};
1285
1286			r_pwm_pin: r-pwm-pin {
1287				pins = "PL10";
1288				function = "s_pwm";
1289			};
1290
1291			r_rsb_pins: r-rsb-pins {
1292				pins = "PL0", "PL1";
1293				function = "s_rsb";
1294			};
1295		};
1296
1297		r_rsb: rsb@1f03400 {
1298			compatible = "allwinner,sun8i-a23-rsb";
1299			reg = <0x01f03400 0x400>;
1300			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1301			clocks = <&r_ccu 6>;
1302			clock-frequency = <3000000>;
1303			resets = <&r_ccu 2>;
1304			pinctrl-names = "default";
1305			pinctrl-0 = <&r_rsb_pins>;
1306			status = "disabled";
1307			#address-cells = <1>;
1308			#size-cells = <0>;
1309		};
1310
1311		wdt0: watchdog@1c20ca0 {
1312			compatible = "allwinner,sun50i-a64-wdt",
1313				     "allwinner,sun6i-a31-wdt";
1314			reg = <0x01c20ca0 0x20>;
1315			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1316			clocks = <&osc24M>;
1317		};
1318	};
1319};
1320