1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun50i-a64-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <3>; 83 enable-method = "psci"; 84 }; 85 }; 86 87 osc24M: osc24M_clk { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-output-names = "osc32k"; 99 }; 100 101 iosc: internal-osc-clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 clock-frequency = <16000000>; 105 clock-accuracy = <300000000>; 106 clock-output-names = "iosc"; 107 }; 108 109 psci { 110 compatible = "arm,psci-0.2"; 111 method = "smc"; 112 }; 113 114 timer { 115 compatible = "arm,armv8-timer"; 116 interrupts = <GIC_PPI 13 117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 118 <GIC_PPI 14 119 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 120 <GIC_PPI 11 121 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 122 <GIC_PPI 10 123 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 mmc0: mmc@1c0f000 { 133 compatible = "allwinner,sun50i-a64-mmc"; 134 reg = <0x01c0f000 0x1000>; 135 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 136 clock-names = "ahb", "mmc"; 137 resets = <&ccu RST_BUS_MMC0>; 138 reset-names = "ahb"; 139 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 140 max-frequency = <150000000>; 141 status = "disabled"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 }; 145 146 mmc1: mmc@1c10000 { 147 compatible = "allwinner,sun50i-a64-mmc"; 148 reg = <0x01c10000 0x1000>; 149 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 150 clock-names = "ahb", "mmc"; 151 resets = <&ccu RST_BUS_MMC1>; 152 reset-names = "ahb"; 153 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 154 max-frequency = <150000000>; 155 status = "disabled"; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 }; 159 160 mmc2: mmc@1c11000 { 161 compatible = "allwinner,sun50i-a64-emmc"; 162 reg = <0x01c11000 0x1000>; 163 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 164 clock-names = "ahb", "mmc"; 165 resets = <&ccu RST_BUS_MMC2>; 166 reset-names = "ahb"; 167 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 168 max-frequency = <200000000>; 169 status = "disabled"; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 }; 173 174 usb_otg: usb@01c19000 { 175 compatible = "allwinner,sun8i-a33-musb"; 176 reg = <0x01c19000 0x0400>; 177 clocks = <&ccu CLK_BUS_OTG>; 178 resets = <&ccu RST_BUS_OTG>; 179 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "mc"; 181 phys = <&usbphy 0>; 182 phy-names = "usb"; 183 extcon = <&usbphy 0>; 184 status = "disabled"; 185 }; 186 187 usbphy: phy@01c19400 { 188 compatible = "allwinner,sun50i-a64-usb-phy"; 189 reg = <0x01c19400 0x14>, 190 <0x01c1b800 0x4>; 191 reg-names = "phy_ctrl", 192 "pmu1"; 193 clocks = <&ccu CLK_USB_PHY0>, 194 <&ccu CLK_USB_PHY1>; 195 clock-names = "usb0_phy", 196 "usb1_phy"; 197 resets = <&ccu RST_USB_PHY0>, 198 <&ccu RST_USB_PHY1>; 199 reset-names = "usb0_reset", 200 "usb1_reset"; 201 status = "disabled"; 202 #phy-cells = <1>; 203 }; 204 205 ehci1: usb@01c1b000 { 206 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 207 reg = <0x01c1b000 0x100>; 208 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&ccu CLK_BUS_OHCI1>, 210 <&ccu CLK_BUS_EHCI1>, 211 <&ccu CLK_USB_OHCI1>; 212 resets = <&ccu RST_BUS_OHCI1>, 213 <&ccu RST_BUS_EHCI1>; 214 phys = <&usbphy 1>; 215 phy-names = "usb"; 216 status = "disabled"; 217 }; 218 219 ohci1: usb@01c1b400 { 220 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 221 reg = <0x01c1b400 0x100>; 222 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&ccu CLK_BUS_OHCI1>, 224 <&ccu CLK_USB_OHCI1>; 225 resets = <&ccu RST_BUS_OHCI1>; 226 phys = <&usbphy 1>; 227 phy-names = "usb"; 228 status = "disabled"; 229 }; 230 231 ccu: clock@01c20000 { 232 compatible = "allwinner,sun50i-a64-ccu"; 233 reg = <0x01c20000 0x400>; 234 clocks = <&osc24M>, <&osc32k>; 235 clock-names = "hosc", "losc"; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 pio: pinctrl@1c20800 { 241 compatible = "allwinner,sun50i-a64-pinctrl"; 242 reg = <0x01c20800 0x400>; 243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&ccu 58>; 247 gpio-controller; 248 #gpio-cells = <3>; 249 interrupt-controller; 250 #interrupt-cells = <3>; 251 252 i2c1_pins: i2c1_pins { 253 pins = "PH2", "PH3"; 254 function = "i2c1"; 255 }; 256 257 mmc0_pins: mmc0-pins { 258 pins = "PF0", "PF1", "PF2", "PF3", 259 "PF4", "PF5"; 260 function = "mmc0"; 261 drive-strength = <30>; 262 bias-pull-up; 263 }; 264 265 mmc1_pins: mmc1-pins { 266 pins = "PG0", "PG1", "PG2", "PG3", 267 "PG4", "PG5"; 268 function = "mmc1"; 269 drive-strength = <30>; 270 bias-pull-up; 271 }; 272 273 mmc2_pins: mmc2-pins { 274 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 275 "PC10","PC11", "PC12", "PC13", 276 "PC14", "PC15", "PC16"; 277 function = "mmc2"; 278 drive-strength = <30>; 279 bias-pull-up; 280 }; 281 282 uart0_pins_a: uart0@0 { 283 pins = "PB8", "PB9"; 284 function = "uart0"; 285 }; 286 287 uart1_pins: uart1_pins { 288 pins = "PG6", "PG7"; 289 function = "uart1"; 290 }; 291 292 uart1_rts_cts_pins: uart1_rts_cts_pins { 293 pins = "PG8", "PG9"; 294 function = "uart1"; 295 }; 296 }; 297 298 uart0: serial@1c28000 { 299 compatible = "snps,dw-apb-uart"; 300 reg = <0x01c28000 0x400>; 301 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 302 reg-shift = <2>; 303 reg-io-width = <4>; 304 clocks = <&ccu 67>; 305 resets = <&ccu 46>; 306 status = "disabled"; 307 }; 308 309 uart1: serial@1c28400 { 310 compatible = "snps,dw-apb-uart"; 311 reg = <0x01c28400 0x400>; 312 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 313 reg-shift = <2>; 314 reg-io-width = <4>; 315 clocks = <&ccu 68>; 316 resets = <&ccu 47>; 317 status = "disabled"; 318 }; 319 320 uart2: serial@1c28800 { 321 compatible = "snps,dw-apb-uart"; 322 reg = <0x01c28800 0x400>; 323 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 324 reg-shift = <2>; 325 reg-io-width = <4>; 326 clocks = <&ccu 69>; 327 resets = <&ccu 48>; 328 status = "disabled"; 329 }; 330 331 uart3: serial@1c28c00 { 332 compatible = "snps,dw-apb-uart"; 333 reg = <0x01c28c00 0x400>; 334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 clocks = <&ccu 70>; 338 resets = <&ccu 49>; 339 status = "disabled"; 340 }; 341 342 uart4: serial@1c29000 { 343 compatible = "snps,dw-apb-uart"; 344 reg = <0x01c29000 0x400>; 345 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 346 reg-shift = <2>; 347 reg-io-width = <4>; 348 clocks = <&ccu 71>; 349 resets = <&ccu 50>; 350 status = "disabled"; 351 }; 352 353 i2c0: i2c@1c2ac00 { 354 compatible = "allwinner,sun6i-a31-i2c"; 355 reg = <0x01c2ac00 0x400>; 356 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&ccu 63>; 358 resets = <&ccu 42>; 359 status = "disabled"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 364 i2c1: i2c@1c2b000 { 365 compatible = "allwinner,sun6i-a31-i2c"; 366 reg = <0x01c2b000 0x400>; 367 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&ccu 64>; 369 resets = <&ccu 43>; 370 status = "disabled"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 }; 374 375 i2c2: i2c@1c2b400 { 376 compatible = "allwinner,sun6i-a31-i2c"; 377 reg = <0x01c2b400 0x400>; 378 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&ccu 65>; 380 resets = <&ccu 44>; 381 status = "disabled"; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 }; 385 386 gic: interrupt-controller@1c81000 { 387 compatible = "arm,gic-400"; 388 reg = <0x01c81000 0x1000>, 389 <0x01c82000 0x2000>, 390 <0x01c84000 0x2000>, 391 <0x01c86000 0x2000>; 392 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 393 interrupt-controller; 394 #interrupt-cells = <3>; 395 }; 396 397 rtc: rtc@1f00000 { 398 compatible = "allwinner,sun6i-a31-rtc"; 399 reg = <0x01f00000 0x54>; 400 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 402 }; 403 404 r_ccu: clock@1f01400 { 405 compatible = "allwinner,sun50i-a64-r-ccu"; 406 reg = <0x01f01400 0x100>; 407 clocks = <&osc24M>, <&osc32k>, <&iosc>; 408 clock-names = "hosc", "losc", "iosc"; 409 #clock-cells = <1>; 410 #reset-cells = <1>; 411 }; 412 }; 413}; 414