1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/sun4i-a10.h> 48#include <dt-bindings/reset/sun50i-a64-ccu.h> 49 50/ { 51 interrupt-parent = <&gic>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 device_type = "cpu"; 62 reg = <0>; 63 enable-method = "psci"; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <1>; 70 enable-method = "psci"; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53", "arm,armv8"; 75 device_type = "cpu"; 76 reg = <2>; 77 enable-method = "psci"; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <3>; 84 enable-method = "psci"; 85 }; 86 }; 87 88 osc24M: osc24M_clk { 89 #clock-cells = <0>; 90 compatible = "fixed-clock"; 91 clock-frequency = <24000000>; 92 clock-output-names = "osc24M"; 93 }; 94 95 osc32k: osc32k_clk { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <32768>; 99 clock-output-names = "osc32k"; 100 }; 101 102 psci { 103 compatible = "arm,psci-0.2"; 104 method = "smc"; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <GIC_PPI 13 110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 111 <GIC_PPI 14 112 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 11 114 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 115 <GIC_PPI 10 116 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges; 124 125 ccu: clock@01c20000 { 126 compatible = "allwinner,sun50i-a64-ccu"; 127 reg = <0x01c20000 0x400>; 128 clocks = <&osc24M>, <&osc32k>; 129 clock-names = "hosc", "losc"; 130 #clock-cells = <1>; 131 #reset-cells = <1>; 132 }; 133 134 pio: pinctrl@1c20800 { 135 compatible = "allwinner,sun50i-a64-pinctrl"; 136 reg = <0x01c20800 0x400>; 137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&ccu CLK_BUS_PIO>; 141 gpio-controller; 142 #gpio-cells = <3>; 143 interrupt-controller; 144 #interrupt-cells = <3>; 145 146 i2c1_pins: i2c1_pins { 147 pins = "PH2", "PH3"; 148 function = "i2c1"; 149 }; 150 151 uart0_pins_a: uart0@0 { 152 pins = "PB8", "PB9"; 153 function = "uart0"; 154 }; 155 }; 156 157 uart0: serial@1c28000 { 158 compatible = "snps,dw-apb-uart"; 159 reg = <0x01c28000 0x400>; 160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 161 reg-shift = <2>; 162 reg-io-width = <4>; 163 clocks = <&ccu CLK_BUS_UART0>; 164 resets = <&ccu RST_BUS_UART0>; 165 status = "disabled"; 166 }; 167 168 uart1: serial@1c28400 { 169 compatible = "snps,dw-apb-uart"; 170 reg = <0x01c28400 0x400>; 171 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 172 reg-shift = <2>; 173 reg-io-width = <4>; 174 clocks = <&ccu CLK_BUS_UART1>; 175 resets = <&ccu RST_BUS_UART1>; 176 status = "disabled"; 177 }; 178 179 uart2: serial@1c28800 { 180 compatible = "snps,dw-apb-uart"; 181 reg = <0x01c28800 0x400>; 182 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 183 reg-shift = <2>; 184 reg-io-width = <4>; 185 clocks = <&ccu CLK_BUS_UART2>; 186 resets = <&ccu RST_BUS_UART2>; 187 status = "disabled"; 188 }; 189 190 uart3: serial@1c28c00 { 191 compatible = "snps,dw-apb-uart"; 192 reg = <0x01c28c00 0x400>; 193 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 194 reg-shift = <2>; 195 reg-io-width = <4>; 196 clocks = <&ccu CLK_BUS_UART3>; 197 resets = <&ccu RST_BUS_UART3>; 198 status = "disabled"; 199 }; 200 201 uart4: serial@1c29000 { 202 compatible = "snps,dw-apb-uart"; 203 reg = <0x01c29000 0x400>; 204 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 205 reg-shift = <2>; 206 reg-io-width = <4>; 207 clocks = <&ccu CLK_BUS_UART4>; 208 resets = <&ccu RST_BUS_UART4>; 209 status = "disabled"; 210 }; 211 212 i2c0: i2c@1c2ac00 { 213 compatible = "allwinner,sun6i-a31-i2c"; 214 reg = <0x01c2ac00 0x400>; 215 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&ccu CLK_BUS_I2C0>; 217 resets = <&ccu RST_BUS_I2C0>; 218 status = "disabled"; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 }; 222 223 i2c1: i2c@1c2b000 { 224 compatible = "allwinner,sun6i-a31-i2c"; 225 reg = <0x01c2b000 0x400>; 226 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&ccu CLK_BUS_I2C1>; 228 resets = <&ccu RST_BUS_I2C1>; 229 status = "disabled"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 }; 233 234 i2c2: i2c@1c2b400 { 235 compatible = "allwinner,sun6i-a31-i2c"; 236 reg = <0x01c2b400 0x400>; 237 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&ccu CLK_BUS_I2C2>; 239 resets = <&ccu RST_BUS_I2C2>; 240 status = "disabled"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 }; 244 245 gic: interrupt-controller@1c81000 { 246 compatible = "arm,gic-400"; 247 reg = <0x01c81000 0x1000>, 248 <0x01c82000 0x2000>, 249 <0x01c84000 0x2000>, 250 <0x01c86000 0x2000>; 251 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 252 interrupt-controller; 253 #interrupt-cells = <3>; 254 }; 255 256 rtc: rtc@1f00000 { 257 compatible = "allwinner,sun6i-a31-rtc"; 258 reg = <0x01f00000 0x54>; 259 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 261 }; 262 }; 263}; 264