1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-r-ccu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/sun50i-a64-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/reset/sun8i-r-ccu.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 chosen { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 simplefb_lcd: framebuffer-lcd { 26 compatible = "allwinner,simple-framebuffer", 27 "simple-framebuffer"; 28 allwinner,pipeline = "mixer0-lcd0"; 29 clocks = <&ccu CLK_TCON0>, 30 <&display_clocks CLK_MIXER0>; 31 status = "disabled"; 32 }; 33 34 simplefb_hdmi: framebuffer-hdmi { 35 compatible = "allwinner,simple-framebuffer", 36 "simple-framebuffer"; 37 allwinner,pipeline = "mixer1-lcd1-hdmi"; 38 clocks = <&display_clocks CLK_MIXER1>, 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40 status = "disabled"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 reg = <0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2>; 54 }; 55 56 cpu1: cpu@1 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 reg = <1>; 60 enable-method = "psci"; 61 next-level-cache = <&L2>; 62 }; 63 64 cpu2: cpu@2 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 reg = <2>; 68 enable-method = "psci"; 69 next-level-cache = <&L2>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 reg = <3>; 76 enable-method = "psci"; 77 next-level-cache = <&L2>; 78 }; 79 80 L2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 }; 84 }; 85 86 de: display-engine { 87 compatible = "allwinner,sun50i-a64-display-engine"; 88 allwinner,pipelines = <&mixer0>, 89 <&mixer1>; 90 status = "disabled"; 91 }; 92 93 osc24M: osc24M_clk { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <24000000>; 97 clock-output-names = "osc24M"; 98 }; 99 100 osc32k: osc32k_clk { 101 #clock-cells = <0>; 102 compatible = "fixed-clock"; 103 clock-frequency = <32768>; 104 clock-output-names = "ext-osc32k"; 105 }; 106 107 pmu { 108 compatible = "arm,cortex-a53-pmu"; 109 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 113 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 114 }; 115 116 psci { 117 compatible = "arm,psci-0.2"; 118 method = "smc"; 119 }; 120 121 sound: sound { 122 compatible = "simple-audio-card"; 123 simple-audio-card,name = "sun50i-a64-audio"; 124 simple-audio-card,format = "i2s"; 125 simple-audio-card,frame-master = <&cpudai>; 126 simple-audio-card,bitclock-master = <&cpudai>; 127 simple-audio-card,mclk-fs = <128>; 128 simple-audio-card,aux-devs = <&codec_analog>; 129 simple-audio-card,routing = 130 "Left DAC", "AIF1 Slot 0 Left", 131 "Right DAC", "AIF1 Slot 0 Right", 132 "AIF1 Slot 0 Left ADC", "Left ADC", 133 "AIF1 Slot 0 Right ADC", "Right ADC"; 134 status = "disabled"; 135 136 cpudai: simple-audio-card,cpu { 137 sound-dai = <&dai>; 138 }; 139 140 link_codec: simple-audio-card,codec { 141 sound-dai = <&codec>; 142 }; 143 }; 144 145 sound_spdif { 146 compatible = "simple-audio-card"; 147 simple-audio-card,name = "On-board SPDIF"; 148 149 simple-audio-card,cpu { 150 sound-dai = <&spdif>; 151 }; 152 153 simple-audio-card,codec { 154 sound-dai = <&spdif_out>; 155 }; 156 }; 157 158 spdif_out: spdif-out { 159 #sound-dai-cells = <0>; 160 compatible = "linux,spdif-dit"; 161 }; 162 163 timer { 164 compatible = "arm,armv8-timer"; 165 allwinner,erratum-unknown1; 166 interrupts = <GIC_PPI 13 167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 168 <GIC_PPI 14 169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 170 <GIC_PPI 11 171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 172 <GIC_PPI 10 173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 174 }; 175 176 thermal-zones { 177 cpu_thermal: cpu0-thermal { 178 /* milliseconds */ 179 polling-delay-passive = <0>; 180 polling-delay = <0>; 181 thermal-sensors = <&ths 0>; 182 }; 183 184 gpu0_thermal: gpu0-thermal { 185 /* milliseconds */ 186 polling-delay-passive = <0>; 187 polling-delay = <0>; 188 thermal-sensors = <&ths 1>; 189 }; 190 191 gpu1_thermal: gpu1-thermal { 192 /* milliseconds */ 193 polling-delay-passive = <0>; 194 polling-delay = <0>; 195 thermal-sensors = <&ths 2>; 196 }; 197 }; 198 199 soc { 200 compatible = "simple-bus"; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges; 204 205 bus@1000000 { 206 compatible = "allwinner,sun50i-a64-de2"; 207 reg = <0x1000000 0x400000>; 208 allwinner,sram = <&de2_sram 1>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0 0x1000000 0x400000>; 212 213 display_clocks: clock@0 { 214 compatible = "allwinner,sun50i-a64-de2-clk"; 215 reg = <0x0 0x100000>; 216 clocks = <&ccu CLK_BUS_DE>, 217 <&ccu CLK_DE>; 218 clock-names = "bus", 219 "mod"; 220 resets = <&ccu RST_BUS_DE>; 221 #clock-cells = <1>; 222 #reset-cells = <1>; 223 }; 224 225 mixer0: mixer@100000 { 226 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 227 reg = <0x100000 0x100000>; 228 clocks = <&display_clocks CLK_BUS_MIXER0>, 229 <&display_clocks CLK_MIXER0>; 230 clock-names = "bus", 231 "mod"; 232 resets = <&display_clocks RST_MIXER0>; 233 234 ports { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 mixer0_out: port@1 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <1>; 242 243 mixer0_out_tcon0: endpoint@0 { 244 reg = <0>; 245 remote-endpoint = <&tcon0_in_mixer0>; 246 }; 247 248 mixer0_out_tcon1: endpoint@1 { 249 reg = <1>; 250 remote-endpoint = <&tcon1_in_mixer0>; 251 }; 252 }; 253 }; 254 }; 255 256 mixer1: mixer@200000 { 257 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 258 reg = <0x200000 0x100000>; 259 clocks = <&display_clocks CLK_BUS_MIXER1>, 260 <&display_clocks CLK_MIXER1>; 261 clock-names = "bus", 262 "mod"; 263 resets = <&display_clocks RST_MIXER1>; 264 265 ports { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 mixer1_out: port@1 { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 reg = <1>; 273 274 mixer1_out_tcon0: endpoint@0 { 275 reg = <0>; 276 remote-endpoint = <&tcon0_in_mixer1>; 277 }; 278 279 mixer1_out_tcon1: endpoint@1 { 280 reg = <1>; 281 remote-endpoint = <&tcon1_in_mixer1>; 282 }; 283 }; 284 }; 285 }; 286 }; 287 288 syscon: syscon@1c00000 { 289 compatible = "allwinner,sun50i-a64-system-control"; 290 reg = <0x01c00000 0x1000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges; 294 295 sram_c: sram@18000 { 296 compatible = "mmio-sram"; 297 reg = <0x00018000 0x28000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges = <0 0x00018000 0x28000>; 301 302 de2_sram: sram-section@0 { 303 compatible = "allwinner,sun50i-a64-sram-c"; 304 reg = <0x0000 0x28000>; 305 }; 306 }; 307 308 sram_c1: sram@1d00000 { 309 compatible = "mmio-sram"; 310 reg = <0x01d00000 0x40000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0 0x01d00000 0x40000>; 314 315 ve_sram: sram-section@0 { 316 compatible = "allwinner,sun50i-a64-sram-c1", 317 "allwinner,sun4i-a10-sram-c1"; 318 reg = <0x000000 0x40000>; 319 }; 320 }; 321 }; 322 323 dma: dma-controller@1c02000 { 324 compatible = "allwinner,sun50i-a64-dma"; 325 reg = <0x01c02000 0x1000>; 326 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&ccu CLK_BUS_DMA>; 328 dma-channels = <8>; 329 dma-requests = <27>; 330 resets = <&ccu RST_BUS_DMA>; 331 #dma-cells = <1>; 332 }; 333 334 tcon0: lcd-controller@1c0c000 { 335 compatible = "allwinner,sun50i-a64-tcon-lcd", 336 "allwinner,sun8i-a83t-tcon-lcd"; 337 reg = <0x01c0c000 0x1000>; 338 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 340 clock-names = "ahb", "tcon-ch0"; 341 clock-output-names = "tcon-pixel-clock"; 342 #clock-cells = <0>; 343 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 344 reset-names = "lcd", "lvds"; 345 346 ports { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 tcon0_in: port@0 { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <0>; 354 355 tcon0_in_mixer0: endpoint@0 { 356 reg = <0>; 357 remote-endpoint = <&mixer0_out_tcon0>; 358 }; 359 360 tcon0_in_mixer1: endpoint@1 { 361 reg = <1>; 362 remote-endpoint = <&mixer1_out_tcon0>; 363 }; 364 }; 365 366 tcon0_out: port@1 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <1>; 370 }; 371 }; 372 }; 373 374 tcon1: lcd-controller@1c0d000 { 375 compatible = "allwinner,sun50i-a64-tcon-tv", 376 "allwinner,sun8i-a83t-tcon-tv"; 377 reg = <0x01c0d000 0x1000>; 378 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 380 clock-names = "ahb", "tcon-ch1"; 381 resets = <&ccu RST_BUS_TCON1>; 382 reset-names = "lcd"; 383 384 ports { 385 #address-cells = <1>; 386 #size-cells = <0>; 387 388 tcon1_in: port@0 { 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0>; 392 393 tcon1_in_mixer0: endpoint@0 { 394 reg = <0>; 395 remote-endpoint = <&mixer0_out_tcon1>; 396 }; 397 398 tcon1_in_mixer1: endpoint@1 { 399 reg = <1>; 400 remote-endpoint = <&mixer1_out_tcon1>; 401 }; 402 }; 403 404 tcon1_out: port@1 { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 reg = <1>; 408 409 tcon1_out_hdmi: endpoint@1 { 410 reg = <1>; 411 remote-endpoint = <&hdmi_in_tcon1>; 412 }; 413 }; 414 }; 415 }; 416 417 video-codec@1c0e000 { 418 compatible = "allwinner,sun50i-a64-video-engine"; 419 reg = <0x01c0e000 0x1000>; 420 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 421 <&ccu CLK_DRAM_VE>; 422 clock-names = "ahb", "mod", "ram"; 423 resets = <&ccu RST_BUS_VE>; 424 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 425 allwinner,sram = <&ve_sram 1>; 426 }; 427 428 mmc0: mmc@1c0f000 { 429 compatible = "allwinner,sun50i-a64-mmc"; 430 reg = <0x01c0f000 0x1000>; 431 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 432 clock-names = "ahb", "mmc"; 433 resets = <&ccu RST_BUS_MMC0>; 434 reset-names = "ahb"; 435 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 436 max-frequency = <150000000>; 437 status = "disabled"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 442 mmc1: mmc@1c10000 { 443 compatible = "allwinner,sun50i-a64-mmc"; 444 reg = <0x01c10000 0x1000>; 445 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 446 clock-names = "ahb", "mmc"; 447 resets = <&ccu RST_BUS_MMC1>; 448 reset-names = "ahb"; 449 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 450 max-frequency = <150000000>; 451 status = "disabled"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 }; 455 456 mmc2: mmc@1c11000 { 457 compatible = "allwinner,sun50i-a64-emmc"; 458 reg = <0x01c11000 0x1000>; 459 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 460 clock-names = "ahb", "mmc"; 461 resets = <&ccu RST_BUS_MMC2>; 462 reset-names = "ahb"; 463 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 464 max-frequency = <200000000>; 465 status = "disabled"; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 }; 469 470 sid: eeprom@1c14000 { 471 compatible = "allwinner,sun50i-a64-sid"; 472 reg = <0x1c14000 0x400>; 473 #address-cells = <1>; 474 #size-cells = <1>; 475 476 ths_calibration: thermal-sensor-calibration@34 { 477 reg = <0x34 0x8>; 478 }; 479 }; 480 481 crypto: crypto@1c15000 { 482 compatible = "allwinner,sun50i-a64-crypto"; 483 reg = <0x01c15000 0x1000>; 484 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 486 clock-names = "bus", "mod"; 487 resets = <&ccu RST_BUS_CE>; 488 }; 489 490 usb_otg: usb@1c19000 { 491 compatible = "allwinner,sun8i-a33-musb"; 492 reg = <0x01c19000 0x0400>; 493 clocks = <&ccu CLK_BUS_OTG>; 494 resets = <&ccu RST_BUS_OTG>; 495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "mc"; 497 phys = <&usbphy 0>; 498 phy-names = "usb"; 499 extcon = <&usbphy 0>; 500 dr_mode = "otg"; 501 status = "disabled"; 502 }; 503 504 usbphy: phy@1c19400 { 505 compatible = "allwinner,sun50i-a64-usb-phy"; 506 reg = <0x01c19400 0x14>, 507 <0x01c1a800 0x4>, 508 <0x01c1b800 0x4>; 509 reg-names = "phy_ctrl", 510 "pmu0", 511 "pmu1"; 512 clocks = <&ccu CLK_USB_PHY0>, 513 <&ccu CLK_USB_PHY1>; 514 clock-names = "usb0_phy", 515 "usb1_phy"; 516 resets = <&ccu RST_USB_PHY0>, 517 <&ccu RST_USB_PHY1>; 518 reset-names = "usb0_reset", 519 "usb1_reset"; 520 status = "disabled"; 521 #phy-cells = <1>; 522 }; 523 524 ehci0: usb@1c1a000 { 525 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 526 reg = <0x01c1a000 0x100>; 527 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&ccu CLK_BUS_OHCI0>, 529 <&ccu CLK_BUS_EHCI0>, 530 <&ccu CLK_USB_OHCI0>; 531 resets = <&ccu RST_BUS_OHCI0>, 532 <&ccu RST_BUS_EHCI0>; 533 status = "disabled"; 534 }; 535 536 ohci0: usb@1c1a400 { 537 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 538 reg = <0x01c1a400 0x100>; 539 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&ccu CLK_BUS_OHCI0>, 541 <&ccu CLK_USB_OHCI0>; 542 resets = <&ccu RST_BUS_OHCI0>; 543 status = "disabled"; 544 }; 545 546 ehci1: usb@1c1b000 { 547 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 548 reg = <0x01c1b000 0x100>; 549 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&ccu CLK_BUS_OHCI1>, 551 <&ccu CLK_BUS_EHCI1>, 552 <&ccu CLK_USB_OHCI1>; 553 resets = <&ccu RST_BUS_OHCI1>, 554 <&ccu RST_BUS_EHCI1>; 555 phys = <&usbphy 1>; 556 phy-names = "usb"; 557 status = "disabled"; 558 }; 559 560 ohci1: usb@1c1b400 { 561 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 562 reg = <0x01c1b400 0x100>; 563 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_BUS_OHCI1>, 565 <&ccu CLK_USB_OHCI1>; 566 resets = <&ccu RST_BUS_OHCI1>; 567 phys = <&usbphy 1>; 568 phy-names = "usb"; 569 status = "disabled"; 570 }; 571 572 ccu: clock@1c20000 { 573 compatible = "allwinner,sun50i-a64-ccu"; 574 reg = <0x01c20000 0x400>; 575 clocks = <&osc24M>, <&rtc 0>; 576 clock-names = "hosc", "losc"; 577 #clock-cells = <1>; 578 #reset-cells = <1>; 579 }; 580 581 pio: pinctrl@1c20800 { 582 compatible = "allwinner,sun50i-a64-pinctrl"; 583 reg = <0x01c20800 0x400>; 584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 588 clock-names = "apb", "hosc", "losc"; 589 gpio-controller; 590 #gpio-cells = <3>; 591 interrupt-controller; 592 #interrupt-cells = <3>; 593 594 csi_pins: csi-pins { 595 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 596 "PE7", "PE8", "PE9", "PE10", "PE11"; 597 function = "csi"; 598 }; 599 600 /omit-if-no-ref/ 601 csi_mclk_pin: csi-mclk-pin { 602 pins = "PE1"; 603 function = "csi"; 604 }; 605 606 i2c0_pins: i2c0-pins { 607 pins = "PH0", "PH1"; 608 function = "i2c0"; 609 }; 610 611 i2c1_pins: i2c1-pins { 612 pins = "PH2", "PH3"; 613 function = "i2c1"; 614 }; 615 616 /omit-if-no-ref/ 617 lcd_rgb666_pins: lcd-rgb666-pins { 618 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 619 "PD5", "PD6", "PD7", "PD8", "PD9", 620 "PD10", "PD11", "PD12", "PD13", 621 "PD14", "PD15", "PD16", "PD17", 622 "PD18", "PD19", "PD20", "PD21"; 623 function = "lcd0"; 624 }; 625 626 mmc0_pins: mmc0-pins { 627 pins = "PF0", "PF1", "PF2", "PF3", 628 "PF4", "PF5"; 629 function = "mmc0"; 630 drive-strength = <30>; 631 bias-pull-up; 632 }; 633 634 mmc1_pins: mmc1-pins { 635 pins = "PG0", "PG1", "PG2", "PG3", 636 "PG4", "PG5"; 637 function = "mmc1"; 638 drive-strength = <30>; 639 bias-pull-up; 640 }; 641 642 mmc2_pins: mmc2-pins { 643 pins = "PC5", "PC6", "PC8", "PC9", 644 "PC10","PC11", "PC12", "PC13", 645 "PC14", "PC15", "PC16"; 646 function = "mmc2"; 647 drive-strength = <30>; 648 bias-pull-up; 649 }; 650 651 mmc2_ds_pin: mmc2-ds-pin { 652 pins = "PC1"; 653 function = "mmc2"; 654 drive-strength = <30>; 655 bias-pull-up; 656 }; 657 658 pwm_pin: pwm-pin { 659 pins = "PD22"; 660 function = "pwm"; 661 }; 662 663 rmii_pins: rmii-pins { 664 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 665 "PD18", "PD19", "PD20", "PD22", "PD23"; 666 function = "emac"; 667 drive-strength = <40>; 668 }; 669 670 rgmii_pins: rgmii-pins { 671 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 672 "PD13", "PD15", "PD16", "PD17", "PD18", 673 "PD19", "PD20", "PD21", "PD22", "PD23"; 674 function = "emac"; 675 drive-strength = <40>; 676 }; 677 678 spdif_tx_pin: spdif-tx-pin { 679 pins = "PH8"; 680 function = "spdif"; 681 }; 682 683 spi0_pins: spi0-pins { 684 pins = "PC0", "PC1", "PC2", "PC3"; 685 function = "spi0"; 686 }; 687 688 spi1_pins: spi1-pins { 689 pins = "PD0", "PD1", "PD2", "PD3"; 690 function = "spi1"; 691 }; 692 693 uart0_pb_pins: uart0-pb-pins { 694 pins = "PB8", "PB9"; 695 function = "uart0"; 696 }; 697 698 uart1_pins: uart1-pins { 699 pins = "PG6", "PG7"; 700 function = "uart1"; 701 }; 702 703 uart1_rts_cts_pins: uart1-rts-cts-pins { 704 pins = "PG8", "PG9"; 705 function = "uart1"; 706 }; 707 708 uart2_pins: uart2-pins { 709 pins = "PB0", "PB1"; 710 function = "uart2"; 711 }; 712 713 uart3_pins: uart3-pins { 714 pins = "PD0", "PD1"; 715 function = "uart3"; 716 }; 717 718 uart4_pins: uart4-pins { 719 pins = "PD2", "PD3"; 720 function = "uart4"; 721 }; 722 723 uart4_rts_cts_pins: uart4-rts-cts-pins { 724 pins = "PD4", "PD5"; 725 function = "uart4"; 726 }; 727 }; 728 729 spdif: spdif@1c21000 { 730 #sound-dai-cells = <0>; 731 compatible = "allwinner,sun50i-a64-spdif", 732 "allwinner,sun8i-h3-spdif"; 733 reg = <0x01c21000 0x400>; 734 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 736 resets = <&ccu RST_BUS_SPDIF>; 737 clock-names = "apb", "spdif"; 738 dmas = <&dma 2>; 739 dma-names = "tx"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&spdif_tx_pin>; 742 status = "disabled"; 743 }; 744 745 lradc: lradc@1c21800 { 746 compatible = "allwinner,sun50i-a64-lradc", 747 "allwinner,sun8i-a83t-r-lradc"; 748 reg = <0x01c21800 0x400>; 749 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 750 status = "disabled"; 751 }; 752 753 i2s0: i2s@1c22000 { 754 #sound-dai-cells = <0>; 755 compatible = "allwinner,sun50i-a64-i2s", 756 "allwinner,sun8i-h3-i2s"; 757 reg = <0x01c22000 0x400>; 758 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 760 clock-names = "apb", "mod"; 761 resets = <&ccu RST_BUS_I2S0>; 762 dma-names = "rx", "tx"; 763 dmas = <&dma 3>, <&dma 3>; 764 status = "disabled"; 765 }; 766 767 i2s1: i2s@1c22400 { 768 #sound-dai-cells = <0>; 769 compatible = "allwinner,sun50i-a64-i2s", 770 "allwinner,sun8i-h3-i2s"; 771 reg = <0x01c22400 0x400>; 772 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 774 clock-names = "apb", "mod"; 775 resets = <&ccu RST_BUS_I2S1>; 776 dma-names = "rx", "tx"; 777 dmas = <&dma 4>, <&dma 4>; 778 status = "disabled"; 779 }; 780 781 dai: dai@1c22c00 { 782 #sound-dai-cells = <0>; 783 compatible = "allwinner,sun50i-a64-codec-i2s"; 784 reg = <0x01c22c00 0x200>; 785 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 787 clock-names = "apb", "mod"; 788 resets = <&ccu RST_BUS_CODEC>; 789 dmas = <&dma 15>, <&dma 15>; 790 dma-names = "rx", "tx"; 791 status = "disabled"; 792 }; 793 794 codec: codec@1c22e00 { 795 #sound-dai-cells = <0>; 796 compatible = "allwinner,sun8i-a33-codec"; 797 reg = <0x01c22e00 0x600>; 798 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 800 clock-names = "bus", "mod"; 801 status = "disabled"; 802 }; 803 804 ths: thermal-sensor@1c25000 { 805 compatible = "allwinner,sun50i-a64-ths"; 806 reg = <0x01c25000 0x100>; 807 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 808 clock-names = "bus", "mod"; 809 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 810 resets = <&ccu RST_BUS_THS>; 811 nvmem-cells = <&ths_calibration>; 812 nvmem-cell-names = "calibration"; 813 #thermal-sensor-cells = <1>; 814 }; 815 816 uart0: serial@1c28000 { 817 compatible = "snps,dw-apb-uart"; 818 reg = <0x01c28000 0x400>; 819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 820 reg-shift = <2>; 821 reg-io-width = <4>; 822 clocks = <&ccu CLK_BUS_UART0>; 823 resets = <&ccu RST_BUS_UART0>; 824 status = "disabled"; 825 }; 826 827 uart1: serial@1c28400 { 828 compatible = "snps,dw-apb-uart"; 829 reg = <0x01c28400 0x400>; 830 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 831 reg-shift = <2>; 832 reg-io-width = <4>; 833 clocks = <&ccu CLK_BUS_UART1>; 834 resets = <&ccu RST_BUS_UART1>; 835 status = "disabled"; 836 }; 837 838 uart2: serial@1c28800 { 839 compatible = "snps,dw-apb-uart"; 840 reg = <0x01c28800 0x400>; 841 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 842 reg-shift = <2>; 843 reg-io-width = <4>; 844 clocks = <&ccu CLK_BUS_UART2>; 845 resets = <&ccu RST_BUS_UART2>; 846 status = "disabled"; 847 }; 848 849 uart3: serial@1c28c00 { 850 compatible = "snps,dw-apb-uart"; 851 reg = <0x01c28c00 0x400>; 852 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 853 reg-shift = <2>; 854 reg-io-width = <4>; 855 clocks = <&ccu CLK_BUS_UART3>; 856 resets = <&ccu RST_BUS_UART3>; 857 status = "disabled"; 858 }; 859 860 uart4: serial@1c29000 { 861 compatible = "snps,dw-apb-uart"; 862 reg = <0x01c29000 0x400>; 863 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 864 reg-shift = <2>; 865 reg-io-width = <4>; 866 clocks = <&ccu CLK_BUS_UART4>; 867 resets = <&ccu RST_BUS_UART4>; 868 status = "disabled"; 869 }; 870 871 i2c0: i2c@1c2ac00 { 872 compatible = "allwinner,sun6i-a31-i2c"; 873 reg = <0x01c2ac00 0x400>; 874 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&ccu CLK_BUS_I2C0>; 876 resets = <&ccu RST_BUS_I2C0>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&i2c0_pins>; 879 status = "disabled"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 }; 883 884 i2c1: i2c@1c2b000 { 885 compatible = "allwinner,sun6i-a31-i2c"; 886 reg = <0x01c2b000 0x400>; 887 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&ccu CLK_BUS_I2C1>; 889 resets = <&ccu RST_BUS_I2C1>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&i2c1_pins>; 892 status = "disabled"; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 }; 896 897 i2c2: i2c@1c2b400 { 898 compatible = "allwinner,sun6i-a31-i2c"; 899 reg = <0x01c2b400 0x400>; 900 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&ccu CLK_BUS_I2C2>; 902 resets = <&ccu RST_BUS_I2C2>; 903 status = "disabled"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 }; 907 908 909 spi0: spi@1c68000 { 910 compatible = "allwinner,sun8i-h3-spi"; 911 reg = <0x01c68000 0x1000>; 912 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 914 clock-names = "ahb", "mod"; 915 dmas = <&dma 23>, <&dma 23>; 916 dma-names = "rx", "tx"; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&spi0_pins>; 919 resets = <&ccu RST_BUS_SPI0>; 920 status = "disabled"; 921 num-cs = <1>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 }; 925 926 spi1: spi@1c69000 { 927 compatible = "allwinner,sun8i-h3-spi"; 928 reg = <0x01c69000 0x1000>; 929 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 931 clock-names = "ahb", "mod"; 932 dmas = <&dma 24>, <&dma 24>; 933 dma-names = "rx", "tx"; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&spi1_pins>; 936 resets = <&ccu RST_BUS_SPI1>; 937 status = "disabled"; 938 num-cs = <1>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 }; 942 943 emac: ethernet@1c30000 { 944 compatible = "allwinner,sun50i-a64-emac"; 945 syscon = <&syscon>; 946 reg = <0x01c30000 0x10000>; 947 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "macirq"; 949 resets = <&ccu RST_BUS_EMAC>; 950 reset-names = "stmmaceth"; 951 clocks = <&ccu CLK_BUS_EMAC>; 952 clock-names = "stmmaceth"; 953 status = "disabled"; 954 955 mdio: mdio { 956 compatible = "snps,dwmac-mdio"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 }; 960 }; 961 962 mali: gpu@1c40000 { 963 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 964 reg = <0x01c40000 0x10000>; 965 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "gp", 973 "gpmmu", 974 "pp0", 975 "ppmmu0", 976 "pp1", 977 "ppmmu1", 978 "pmu"; 979 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 980 clock-names = "bus", "core"; 981 resets = <&ccu RST_BUS_GPU>; 982 }; 983 984 gic: interrupt-controller@1c81000 { 985 compatible = "arm,gic-400"; 986 reg = <0x01c81000 0x1000>, 987 <0x01c82000 0x2000>, 988 <0x01c84000 0x2000>, 989 <0x01c86000 0x2000>; 990 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 991 interrupt-controller; 992 #interrupt-cells = <3>; 993 }; 994 995 pwm: pwm@1c21400 { 996 compatible = "allwinner,sun50i-a64-pwm", 997 "allwinner,sun5i-a13-pwm"; 998 reg = <0x01c21400 0x400>; 999 clocks = <&osc24M>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&pwm_pin>; 1002 #pwm-cells = <3>; 1003 status = "disabled"; 1004 }; 1005 1006 csi: csi@1cb0000 { 1007 compatible = "allwinner,sun50i-a64-csi"; 1008 reg = <0x01cb0000 0x1000>; 1009 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&ccu CLK_BUS_CSI>, 1011 <&ccu CLK_CSI_SCLK>, 1012 <&ccu CLK_DRAM_CSI>; 1013 clock-names = "bus", "mod", "ram"; 1014 resets = <&ccu RST_BUS_CSI>; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&csi_pins>; 1017 status = "disabled"; 1018 }; 1019 1020 hdmi: hdmi@1ee0000 { 1021 compatible = "allwinner,sun50i-a64-dw-hdmi", 1022 "allwinner,sun8i-a83t-dw-hdmi"; 1023 reg = <0x01ee0000 0x10000>; 1024 reg-io-width = <1>; 1025 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1027 <&ccu CLK_HDMI>; 1028 clock-names = "iahb", "isfr", "tmds"; 1029 resets = <&ccu RST_BUS_HDMI1>; 1030 reset-names = "ctrl"; 1031 phys = <&hdmi_phy>; 1032 phy-names = "phy"; 1033 status = "disabled"; 1034 1035 ports { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 1039 hdmi_in: port@0 { 1040 reg = <0>; 1041 1042 hdmi_in_tcon1: endpoint { 1043 remote-endpoint = <&tcon1_out_hdmi>; 1044 }; 1045 }; 1046 1047 hdmi_out: port@1 { 1048 reg = <1>; 1049 }; 1050 }; 1051 }; 1052 1053 hdmi_phy: hdmi-phy@1ef0000 { 1054 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1055 reg = <0x01ef0000 0x10000>; 1056 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1057 <&ccu 7>; 1058 clock-names = "bus", "mod", "pll-0"; 1059 resets = <&ccu RST_BUS_HDMI0>; 1060 reset-names = "phy"; 1061 #phy-cells = <0>; 1062 }; 1063 1064 rtc: rtc@1f00000 { 1065 compatible = "allwinner,sun50i-a64-rtc", 1066 "allwinner,sun8i-h3-rtc"; 1067 reg = <0x01f00000 0x400>; 1068 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1070 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1071 clocks = <&osc32k>; 1072 #clock-cells = <1>; 1073 }; 1074 1075 r_intc: interrupt-controller@1f00c00 { 1076 compatible = "allwinner,sun50i-a64-r-intc", 1077 "allwinner,sun6i-a31-r-intc"; 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 reg = <0x01f00c00 0x400>; 1081 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1082 }; 1083 1084 r_ccu: clock@1f01400 { 1085 compatible = "allwinner,sun50i-a64-r-ccu"; 1086 reg = <0x01f01400 0x100>; 1087 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1088 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1089 #clock-cells = <1>; 1090 #reset-cells = <1>; 1091 }; 1092 1093 codec_analog: codec-analog@1f015c0 { 1094 compatible = "allwinner,sun50i-a64-codec-analog"; 1095 reg = <0x01f015c0 0x4>; 1096 status = "disabled"; 1097 }; 1098 1099 r_i2c: i2c@1f02400 { 1100 compatible = "allwinner,sun50i-a64-i2c", 1101 "allwinner,sun6i-a31-i2c"; 1102 reg = <0x01f02400 0x400>; 1103 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&r_ccu CLK_APB0_I2C>; 1105 resets = <&r_ccu RST_APB0_I2C>; 1106 status = "disabled"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 }; 1110 1111 r_ir: ir@1f02000 { 1112 compatible = "allwinner,sun50i-a64-ir", 1113 "allwinner,sun6i-a31-ir"; 1114 reg = <0x01f02000 0x400>; 1115 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1116 clock-names = "apb", "ir"; 1117 resets = <&r_ccu RST_APB0_IR>; 1118 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&r_ir_rx_pin>; 1121 status = "disabled"; 1122 }; 1123 1124 r_pwm: pwm@1f03800 { 1125 compatible = "allwinner,sun50i-a64-pwm", 1126 "allwinner,sun5i-a13-pwm"; 1127 reg = <0x01f03800 0x400>; 1128 clocks = <&osc24M>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&r_pwm_pin>; 1131 #pwm-cells = <3>; 1132 status = "disabled"; 1133 }; 1134 1135 r_pio: pinctrl@1f02c00 { 1136 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1137 reg = <0x01f02c00 0x400>; 1138 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1140 clock-names = "apb", "hosc", "losc"; 1141 gpio-controller; 1142 #gpio-cells = <3>; 1143 interrupt-controller; 1144 #interrupt-cells = <3>; 1145 1146 r_i2c_pl89_pins: r-i2c-pl89-pins { 1147 pins = "PL8", "PL9"; 1148 function = "s_i2c"; 1149 }; 1150 1151 r_ir_rx_pin: r-ir-rx-pin { 1152 pins = "PL11"; 1153 function = "s_cir_rx"; 1154 }; 1155 1156 r_pwm_pin: r-pwm-pin { 1157 pins = "PL10"; 1158 function = "s_pwm"; 1159 }; 1160 1161 r_rsb_pins: r-rsb-pins { 1162 pins = "PL0", "PL1"; 1163 function = "s_rsb"; 1164 }; 1165 }; 1166 1167 r_rsb: rsb@1f03400 { 1168 compatible = "allwinner,sun8i-a23-rsb"; 1169 reg = <0x01f03400 0x400>; 1170 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&r_ccu 6>; 1172 clock-frequency = <3000000>; 1173 resets = <&r_ccu 2>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&r_rsb_pins>; 1176 status = "disabled"; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 }; 1180 1181 wdt0: watchdog@1c20ca0 { 1182 compatible = "allwinner,sun50i-a64-wdt", 1183 "allwinner,sun6i-a31-wdt"; 1184 reg = <0x01c20ca0 0x20>; 1185 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&osc24M>; 1187 }; 1188 }; 1189}; 1190