1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 de2@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_DE>, 232 <&ccu CLK_BUS_DE>; 233 clock-names = "mod", 234 "bus"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <1>; 257 258 mixer0_out_tcon0: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&tcon0_in_mixer0>; 261 }; 262 263 mixer0_out_tcon1: endpoint@1 { 264 reg = <1>; 265 remote-endpoint = <&tcon1_in_mixer0>; 266 }; 267 }; 268 }; 269 }; 270 271 mixer1: mixer@200000 { 272 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273 reg = <0x200000 0x100000>; 274 clocks = <&display_clocks CLK_BUS_MIXER1>, 275 <&display_clocks CLK_MIXER1>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&display_clocks RST_MIXER1>; 279 280 ports { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 mixer1_out: port@1 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <1>; 288 289 mixer1_out_tcon0: endpoint@0 { 290 reg = <0>; 291 remote-endpoint = <&tcon0_in_mixer1>; 292 }; 293 294 mixer1_out_tcon1: endpoint@1 { 295 reg = <1>; 296 remote-endpoint = <&tcon1_in_mixer1>; 297 }; 298 }; 299 }; 300 }; 301 }; 302 303 syscon: syscon@1c00000 { 304 compatible = "allwinner,sun50i-a64-system-control"; 305 reg = <0x01c00000 0x1000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges; 309 310 sram_c: sram@18000 { 311 compatible = "mmio-sram"; 312 reg = <0x00018000 0x28000>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0 0x00018000 0x28000>; 316 317 de2_sram: sram-section@0 { 318 compatible = "allwinner,sun50i-a64-sram-c"; 319 reg = <0x0000 0x28000>; 320 }; 321 }; 322 323 sram_c1: sram@1d00000 { 324 compatible = "mmio-sram"; 325 reg = <0x01d00000 0x40000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0 0x01d00000 0x40000>; 329 330 ve_sram: sram-section@0 { 331 compatible = "allwinner,sun50i-a64-sram-c1", 332 "allwinner,sun4i-a10-sram-c1"; 333 reg = <0x000000 0x40000>; 334 }; 335 }; 336 }; 337 338 dma: dma-controller@1c02000 { 339 compatible = "allwinner,sun50i-a64-dma"; 340 reg = <0x01c02000 0x1000>; 341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&ccu CLK_BUS_DMA>; 343 dma-channels = <8>; 344 dma-requests = <27>; 345 resets = <&ccu RST_BUS_DMA>; 346 #dma-cells = <1>; 347 }; 348 349 tcon0: lcd-controller@1c0c000 { 350 compatible = "allwinner,sun50i-a64-tcon-lcd", 351 "allwinner,sun8i-a83t-tcon-lcd"; 352 reg = <0x01c0c000 0x1000>; 353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 355 clock-names = "ahb", "tcon-ch0"; 356 clock-output-names = "tcon-pixel-clock"; 357 #clock-cells = <0>; 358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 359 reset-names = "lcd", "lvds"; 360 361 ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 tcon0_in: port@0 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0>; 369 370 tcon0_in_mixer0: endpoint@0 { 371 reg = <0>; 372 remote-endpoint = <&mixer0_out_tcon0>; 373 }; 374 375 tcon0_in_mixer1: endpoint@1 { 376 reg = <1>; 377 remote-endpoint = <&mixer1_out_tcon0>; 378 }; 379 }; 380 381 tcon0_out: port@1 { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <1>; 385 }; 386 }; 387 }; 388 389 tcon1: lcd-controller@1c0d000 { 390 compatible = "allwinner,sun50i-a64-tcon-tv", 391 "allwinner,sun8i-a83t-tcon-tv"; 392 reg = <0x01c0d000 0x1000>; 393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 395 clock-names = "ahb", "tcon-ch1"; 396 resets = <&ccu RST_BUS_TCON1>; 397 reset-names = "lcd"; 398 399 ports { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 tcon1_in: port@0 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0>; 407 408 tcon1_in_mixer0: endpoint@0 { 409 reg = <0>; 410 remote-endpoint = <&mixer0_out_tcon1>; 411 }; 412 413 tcon1_in_mixer1: endpoint@1 { 414 reg = <1>; 415 remote-endpoint = <&mixer1_out_tcon1>; 416 }; 417 }; 418 419 tcon1_out: port@1 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <1>; 423 424 tcon1_out_hdmi: endpoint@1 { 425 reg = <1>; 426 remote-endpoint = <&hdmi_in_tcon1>; 427 }; 428 }; 429 }; 430 }; 431 432 video-codec@1c0e000 { 433 compatible = "allwinner,sun50i-a64-video-engine"; 434 reg = <0x01c0e000 0x1000>; 435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 436 <&ccu CLK_DRAM_VE>; 437 clock-names = "ahb", "mod", "ram"; 438 resets = <&ccu RST_BUS_VE>; 439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 440 allwinner,sram = <&ve_sram 1>; 441 }; 442 443 mmc0: mmc@1c0f000 { 444 compatible = "allwinner,sun50i-a64-mmc"; 445 reg = <0x01c0f000 0x1000>; 446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 447 clock-names = "ahb", "mmc"; 448 resets = <&ccu RST_BUS_MMC0>; 449 reset-names = "ahb"; 450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 451 max-frequency = <150000000>; 452 status = "disabled"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 }; 456 457 mmc1: mmc@1c10000 { 458 compatible = "allwinner,sun50i-a64-mmc"; 459 reg = <0x01c10000 0x1000>; 460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 461 clock-names = "ahb", "mmc"; 462 resets = <&ccu RST_BUS_MMC1>; 463 reset-names = "ahb"; 464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 465 max-frequency = <150000000>; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 mmc2: mmc@1c11000 { 472 compatible = "allwinner,sun50i-a64-emmc"; 473 reg = <0x01c11000 0x1000>; 474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 475 clock-names = "ahb", "mmc"; 476 resets = <&ccu RST_BUS_MMC2>; 477 reset-names = "ahb"; 478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 479 max-frequency = <200000000>; 480 status = "disabled"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 }; 484 485 sid: eeprom@1c14000 { 486 compatible = "allwinner,sun50i-a64-sid"; 487 reg = <0x1c14000 0x400>; 488 }; 489 490 usb_otg: usb@1c19000 { 491 compatible = "allwinner,sun8i-a33-musb"; 492 reg = <0x01c19000 0x0400>; 493 clocks = <&ccu CLK_BUS_OTG>; 494 resets = <&ccu RST_BUS_OTG>; 495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "mc"; 497 phys = <&usbphy 0>; 498 phy-names = "usb"; 499 extcon = <&usbphy 0>; 500 status = "disabled"; 501 }; 502 503 usbphy: phy@1c19400 { 504 compatible = "allwinner,sun50i-a64-usb-phy"; 505 reg = <0x01c19400 0x14>, 506 <0x01c1a800 0x4>, 507 <0x01c1b800 0x4>; 508 reg-names = "phy_ctrl", 509 "pmu0", 510 "pmu1"; 511 clocks = <&ccu CLK_USB_PHY0>, 512 <&ccu CLK_USB_PHY1>; 513 clock-names = "usb0_phy", 514 "usb1_phy"; 515 resets = <&ccu RST_USB_PHY0>, 516 <&ccu RST_USB_PHY1>; 517 reset-names = "usb0_reset", 518 "usb1_reset"; 519 status = "disabled"; 520 #phy-cells = <1>; 521 }; 522 523 ehci0: usb@1c1a000 { 524 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 525 reg = <0x01c1a000 0x100>; 526 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&ccu CLK_BUS_OHCI0>, 528 <&ccu CLK_BUS_EHCI0>, 529 <&ccu CLK_USB_OHCI0>; 530 resets = <&ccu RST_BUS_OHCI0>, 531 <&ccu RST_BUS_EHCI0>; 532 status = "disabled"; 533 }; 534 535 ohci0: usb@1c1a400 { 536 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 537 reg = <0x01c1a400 0x100>; 538 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&ccu CLK_BUS_OHCI0>, 540 <&ccu CLK_USB_OHCI0>; 541 resets = <&ccu RST_BUS_OHCI0>; 542 status = "disabled"; 543 }; 544 545 ehci1: usb@1c1b000 { 546 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 547 reg = <0x01c1b000 0x100>; 548 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_BUS_OHCI1>, 550 <&ccu CLK_BUS_EHCI1>, 551 <&ccu CLK_USB_OHCI1>; 552 resets = <&ccu RST_BUS_OHCI1>, 553 <&ccu RST_BUS_EHCI1>; 554 phys = <&usbphy 1>; 555 phy-names = "usb"; 556 status = "disabled"; 557 }; 558 559 ohci1: usb@1c1b400 { 560 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 561 reg = <0x01c1b400 0x100>; 562 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&ccu CLK_BUS_OHCI1>, 564 <&ccu CLK_USB_OHCI1>; 565 resets = <&ccu RST_BUS_OHCI1>; 566 phys = <&usbphy 1>; 567 phy-names = "usb"; 568 status = "disabled"; 569 }; 570 571 ccu: clock@1c20000 { 572 compatible = "allwinner,sun50i-a64-ccu"; 573 reg = <0x01c20000 0x400>; 574 clocks = <&osc24M>, <&rtc 0>; 575 clock-names = "hosc", "losc"; 576 #clock-cells = <1>; 577 #reset-cells = <1>; 578 }; 579 580 pio: pinctrl@1c20800 { 581 compatible = "allwinner,sun50i-a64-pinctrl"; 582 reg = <0x01c20800 0x400>; 583 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 587 clock-names = "apb", "hosc", "losc"; 588 gpio-controller; 589 #gpio-cells = <3>; 590 interrupt-controller; 591 #interrupt-cells = <3>; 592 593 csi_pins: csi-pins { 594 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 595 "PE7", "PE8", "PE9", "PE10", "PE11"; 596 function = "csi"; 597 }; 598 599 i2c0_pins: i2c0-pins { 600 pins = "PH0", "PH1"; 601 function = "i2c0"; 602 }; 603 604 i2c1_pins: i2c1-pins { 605 pins = "PH2", "PH3"; 606 function = "i2c1"; 607 }; 608 609 mmc0_pins: mmc0-pins { 610 pins = "PF0", "PF1", "PF2", "PF3", 611 "PF4", "PF5"; 612 function = "mmc0"; 613 drive-strength = <30>; 614 bias-pull-up; 615 }; 616 617 mmc1_pins: mmc1-pins { 618 pins = "PG0", "PG1", "PG2", "PG3", 619 "PG4", "PG5"; 620 function = "mmc1"; 621 drive-strength = <30>; 622 bias-pull-up; 623 }; 624 625 mmc2_pins: mmc2-pins { 626 pins = "PC5", "PC6", "PC8", "PC9", 627 "PC10","PC11", "PC12", "PC13", 628 "PC14", "PC15", "PC16"; 629 function = "mmc2"; 630 drive-strength = <30>; 631 bias-pull-up; 632 }; 633 634 mmc2_ds_pin: mmc2-ds-pin { 635 pins = "PC1"; 636 function = "mmc2"; 637 drive-strength = <30>; 638 bias-pull-up; 639 }; 640 641 pwm_pin: pwm-pin { 642 pins = "PD22"; 643 function = "pwm"; 644 }; 645 646 rmii_pins: rmii-pins { 647 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 648 "PD18", "PD19", "PD20", "PD22", "PD23"; 649 function = "emac"; 650 drive-strength = <40>; 651 }; 652 653 rgmii_pins: rgmii-pins { 654 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 655 "PD13", "PD15", "PD16", "PD17", "PD18", 656 "PD19", "PD20", "PD21", "PD22", "PD23"; 657 function = "emac"; 658 drive-strength = <40>; 659 }; 660 661 spdif_tx_pin: spdif-tx-pin { 662 pins = "PH8"; 663 function = "spdif"; 664 }; 665 666 spi0_pins: spi0-pins { 667 pins = "PC0", "PC1", "PC2", "PC3"; 668 function = "spi0"; 669 }; 670 671 spi1_pins: spi1-pins { 672 pins = "PD0", "PD1", "PD2", "PD3"; 673 function = "spi1"; 674 }; 675 676 uart0_pb_pins: uart0-pb-pins { 677 pins = "PB8", "PB9"; 678 function = "uart0"; 679 }; 680 681 uart1_pins: uart1-pins { 682 pins = "PG6", "PG7"; 683 function = "uart1"; 684 }; 685 686 uart1_rts_cts_pins: uart1-rts-cts-pins { 687 pins = "PG8", "PG9"; 688 function = "uart1"; 689 }; 690 691 uart2_pins: uart2-pins { 692 pins = "PB0", "PB1"; 693 function = "uart2"; 694 }; 695 696 uart3_pins: uart3-pins { 697 pins = "PD0", "PD1"; 698 function = "uart3"; 699 }; 700 701 uart4_pins: uart4-pins { 702 pins = "PD2", "PD3"; 703 function = "uart4"; 704 }; 705 706 uart4_rts_cts_pins: uart4-rts-cts-pins { 707 pins = "PD4", "PD5"; 708 function = "uart4"; 709 }; 710 }; 711 712 spdif: spdif@1c21000 { 713 #sound-dai-cells = <0>; 714 compatible = "allwinner,sun50i-a64-spdif", 715 "allwinner,sun8i-h3-spdif"; 716 reg = <0x01c21000 0x400>; 717 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 719 resets = <&ccu RST_BUS_SPDIF>; 720 clock-names = "apb", "spdif"; 721 dmas = <&dma 2>; 722 dma-names = "tx"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&spdif_tx_pin>; 725 status = "disabled"; 726 }; 727 728 i2s0: i2s@1c22000 { 729 #sound-dai-cells = <0>; 730 compatible = "allwinner,sun50i-a64-i2s", 731 "allwinner,sun8i-h3-i2s"; 732 reg = <0x01c22000 0x400>; 733 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 735 clock-names = "apb", "mod"; 736 resets = <&ccu RST_BUS_I2S0>; 737 dma-names = "rx", "tx"; 738 dmas = <&dma 3>, <&dma 3>; 739 status = "disabled"; 740 }; 741 742 i2s1: i2s@1c22400 { 743 #sound-dai-cells = <0>; 744 compatible = "allwinner,sun50i-a64-i2s", 745 "allwinner,sun8i-h3-i2s"; 746 reg = <0x01c22400 0x400>; 747 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 749 clock-names = "apb", "mod"; 750 resets = <&ccu RST_BUS_I2S1>; 751 dma-names = "rx", "tx"; 752 dmas = <&dma 4>, <&dma 4>; 753 status = "disabled"; 754 }; 755 756 dai: dai@1c22c00 { 757 #sound-dai-cells = <0>; 758 compatible = "allwinner,sun50i-a64-codec-i2s"; 759 reg = <0x01c22c00 0x200>; 760 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 762 clock-names = "apb", "mod"; 763 resets = <&ccu RST_BUS_CODEC>; 764 reset-names = "rst"; 765 dmas = <&dma 15>, <&dma 15>; 766 dma-names = "rx", "tx"; 767 status = "disabled"; 768 }; 769 770 codec: codec@1c22e00 { 771 #sound-dai-cells = <0>; 772 compatible = "allwinner,sun8i-a33-codec"; 773 reg = <0x01c22e00 0x600>; 774 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 776 clock-names = "bus", "mod"; 777 status = "disabled"; 778 }; 779 780 uart0: serial@1c28000 { 781 compatible = "snps,dw-apb-uart"; 782 reg = <0x01c28000 0x400>; 783 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 784 reg-shift = <2>; 785 reg-io-width = <4>; 786 clocks = <&ccu CLK_BUS_UART0>; 787 resets = <&ccu RST_BUS_UART0>; 788 status = "disabled"; 789 }; 790 791 uart1: serial@1c28400 { 792 compatible = "snps,dw-apb-uart"; 793 reg = <0x01c28400 0x400>; 794 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 795 reg-shift = <2>; 796 reg-io-width = <4>; 797 clocks = <&ccu CLK_BUS_UART1>; 798 resets = <&ccu RST_BUS_UART1>; 799 status = "disabled"; 800 }; 801 802 uart2: serial@1c28800 { 803 compatible = "snps,dw-apb-uart"; 804 reg = <0x01c28800 0x400>; 805 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 806 reg-shift = <2>; 807 reg-io-width = <4>; 808 clocks = <&ccu CLK_BUS_UART2>; 809 resets = <&ccu RST_BUS_UART2>; 810 status = "disabled"; 811 }; 812 813 uart3: serial@1c28c00 { 814 compatible = "snps,dw-apb-uart"; 815 reg = <0x01c28c00 0x400>; 816 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 817 reg-shift = <2>; 818 reg-io-width = <4>; 819 clocks = <&ccu CLK_BUS_UART3>; 820 resets = <&ccu RST_BUS_UART3>; 821 status = "disabled"; 822 }; 823 824 uart4: serial@1c29000 { 825 compatible = "snps,dw-apb-uart"; 826 reg = <0x01c29000 0x400>; 827 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 828 reg-shift = <2>; 829 reg-io-width = <4>; 830 clocks = <&ccu CLK_BUS_UART4>; 831 resets = <&ccu RST_BUS_UART4>; 832 status = "disabled"; 833 }; 834 835 i2c0: i2c@1c2ac00 { 836 compatible = "allwinner,sun6i-a31-i2c"; 837 reg = <0x01c2ac00 0x400>; 838 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&ccu CLK_BUS_I2C0>; 840 resets = <&ccu RST_BUS_I2C0>; 841 status = "disabled"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 }; 845 846 i2c1: i2c@1c2b000 { 847 compatible = "allwinner,sun6i-a31-i2c"; 848 reg = <0x01c2b000 0x400>; 849 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&ccu CLK_BUS_I2C1>; 851 resets = <&ccu RST_BUS_I2C1>; 852 status = "disabled"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 }; 856 857 i2c2: i2c@1c2b400 { 858 compatible = "allwinner,sun6i-a31-i2c"; 859 reg = <0x01c2b400 0x400>; 860 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&ccu CLK_BUS_I2C2>; 862 resets = <&ccu RST_BUS_I2C2>; 863 status = "disabled"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 }; 867 868 869 spi0: spi@1c68000 { 870 compatible = "allwinner,sun8i-h3-spi"; 871 reg = <0x01c68000 0x1000>; 872 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 874 clock-names = "ahb", "mod"; 875 dmas = <&dma 23>, <&dma 23>; 876 dma-names = "rx", "tx"; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&spi0_pins>; 879 resets = <&ccu RST_BUS_SPI0>; 880 status = "disabled"; 881 num-cs = <1>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 }; 885 886 spi1: spi@1c69000 { 887 compatible = "allwinner,sun8i-h3-spi"; 888 reg = <0x01c69000 0x1000>; 889 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 891 clock-names = "ahb", "mod"; 892 dmas = <&dma 24>, <&dma 24>; 893 dma-names = "rx", "tx"; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&spi1_pins>; 896 resets = <&ccu RST_BUS_SPI1>; 897 status = "disabled"; 898 num-cs = <1>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 }; 902 903 emac: ethernet@1c30000 { 904 compatible = "allwinner,sun50i-a64-emac"; 905 syscon = <&syscon>; 906 reg = <0x01c30000 0x10000>; 907 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "macirq"; 909 resets = <&ccu RST_BUS_EMAC>; 910 reset-names = "stmmaceth"; 911 clocks = <&ccu CLK_BUS_EMAC>; 912 clock-names = "stmmaceth"; 913 status = "disabled"; 914 915 mdio: mdio { 916 compatible = "snps,dwmac-mdio"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 }; 920 }; 921 922 mali: gpu@1c40000 { 923 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 924 reg = <0x01c40000 0x10000>; 925 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 932 interrupt-names = "gp", 933 "gpmmu", 934 "pp0", 935 "ppmmu0", 936 "pp1", 937 "ppmmu1", 938 "pmu"; 939 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 940 clock-names = "bus", "core"; 941 resets = <&ccu RST_BUS_GPU>; 942 }; 943 944 gic: interrupt-controller@1c81000 { 945 compatible = "arm,gic-400"; 946 reg = <0x01c81000 0x1000>, 947 <0x01c82000 0x2000>, 948 <0x01c84000 0x2000>, 949 <0x01c86000 0x2000>; 950 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 951 interrupt-controller; 952 #interrupt-cells = <3>; 953 }; 954 955 pwm: pwm@1c21400 { 956 compatible = "allwinner,sun50i-a64-pwm", 957 "allwinner,sun5i-a13-pwm"; 958 reg = <0x01c21400 0x400>; 959 clocks = <&osc24M>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&pwm_pin>; 962 #pwm-cells = <3>; 963 status = "disabled"; 964 }; 965 966 csi: csi@1cb0000 { 967 compatible = "allwinner,sun50i-a64-csi"; 968 reg = <0x01cb0000 0x1000>; 969 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&ccu CLK_BUS_CSI>, 971 <&ccu CLK_CSI_SCLK>, 972 <&ccu CLK_DRAM_CSI>; 973 clock-names = "bus", "mod", "ram"; 974 resets = <&ccu RST_BUS_CSI>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&csi_pins>; 977 status = "disabled"; 978 }; 979 980 hdmi: hdmi@1ee0000 { 981 compatible = "allwinner,sun50i-a64-dw-hdmi", 982 "allwinner,sun8i-a83t-dw-hdmi"; 983 reg = <0x01ee0000 0x10000>; 984 reg-io-width = <1>; 985 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 987 <&ccu CLK_HDMI>; 988 clock-names = "iahb", "isfr", "tmds"; 989 resets = <&ccu RST_BUS_HDMI1>; 990 reset-names = "ctrl"; 991 phys = <&hdmi_phy>; 992 phy-names = "hdmi-phy"; 993 status = "disabled"; 994 995 ports { 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 hdmi_in: port@0 { 1000 reg = <0>; 1001 1002 hdmi_in_tcon1: endpoint { 1003 remote-endpoint = <&tcon1_out_hdmi>; 1004 }; 1005 }; 1006 1007 hdmi_out: port@1 { 1008 reg = <1>; 1009 }; 1010 }; 1011 }; 1012 1013 hdmi_phy: hdmi-phy@1ef0000 { 1014 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1015 reg = <0x01ef0000 0x10000>; 1016 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1017 <&ccu 7>; 1018 clock-names = "bus", "mod", "pll-0"; 1019 resets = <&ccu RST_BUS_HDMI0>; 1020 reset-names = "phy"; 1021 #phy-cells = <0>; 1022 }; 1023 1024 rtc: rtc@1f00000 { 1025 compatible = "allwinner,sun50i-a64-rtc", 1026 "allwinner,sun8i-h3-rtc"; 1027 reg = <0x01f00000 0x400>; 1028 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1030 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1031 clocks = <&osc32k>; 1032 #clock-cells = <1>; 1033 }; 1034 1035 r_intc: interrupt-controller@1f00c00 { 1036 compatible = "allwinner,sun50i-a64-r-intc", 1037 "allwinner,sun6i-a31-r-intc"; 1038 interrupt-controller; 1039 #interrupt-cells = <2>; 1040 reg = <0x01f00c00 0x400>; 1041 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1042 }; 1043 1044 r_ccu: clock@1f01400 { 1045 compatible = "allwinner,sun50i-a64-r-ccu"; 1046 reg = <0x01f01400 0x100>; 1047 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1048 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1049 #clock-cells = <1>; 1050 #reset-cells = <1>; 1051 }; 1052 1053 codec_analog: codec-analog@1f015c0 { 1054 compatible = "allwinner,sun50i-a64-codec-analog"; 1055 reg = <0x01f015c0 0x4>; 1056 status = "disabled"; 1057 }; 1058 1059 r_i2c: i2c@1f02400 { 1060 compatible = "allwinner,sun50i-a64-i2c", 1061 "allwinner,sun6i-a31-i2c"; 1062 reg = <0x01f02400 0x400>; 1063 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&r_ccu CLK_APB0_I2C>; 1065 resets = <&r_ccu RST_APB0_I2C>; 1066 status = "disabled"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 }; 1070 1071 r_pwm: pwm@1f03800 { 1072 compatible = "allwinner,sun50i-a64-pwm", 1073 "allwinner,sun5i-a13-pwm"; 1074 reg = <0x01f03800 0x400>; 1075 clocks = <&osc24M>; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&r_pwm_pin>; 1078 #pwm-cells = <3>; 1079 status = "disabled"; 1080 }; 1081 1082 r_pio: pinctrl@1f02c00 { 1083 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1084 reg = <0x01f02c00 0x400>; 1085 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1087 clock-names = "apb", "hosc", "losc"; 1088 gpio-controller; 1089 #gpio-cells = <3>; 1090 interrupt-controller; 1091 #interrupt-cells = <3>; 1092 1093 r_i2c_pl89_pins: r-i2c-pl89-pins { 1094 pins = "PL8", "PL9"; 1095 function = "s_i2c"; 1096 }; 1097 1098 r_pwm_pin: r-pwm-pin { 1099 pins = "PL10"; 1100 function = "s_pwm"; 1101 }; 1102 1103 r_rsb_pins: r-rsb-pins { 1104 pins = "PL0", "PL1"; 1105 function = "s_rsb"; 1106 }; 1107 }; 1108 1109 r_rsb: rsb@1f03400 { 1110 compatible = "allwinner,sun8i-a23-rsb"; 1111 reg = <0x01f03400 0x400>; 1112 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&r_ccu 6>; 1114 clock-frequency = <3000000>; 1115 resets = <&r_ccu 2>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&r_rsb_pins>; 1118 status = "disabled"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 }; 1122 1123 wdt0: watchdog@1c20ca0 { 1124 compatible = "allwinner,sun50i-a64-wdt", 1125 "allwinner,sun6i-a31-wdt"; 1126 reg = <0x01c20ca0 0x20>; 1127 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1128 }; 1129 }; 1130}; 1131