1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun50i-a64-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <3>; 83 enable-method = "psci"; 84 }; 85 }; 86 87 osc24M: osc24M_clk { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-output-names = "osc32k"; 99 }; 100 101 psci { 102 compatible = "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 110 <GIC_PPI 14 111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 112 <GIC_PPI 11 113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 114 <GIC_PPI 10 115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 usb_otg: usb@01c19000 { 125 compatible = "allwinner,sun8i-a33-musb"; 126 reg = <0x01c19000 0x0400>; 127 clocks = <&ccu CLK_BUS_OTG>; 128 resets = <&ccu RST_BUS_OTG>; 129 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 130 interrupt-names = "mc"; 131 phys = <&usbphy 0>; 132 phy-names = "usb"; 133 extcon = <&usbphy 0>; 134 status = "disabled"; 135 }; 136 137 usbphy: phy@01c19400 { 138 compatible = "allwinner,sun50i-a64-usb-phy"; 139 reg = <0x01c19400 0x14>, 140 <0x01c1b800 0x4>; 141 reg-names = "phy_ctrl", 142 "pmu1"; 143 clocks = <&ccu CLK_USB_PHY0>, 144 <&ccu CLK_USB_PHY1>; 145 clock-names = "usb0_phy", 146 "usb1_phy"; 147 resets = <&ccu RST_USB_PHY0>, 148 <&ccu RST_USB_PHY1>; 149 reset-names = "usb0_reset", 150 "usb1_reset"; 151 status = "disabled"; 152 #phy-cells = <1>; 153 }; 154 155 ehci1: usb@01c1b000 { 156 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 157 reg = <0x01c1b000 0x100>; 158 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&ccu CLK_BUS_OHCI1>, 160 <&ccu CLK_BUS_EHCI1>, 161 <&ccu CLK_USB_OHCI1>; 162 resets = <&ccu RST_BUS_OHCI1>, 163 <&ccu RST_BUS_EHCI1>; 164 phys = <&usbphy 1>; 165 phy-names = "usb"; 166 status = "disabled"; 167 }; 168 169 ohci1: usb@01c1b400 { 170 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 171 reg = <0x01c1b400 0x100>; 172 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&ccu CLK_BUS_OHCI1>, 174 <&ccu CLK_USB_OHCI1>; 175 resets = <&ccu RST_BUS_OHCI1>; 176 phys = <&usbphy 1>; 177 phy-names = "usb"; 178 status = "disabled"; 179 }; 180 181 ccu: clock@01c20000 { 182 compatible = "allwinner,sun50i-a64-ccu"; 183 reg = <0x01c20000 0x400>; 184 clocks = <&osc24M>, <&osc32k>; 185 clock-names = "hosc", "losc"; 186 #clock-cells = <1>; 187 #reset-cells = <1>; 188 }; 189 190 pio: pinctrl@1c20800 { 191 compatible = "allwinner,sun50i-a64-pinctrl"; 192 reg = <0x01c20800 0x400>; 193 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&ccu 58>; 197 gpio-controller; 198 #gpio-cells = <3>; 199 interrupt-controller; 200 #interrupt-cells = <3>; 201 202 i2c1_pins: i2c1_pins { 203 pins = "PH2", "PH3"; 204 function = "i2c1"; 205 }; 206 207 uart0_pins_a: uart0@0 { 208 pins = "PB8", "PB9"; 209 function = "uart0"; 210 }; 211 }; 212 213 uart0: serial@1c28000 { 214 compatible = "snps,dw-apb-uart"; 215 reg = <0x01c28000 0x400>; 216 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 217 reg-shift = <2>; 218 reg-io-width = <4>; 219 clocks = <&ccu 67>; 220 resets = <&ccu 46>; 221 status = "disabled"; 222 }; 223 224 uart1: serial@1c28400 { 225 compatible = "snps,dw-apb-uart"; 226 reg = <0x01c28400 0x400>; 227 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 228 reg-shift = <2>; 229 reg-io-width = <4>; 230 clocks = <&ccu 68>; 231 resets = <&ccu 47>; 232 status = "disabled"; 233 }; 234 235 uart2: serial@1c28800 { 236 compatible = "snps,dw-apb-uart"; 237 reg = <0x01c28800 0x400>; 238 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 239 reg-shift = <2>; 240 reg-io-width = <4>; 241 clocks = <&ccu 69>; 242 resets = <&ccu 48>; 243 status = "disabled"; 244 }; 245 246 uart3: serial@1c28c00 { 247 compatible = "snps,dw-apb-uart"; 248 reg = <0x01c28c00 0x400>; 249 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 250 reg-shift = <2>; 251 reg-io-width = <4>; 252 clocks = <&ccu 70>; 253 resets = <&ccu 49>; 254 status = "disabled"; 255 }; 256 257 uart4: serial@1c29000 { 258 compatible = "snps,dw-apb-uart"; 259 reg = <0x01c29000 0x400>; 260 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 261 reg-shift = <2>; 262 reg-io-width = <4>; 263 clocks = <&ccu 71>; 264 resets = <&ccu 50>; 265 status = "disabled"; 266 }; 267 268 i2c0: i2c@1c2ac00 { 269 compatible = "allwinner,sun6i-a31-i2c"; 270 reg = <0x01c2ac00 0x400>; 271 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&ccu 63>; 273 resets = <&ccu 42>; 274 status = "disabled"; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 }; 278 279 i2c1: i2c@1c2b000 { 280 compatible = "allwinner,sun6i-a31-i2c"; 281 reg = <0x01c2b000 0x400>; 282 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&ccu 64>; 284 resets = <&ccu 43>; 285 status = "disabled"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 }; 289 290 i2c2: i2c@1c2b400 { 291 compatible = "allwinner,sun6i-a31-i2c"; 292 reg = <0x01c2b400 0x400>; 293 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&ccu 65>; 295 resets = <&ccu 44>; 296 status = "disabled"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 }; 300 301 gic: interrupt-controller@1c81000 { 302 compatible = "arm,gic-400"; 303 reg = <0x01c81000 0x1000>, 304 <0x01c82000 0x2000>, 305 <0x01c84000 0x2000>, 306 <0x01c86000 0x2000>; 307 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 308 interrupt-controller; 309 #interrupt-cells = <3>; 310 }; 311 312 rtc: rtc@1f00000 { 313 compatible = "allwinner,sun6i-a31-rtc"; 314 reg = <0x01f00000 0x54>; 315 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 }; 319}; 320