1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-r-ccu.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/reset/sun50i-a64-ccu.h> 49 50/ { 51 interrupt-parent = <&gic>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 device_type = "cpu"; 62 reg = <0>; 63 enable-method = "psci"; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <1>; 70 enable-method = "psci"; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53", "arm,armv8"; 75 device_type = "cpu"; 76 reg = <2>; 77 enable-method = "psci"; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <3>; 84 enable-method = "psci"; 85 }; 86 }; 87 88 osc24M: osc24M_clk { 89 #clock-cells = <0>; 90 compatible = "fixed-clock"; 91 clock-frequency = <24000000>; 92 clock-output-names = "osc24M"; 93 }; 94 95 osc32k: osc32k_clk { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <32768>; 99 clock-output-names = "osc32k"; 100 }; 101 102 iosc: internal-osc-clk { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 clock-frequency = <16000000>; 106 clock-accuracy = <300000000>; 107 clock-output-names = "iosc"; 108 }; 109 110 psci { 111 compatible = "arm,psci-0.2"; 112 method = "smc"; 113 }; 114 115 timer { 116 compatible = "arm,armv8-timer"; 117 interrupts = <GIC_PPI 13 118 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 119 <GIC_PPI 14 120 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 121 <GIC_PPI 11 122 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 123 <GIC_PPI 10 124 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 mmc0: mmc@1c0f000 { 134 compatible = "allwinner,sun50i-a64-mmc"; 135 reg = <0x01c0f000 0x1000>; 136 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 137 clock-names = "ahb", "mmc"; 138 resets = <&ccu RST_BUS_MMC0>; 139 reset-names = "ahb"; 140 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 141 max-frequency = <150000000>; 142 status = "disabled"; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 }; 146 147 mmc1: mmc@1c10000 { 148 compatible = "allwinner,sun50i-a64-mmc"; 149 reg = <0x01c10000 0x1000>; 150 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 151 clock-names = "ahb", "mmc"; 152 resets = <&ccu RST_BUS_MMC1>; 153 reset-names = "ahb"; 154 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 155 max-frequency = <150000000>; 156 status = "disabled"; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 }; 160 161 mmc2: mmc@1c11000 { 162 compatible = "allwinner,sun50i-a64-emmc"; 163 reg = <0x01c11000 0x1000>; 164 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 165 clock-names = "ahb", "mmc"; 166 resets = <&ccu RST_BUS_MMC2>; 167 reset-names = "ahb"; 168 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 169 max-frequency = <200000000>; 170 status = "disabled"; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 }; 174 175 usb_otg: usb@01c19000 { 176 compatible = "allwinner,sun8i-a33-musb"; 177 reg = <0x01c19000 0x0400>; 178 clocks = <&ccu CLK_BUS_OTG>; 179 resets = <&ccu RST_BUS_OTG>; 180 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "mc"; 182 phys = <&usbphy 0>; 183 phy-names = "usb"; 184 extcon = <&usbphy 0>; 185 status = "disabled"; 186 }; 187 188 usbphy: phy@01c19400 { 189 compatible = "allwinner,sun50i-a64-usb-phy"; 190 reg = <0x01c19400 0x14>, 191 <0x01c1a800 0x4>, 192 <0x01c1b800 0x4>; 193 reg-names = "phy_ctrl", 194 "pmu0", 195 "pmu1"; 196 clocks = <&ccu CLK_USB_PHY0>, 197 <&ccu CLK_USB_PHY1>; 198 clock-names = "usb0_phy", 199 "usb1_phy"; 200 resets = <&ccu RST_USB_PHY0>, 201 <&ccu RST_USB_PHY1>; 202 reset-names = "usb0_reset", 203 "usb1_reset"; 204 status = "disabled"; 205 #phy-cells = <1>; 206 }; 207 208 ehci0: usb@01c1a000 { 209 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 210 reg = <0x01c1a000 0x100>; 211 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&ccu CLK_BUS_OHCI0>, 213 <&ccu CLK_BUS_EHCI0>, 214 <&ccu CLK_USB_OHCI0>; 215 resets = <&ccu RST_BUS_OHCI0>, 216 <&ccu RST_BUS_EHCI0>; 217 status = "disabled"; 218 }; 219 220 ohci0: usb@01c1a400 { 221 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 222 reg = <0x01c1a400 0x100>; 223 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&ccu CLK_BUS_OHCI0>, 225 <&ccu CLK_USB_OHCI0>; 226 resets = <&ccu RST_BUS_OHCI0>; 227 status = "disabled"; 228 }; 229 230 ehci1: usb@01c1b000 { 231 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 232 reg = <0x01c1b000 0x100>; 233 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&ccu CLK_BUS_OHCI1>, 235 <&ccu CLK_BUS_EHCI1>, 236 <&ccu CLK_USB_OHCI1>; 237 resets = <&ccu RST_BUS_OHCI1>, 238 <&ccu RST_BUS_EHCI1>; 239 phys = <&usbphy 1>; 240 phy-names = "usb"; 241 status = "disabled"; 242 }; 243 244 ohci1: usb@01c1b400 { 245 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 246 reg = <0x01c1b400 0x100>; 247 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&ccu CLK_BUS_OHCI1>, 249 <&ccu CLK_USB_OHCI1>; 250 resets = <&ccu RST_BUS_OHCI1>; 251 phys = <&usbphy 1>; 252 phy-names = "usb"; 253 status = "disabled"; 254 }; 255 256 ccu: clock@01c20000 { 257 compatible = "allwinner,sun50i-a64-ccu"; 258 reg = <0x01c20000 0x400>; 259 clocks = <&osc24M>, <&osc32k>; 260 clock-names = "hosc", "losc"; 261 #clock-cells = <1>; 262 #reset-cells = <1>; 263 }; 264 265 pio: pinctrl@1c20800 { 266 compatible = "allwinner,sun50i-a64-pinctrl"; 267 reg = <0x01c20800 0x400>; 268 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&ccu 58>; 272 gpio-controller; 273 #gpio-cells = <3>; 274 interrupt-controller; 275 #interrupt-cells = <3>; 276 277 i2c1_pins: i2c1_pins { 278 pins = "PH2", "PH3"; 279 function = "i2c1"; 280 }; 281 282 mmc0_pins: mmc0-pins { 283 pins = "PF0", "PF1", "PF2", "PF3", 284 "PF4", "PF5"; 285 function = "mmc0"; 286 drive-strength = <30>; 287 bias-pull-up; 288 }; 289 290 mmc1_pins: mmc1-pins { 291 pins = "PG0", "PG1", "PG2", "PG3", 292 "PG4", "PG5"; 293 function = "mmc1"; 294 drive-strength = <30>; 295 bias-pull-up; 296 }; 297 298 mmc2_pins: mmc2-pins { 299 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 300 "PC10","PC11", "PC12", "PC13", 301 "PC14", "PC15", "PC16"; 302 function = "mmc2"; 303 drive-strength = <30>; 304 bias-pull-up; 305 }; 306 307 uart0_pins_a: uart0@0 { 308 pins = "PB8", "PB9"; 309 function = "uart0"; 310 }; 311 312 uart1_pins: uart1_pins { 313 pins = "PG6", "PG7"; 314 function = "uart1"; 315 }; 316 317 uart1_rts_cts_pins: uart1_rts_cts_pins { 318 pins = "PG8", "PG9"; 319 function = "uart1"; 320 }; 321 322 uart2_pins: uart2-pins { 323 pins = "PB0", "PB1"; 324 function = "uart2"; 325 }; 326 327 uart3_pins: uart3-pins { 328 pins = "PD0", "PD1"; 329 function = "uart3"; 330 }; 331 332 uart4_pins: uart4-pins { 333 pins = "PD2", "PD3"; 334 function = "uart4"; 335 }; 336 337 uart4_rts_cts_pins: uart4-rts-cts-pins { 338 pins = "PD4", "PD5"; 339 function = "uart4"; 340 }; 341 }; 342 343 uart0: serial@1c28000 { 344 compatible = "snps,dw-apb-uart"; 345 reg = <0x01c28000 0x400>; 346 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 347 reg-shift = <2>; 348 reg-io-width = <4>; 349 clocks = <&ccu CLK_BUS_UART0>; 350 resets = <&ccu RST_BUS_UART0>; 351 status = "disabled"; 352 }; 353 354 uart1: serial@1c28400 { 355 compatible = "snps,dw-apb-uart"; 356 reg = <0x01c28400 0x400>; 357 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 358 reg-shift = <2>; 359 reg-io-width = <4>; 360 clocks = <&ccu CLK_BUS_UART1>; 361 resets = <&ccu RST_BUS_UART1>; 362 status = "disabled"; 363 }; 364 365 uart2: serial@1c28800 { 366 compatible = "snps,dw-apb-uart"; 367 reg = <0x01c28800 0x400>; 368 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 369 reg-shift = <2>; 370 reg-io-width = <4>; 371 clocks = <&ccu CLK_BUS_UART2>; 372 resets = <&ccu RST_BUS_UART2>; 373 status = "disabled"; 374 }; 375 376 uart3: serial@1c28c00 { 377 compatible = "snps,dw-apb-uart"; 378 reg = <0x01c28c00 0x400>; 379 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 clocks = <&ccu CLK_BUS_UART3>; 383 resets = <&ccu RST_BUS_UART3>; 384 status = "disabled"; 385 }; 386 387 uart4: serial@1c29000 { 388 compatible = "snps,dw-apb-uart"; 389 reg = <0x01c29000 0x400>; 390 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 391 reg-shift = <2>; 392 reg-io-width = <4>; 393 clocks = <&ccu CLK_BUS_UART4>; 394 resets = <&ccu RST_BUS_UART4>; 395 status = "disabled"; 396 }; 397 398 i2c0: i2c@1c2ac00 { 399 compatible = "allwinner,sun6i-a31-i2c"; 400 reg = <0x01c2ac00 0x400>; 401 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&ccu CLK_BUS_I2C0>; 403 resets = <&ccu RST_BUS_I2C0>; 404 status = "disabled"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 409 i2c1: i2c@1c2b000 { 410 compatible = "allwinner,sun6i-a31-i2c"; 411 reg = <0x01c2b000 0x400>; 412 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&ccu CLK_BUS_I2C1>; 414 resets = <&ccu RST_BUS_I2C1>; 415 status = "disabled"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 }; 419 420 i2c2: i2c@1c2b400 { 421 compatible = "allwinner,sun6i-a31-i2c"; 422 reg = <0x01c2b400 0x400>; 423 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&ccu CLK_BUS_I2C2>; 425 resets = <&ccu RST_BUS_I2C2>; 426 status = "disabled"; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 }; 430 431 gic: interrupt-controller@1c81000 { 432 compatible = "arm,gic-400"; 433 reg = <0x01c81000 0x1000>, 434 <0x01c82000 0x2000>, 435 <0x01c84000 0x2000>, 436 <0x01c86000 0x2000>; 437 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 438 interrupt-controller; 439 #interrupt-cells = <3>; 440 }; 441 442 rtc: rtc@1f00000 { 443 compatible = "allwinner,sun6i-a31-rtc"; 444 reg = <0x01f00000 0x54>; 445 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 447 }; 448 449 r_ccu: clock@1f01400 { 450 compatible = "allwinner,sun50i-a64-r-ccu"; 451 reg = <0x01f01400 0x100>; 452 clocks = <&osc24M>, <&osc32k>, <&iosc>; 453 clock-names = "hosc", "losc", "iosc"; 454 #clock-cells = <1>; 455 #reset-cells = <1>; 456 }; 457 458 r_pio: pinctrl@01f02c00 { 459 compatible = "allwinner,sun50i-a64-r-pinctrl"; 460 reg = <0x01f02c00 0x400>; 461 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 463 clock-names = "apb", "hosc", "losc"; 464 gpio-controller; 465 #gpio-cells = <3>; 466 interrupt-controller; 467 #interrupt-cells = <3>; 468 469 r_rsb_pins: rsb@0 { 470 pins = "PL0", "PL1"; 471 function = "s_rsb"; 472 }; 473 }; 474 475 r_rsb: rsb@1f03400 { 476 compatible = "allwinner,sun8i-a23-rsb"; 477 reg = <0x01f03400 0x400>; 478 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&r_ccu 6>; 480 clock-frequency = <3000000>; 481 resets = <&r_ccu 2>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&r_rsb_pins>; 484 status = "disabled"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 }; 488 }; 489}; 490