1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-de2.h>
47#include <dt-bindings/clock/sun8i-r-ccu.h>
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include <dt-bindings/reset/sun50i-a64-ccu.h>
50#include <dt-bindings/reset/sun8i-de2.h>
51#include <dt-bindings/reset/sun8i-r-ccu.h>
52
53/ {
54	interrupt-parent = <&gic>;
55	#address-cells = <1>;
56	#size-cells = <1>;
57
58	chosen {
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges;
62
63		simplefb_lcd: framebuffer-lcd {
64			compatible = "allwinner,simple-framebuffer",
65				     "simple-framebuffer";
66			allwinner,pipeline = "mixer0-lcd0";
67			clocks = <&ccu CLK_TCON0>,
68				 <&display_clocks CLK_MIXER0>;
69			status = "disabled";
70		};
71
72		simplefb_hdmi: framebuffer-hdmi {
73			compatible = "allwinner,simple-framebuffer",
74				     "simple-framebuffer";
75			allwinner,pipeline = "mixer1-lcd1-hdmi";
76			clocks = <&display_clocks CLK_MIXER1>,
77				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
78			status = "disabled";
79		};
80	};
81
82	cpus {
83		#address-cells = <1>;
84		#size-cells = <0>;
85
86		cpu0: cpu@0 {
87			compatible = "arm,cortex-a53", "arm,armv8";
88			device_type = "cpu";
89			reg = <0>;
90			enable-method = "psci";
91			next-level-cache = <&L2>;
92		};
93
94		cpu1: cpu@1 {
95			compatible = "arm,cortex-a53", "arm,armv8";
96			device_type = "cpu";
97			reg = <1>;
98			enable-method = "psci";
99			next-level-cache = <&L2>;
100		};
101
102		cpu2: cpu@2 {
103			compatible = "arm,cortex-a53", "arm,armv8";
104			device_type = "cpu";
105			reg = <2>;
106			enable-method = "psci";
107			next-level-cache = <&L2>;
108		};
109
110		cpu3: cpu@3 {
111			compatible = "arm,cortex-a53", "arm,armv8";
112			device_type = "cpu";
113			reg = <3>;
114			enable-method = "psci";
115			next-level-cache = <&L2>;
116		};
117
118		L2: l2-cache {
119			compatible = "cache";
120			cache-level = <2>;
121		};
122	};
123
124	de: display-engine {
125		compatible = "allwinner,sun50i-a64-display-engine";
126		allwinner,pipelines = <&mixer0>,
127				      <&mixer1>;
128		status = "disabled";
129	};
130
131	osc24M: osc24M_clk {
132		#clock-cells = <0>;
133		compatible = "fixed-clock";
134		clock-frequency = <24000000>;
135		clock-output-names = "osc24M";
136	};
137
138	osc32k: osc32k_clk {
139		#clock-cells = <0>;
140		compatible = "fixed-clock";
141		clock-frequency = <32768>;
142		clock-output-names = "ext-osc32k";
143	};
144
145	psci {
146		compatible = "arm,psci-0.2";
147		method = "smc";
148	};
149
150	sound: sound {
151		compatible = "simple-audio-card";
152		simple-audio-card,name = "sun50i-a64-audio";
153		simple-audio-card,format = "i2s";
154		simple-audio-card,frame-master = <&cpudai>;
155		simple-audio-card,bitclock-master = <&cpudai>;
156		simple-audio-card,mclk-fs = <128>;
157		simple-audio-card,aux-devs = <&codec_analog>;
158		simple-audio-card,routing =
159				"Left DAC", "AIF1 Slot 0 Left",
160				"Right DAC", "AIF1 Slot 0 Right",
161				"AIF1 Slot 0 Left ADC", "Left ADC",
162				"AIF1 Slot 0 Right ADC", "Right ADC";
163		status = "disabled";
164
165		cpudai: simple-audio-card,cpu {
166			sound-dai = <&dai>;
167		};
168
169		link_codec: simple-audio-card,codec {
170			sound-dai = <&codec>;
171		};
172	};
173
174	sound_spdif {
175		compatible = "simple-audio-card";
176		simple-audio-card,name = "On-board SPDIF";
177
178		simple-audio-card,cpu {
179			sound-dai = <&spdif>;
180		};
181
182		simple-audio-card,codec {
183			sound-dai = <&spdif_out>;
184		};
185	};
186
187	spdif_out: spdif-out {
188		#sound-dai-cells = <0>;
189		compatible = "linux,spdif-dit";
190	};
191
192	timer {
193		compatible = "arm,armv8-timer";
194		interrupts = <GIC_PPI 13
195			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
196			     <GIC_PPI 14
197			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
198			     <GIC_PPI 11
199			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
200			     <GIC_PPI 10
201			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
202	};
203
204	soc {
205		compatible = "simple-bus";
206		#address-cells = <1>;
207		#size-cells = <1>;
208		ranges;
209
210		de2@1000000 {
211			compatible = "allwinner,sun50i-a64-de2";
212			reg = <0x1000000 0x400000>;
213			allwinner,sram = <&de2_sram 1>;
214			#address-cells = <1>;
215			#size-cells = <1>;
216			ranges = <0 0x1000000 0x400000>;
217
218			display_clocks: clock@0 {
219				compatible = "allwinner,sun50i-a64-de2-clk";
220				reg = <0x0 0x100000>;
221				clocks = <&ccu CLK_DE>,
222					 <&ccu CLK_BUS_DE>;
223				clock-names = "mod",
224					      "bus";
225				resets = <&ccu RST_BUS_DE>;
226				#clock-cells = <1>;
227				#reset-cells = <1>;
228			};
229
230			mixer0: mixer@100000 {
231				compatible = "allwinner,sun50i-a64-de2-mixer-0";
232				reg = <0x100000 0x100000>;
233				clocks = <&display_clocks CLK_BUS_MIXER0>,
234					 <&display_clocks CLK_MIXER0>;
235				clock-names = "bus",
236					      "mod";
237				resets = <&display_clocks RST_MIXER0>;
238
239				ports {
240					#address-cells = <1>;
241					#size-cells = <0>;
242
243					mixer0_out: port@1 {
244						reg = <1>;
245
246						mixer0_out_tcon0: endpoint {
247							remote-endpoint = <&tcon0_in_mixer0>;
248						};
249					};
250				};
251			};
252
253			mixer1: mixer@200000 {
254				compatible = "allwinner,sun50i-a64-de2-mixer-1";
255				reg = <0x200000 0x100000>;
256				clocks = <&display_clocks CLK_BUS_MIXER1>,
257					 <&display_clocks CLK_MIXER1>;
258				clock-names = "bus",
259					      "mod";
260				resets = <&display_clocks RST_MIXER1>;
261
262				ports {
263					#address-cells = <1>;
264					#size-cells = <0>;
265
266					mixer1_out: port@1 {
267						reg = <1>;
268
269						mixer1_out_tcon1: endpoint {
270							remote-endpoint = <&tcon1_in_mixer1>;
271						};
272					};
273				};
274			};
275		};
276
277		syscon: syscon@1c00000 {
278			compatible = "allwinner,sun50i-a64-system-control";
279			reg = <0x01c00000 0x1000>;
280			#address-cells = <1>;
281			#size-cells = <1>;
282			ranges;
283
284			sram_c: sram@18000 {
285				compatible = "mmio-sram";
286				reg = <0x00018000 0x28000>;
287				#address-cells = <1>;
288				#size-cells = <1>;
289				ranges = <0 0x00018000 0x28000>;
290
291				de2_sram: sram-section@0 {
292					compatible = "allwinner,sun50i-a64-sram-c";
293					reg = <0x0000 0x28000>;
294				};
295			};
296
297			sram_c1: sram@1d00000 {
298				compatible = "mmio-sram";
299				reg = <0x01d00000 0x40000>;
300				#address-cells = <1>;
301				#size-cells = <1>;
302				ranges = <0 0x01d00000 0x40000>;
303
304				ve_sram: sram-section@0 {
305					compatible = "allwinner,sun50i-a64-sram-c1",
306						     "allwinner,sun4i-a10-sram-c1";
307					reg = <0x000000 0x40000>;
308				};
309			};
310		};
311
312		dma: dma-controller@1c02000 {
313			compatible = "allwinner,sun50i-a64-dma";
314			reg = <0x01c02000 0x1000>;
315			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
316			clocks = <&ccu CLK_BUS_DMA>;
317			dma-channels = <8>;
318			dma-requests = <27>;
319			resets = <&ccu RST_BUS_DMA>;
320			#dma-cells = <1>;
321		};
322
323		tcon0: lcd-controller@1c0c000 {
324			compatible = "allwinner,sun50i-a64-tcon-lcd",
325				     "allwinner,sun8i-a83t-tcon-lcd";
326			reg = <0x01c0c000 0x1000>;
327			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
328			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
329			clock-names = "ahb", "tcon-ch0";
330			clock-output-names = "tcon-pixel-clock";
331			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
332			reset-names = "lcd", "lvds";
333
334			ports {
335				#address-cells = <1>;
336				#size-cells = <0>;
337
338				tcon0_in: port@0 {
339					#address-cells = <1>;
340					#size-cells = <0>;
341					reg = <0>;
342
343					tcon0_in_mixer0: endpoint@0 {
344						reg = <0>;
345						remote-endpoint = <&mixer0_out_tcon0>;
346					};
347				};
348
349				tcon0_out: port@1 {
350					#address-cells = <1>;
351					#size-cells = <0>;
352					reg = <1>;
353				};
354			};
355		};
356
357		tcon1: lcd-controller@1c0d000 {
358			compatible = "allwinner,sun50i-a64-tcon-tv",
359				     "allwinner,sun8i-a83t-tcon-tv";
360			reg = <0x01c0d000 0x1000>;
361			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
362			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
363			clock-names = "ahb", "tcon-ch1";
364			resets = <&ccu RST_BUS_TCON1>;
365			reset-names = "lcd";
366
367			ports {
368				#address-cells = <1>;
369				#size-cells = <0>;
370
371				tcon1_in: port@0 {
372					reg = <0>;
373
374					tcon1_in_mixer1: endpoint {
375						remote-endpoint = <&mixer1_out_tcon1>;
376					};
377				};
378
379				tcon1_out: port@1 {
380					#address-cells = <1>;
381					#size-cells = <0>;
382					reg = <1>;
383
384					tcon1_out_hdmi: endpoint@1 {
385						reg = <1>;
386						remote-endpoint = <&hdmi_in_tcon1>;
387					};
388				};
389			};
390		};
391
392		video-codec@1c0e000 {
393			compatible = "allwinner,sun50i-h5-video-engine";
394			reg = <0x01c0e000 0x1000>;
395			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
396				 <&ccu CLK_DRAM_VE>;
397			clock-names = "ahb", "mod", "ram";
398			resets = <&ccu RST_BUS_VE>;
399			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
400			allwinner,sram = <&ve_sram 1>;
401		};
402
403		mmc0: mmc@1c0f000 {
404			compatible = "allwinner,sun50i-a64-mmc";
405			reg = <0x01c0f000 0x1000>;
406			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
407			clock-names = "ahb", "mmc";
408			resets = <&ccu RST_BUS_MMC0>;
409			reset-names = "ahb";
410			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
411			max-frequency = <150000000>;
412			status = "disabled";
413			#address-cells = <1>;
414			#size-cells = <0>;
415		};
416
417		mmc1: mmc@1c10000 {
418			compatible = "allwinner,sun50i-a64-mmc";
419			reg = <0x01c10000 0x1000>;
420			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
421			clock-names = "ahb", "mmc";
422			resets = <&ccu RST_BUS_MMC1>;
423			reset-names = "ahb";
424			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
425			max-frequency = <150000000>;
426			status = "disabled";
427			#address-cells = <1>;
428			#size-cells = <0>;
429		};
430
431		mmc2: mmc@1c11000 {
432			compatible = "allwinner,sun50i-a64-emmc";
433			reg = <0x01c11000 0x1000>;
434			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
435			clock-names = "ahb", "mmc";
436			resets = <&ccu RST_BUS_MMC2>;
437			reset-names = "ahb";
438			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
439			max-frequency = <200000000>;
440			status = "disabled";
441			#address-cells = <1>;
442			#size-cells = <0>;
443		};
444
445		sid: eeprom@1c14000 {
446			compatible = "allwinner,sun50i-a64-sid";
447			reg = <0x1c14000 0x400>;
448		};
449
450		usb_otg: usb@1c19000 {
451			compatible = "allwinner,sun8i-a33-musb";
452			reg = <0x01c19000 0x0400>;
453			clocks = <&ccu CLK_BUS_OTG>;
454			resets = <&ccu RST_BUS_OTG>;
455			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
456			interrupt-names = "mc";
457			phys = <&usbphy 0>;
458			phy-names = "usb";
459			extcon = <&usbphy 0>;
460			status = "disabled";
461		};
462
463		usbphy: phy@1c19400 {
464			compatible = "allwinner,sun50i-a64-usb-phy";
465			reg = <0x01c19400 0x14>,
466			      <0x01c1a800 0x4>,
467			      <0x01c1b800 0x4>;
468			reg-names = "phy_ctrl",
469				    "pmu0",
470				    "pmu1";
471			clocks = <&ccu CLK_USB_PHY0>,
472				 <&ccu CLK_USB_PHY1>;
473			clock-names = "usb0_phy",
474				      "usb1_phy";
475			resets = <&ccu RST_USB_PHY0>,
476				 <&ccu RST_USB_PHY1>;
477			reset-names = "usb0_reset",
478				      "usb1_reset";
479			status = "disabled";
480			#phy-cells = <1>;
481		};
482
483		ehci0: usb@1c1a000 {
484			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
485			reg = <0x01c1a000 0x100>;
486			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
487			clocks = <&ccu CLK_BUS_OHCI0>,
488				 <&ccu CLK_BUS_EHCI0>,
489				 <&ccu CLK_USB_OHCI0>;
490			resets = <&ccu RST_BUS_OHCI0>,
491				 <&ccu RST_BUS_EHCI0>;
492			status = "disabled";
493		};
494
495		ohci0: usb@1c1a400 {
496			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
497			reg = <0x01c1a400 0x100>;
498			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
499			clocks = <&ccu CLK_BUS_OHCI0>,
500				 <&ccu CLK_USB_OHCI0>;
501			resets = <&ccu RST_BUS_OHCI0>;
502			status = "disabled";
503		};
504
505		ehci1: usb@1c1b000 {
506			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
507			reg = <0x01c1b000 0x100>;
508			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
509			clocks = <&ccu CLK_BUS_OHCI1>,
510				 <&ccu CLK_BUS_EHCI1>,
511				 <&ccu CLK_USB_OHCI1>;
512			resets = <&ccu RST_BUS_OHCI1>,
513				 <&ccu RST_BUS_EHCI1>;
514			phys = <&usbphy 1>;
515			phy-names = "usb";
516			status = "disabled";
517		};
518
519		ohci1: usb@1c1b400 {
520			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
521			reg = <0x01c1b400 0x100>;
522			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
523			clocks = <&ccu CLK_BUS_OHCI1>,
524				 <&ccu CLK_USB_OHCI1>;
525			resets = <&ccu RST_BUS_OHCI1>;
526			phys = <&usbphy 1>;
527			phy-names = "usb";
528			status = "disabled";
529		};
530
531		ccu: clock@1c20000 {
532			compatible = "allwinner,sun50i-a64-ccu";
533			reg = <0x01c20000 0x400>;
534			clocks = <&osc24M>, <&rtc 0>;
535			clock-names = "hosc", "losc";
536			#clock-cells = <1>;
537			#reset-cells = <1>;
538		};
539
540		pio: pinctrl@1c20800 {
541			compatible = "allwinner,sun50i-a64-pinctrl";
542			reg = <0x01c20800 0x400>;
543			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
544				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
545				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
546			clocks = <&ccu 58>;
547			gpio-controller;
548			#gpio-cells = <3>;
549			interrupt-controller;
550			#interrupt-cells = <3>;
551
552			i2c0_pins: i2c0_pins {
553				pins = "PH0", "PH1";
554				function = "i2c0";
555			};
556
557			i2c1_pins: i2c1_pins {
558				pins = "PH2", "PH3";
559				function = "i2c1";
560			};
561
562			mmc0_pins: mmc0-pins {
563				pins = "PF0", "PF1", "PF2", "PF3",
564				       "PF4", "PF5";
565				function = "mmc0";
566				drive-strength = <30>;
567				bias-pull-up;
568			};
569
570			mmc1_pins: mmc1-pins {
571				pins = "PG0", "PG1", "PG2", "PG3",
572				       "PG4", "PG5";
573				function = "mmc1";
574				drive-strength = <30>;
575				bias-pull-up;
576			};
577
578			mmc2_pins: mmc2-pins {
579				pins = "PC5", "PC6", "PC8", "PC9",
580				       "PC10","PC11", "PC12", "PC13",
581				       "PC14", "PC15", "PC16";
582				function = "mmc2";
583				drive-strength = <30>;
584				bias-pull-up;
585			};
586
587			mmc2_ds_pin: mmc2-ds-pin {
588				pins = "PC1";
589				function = "mmc2";
590				drive-strength = <30>;
591				bias-pull-up;
592			};
593
594			pwm_pin: pwm_pin {
595				pins = "PD22";
596				function = "pwm";
597			};
598
599			rmii_pins: rmii_pins {
600				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
601				       "PD18", "PD19", "PD20", "PD22", "PD23";
602				function = "emac";
603				drive-strength = <40>;
604			};
605
606			rgmii_pins: rgmii_pins {
607				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
608				       "PD13", "PD15", "PD16", "PD17", "PD18",
609				       "PD19", "PD20", "PD21", "PD22", "PD23";
610				function = "emac";
611				drive-strength = <40>;
612			};
613
614			spdif_tx_pin: spdif {
615				pins = "PH8";
616				function = "spdif";
617			};
618
619			spi0_pins: spi0 {
620				pins = "PC0", "PC1", "PC2", "PC3";
621				function = "spi0";
622			};
623
624			spi1_pins: spi1 {
625				pins = "PD0", "PD1", "PD2", "PD3";
626				function = "spi1";
627			};
628
629			uart0_pb_pins: uart0-pb-pins {
630				pins = "PB8", "PB9";
631				function = "uart0";
632			};
633
634			uart1_pins: uart1_pins {
635				pins = "PG6", "PG7";
636				function = "uart1";
637			};
638
639			uart1_rts_cts_pins: uart1_rts_cts_pins {
640				pins = "PG8", "PG9";
641				function = "uart1";
642			};
643
644			uart2_pins: uart2-pins {
645				pins = "PB0", "PB1";
646				function = "uart2";
647			};
648
649			uart3_pins: uart3-pins {
650				pins = "PD0", "PD1";
651				function = "uart3";
652			};
653
654			uart4_pins: uart4-pins {
655				pins = "PD2", "PD3";
656				function = "uart4";
657			};
658
659			uart4_rts_cts_pins: uart4-rts-cts-pins {
660				pins = "PD4", "PD5";
661				function = "uart4";
662			};
663		};
664
665		spdif: spdif@1c21000 {
666			#sound-dai-cells = <0>;
667			compatible = "allwinner,sun50i-a64-spdif",
668				     "allwinner,sun8i-h3-spdif";
669			reg = <0x01c21000 0x400>;
670			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
671			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
672			resets = <&ccu RST_BUS_SPDIF>;
673			clock-names = "apb", "spdif";
674			dmas = <&dma 2>;
675			dma-names = "tx";
676			pinctrl-names = "default";
677			pinctrl-0 = <&spdif_tx_pin>;
678			status = "disabled";
679		};
680
681		i2s0: i2s@1c22000 {
682			#sound-dai-cells = <0>;
683			compatible = "allwinner,sun50i-a64-i2s",
684				     "allwinner,sun8i-h3-i2s";
685			reg = <0x01c22000 0x400>;
686			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
687			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
688			clock-names = "apb", "mod";
689			resets = <&ccu RST_BUS_I2S0>;
690			dma-names = "rx", "tx";
691			dmas = <&dma 3>, <&dma 3>;
692			status = "disabled";
693		};
694
695		i2s1: i2s@1c22400 {
696			#sound-dai-cells = <0>;
697			compatible = "allwinner,sun50i-a64-i2s",
698				     "allwinner,sun8i-h3-i2s";
699			reg = <0x01c22400 0x400>;
700			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
701			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
702			clock-names = "apb", "mod";
703			resets = <&ccu RST_BUS_I2S1>;
704			dma-names = "rx", "tx";
705			dmas = <&dma 4>, <&dma 4>;
706			status = "disabled";
707		};
708
709		dai: dai@1c22c00 {
710			#sound-dai-cells = <0>;
711			compatible = "allwinner,sun50i-a64-codec-i2s";
712			reg = <0x01c22c00 0x200>;
713			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
714			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
715			clock-names = "apb", "mod";
716			resets = <&ccu RST_BUS_CODEC>;
717			reset-names = "rst";
718			dmas = <&dma 15>, <&dma 15>;
719			dma-names = "rx", "tx";
720			status = "disabled";
721		};
722
723		codec: codec@1c22e00 {
724			#sound-dai-cells = <0>;
725			compatible = "allwinner,sun8i-a33-codec";
726			reg = <0x01c22e00 0x600>;
727			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
728			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
729			clock-names = "bus", "mod";
730			status = "disabled";
731		};
732
733		uart0: serial@1c28000 {
734			compatible = "snps,dw-apb-uart";
735			reg = <0x01c28000 0x400>;
736			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
737			reg-shift = <2>;
738			reg-io-width = <4>;
739			clocks = <&ccu CLK_BUS_UART0>;
740			resets = <&ccu RST_BUS_UART0>;
741			status = "disabled";
742		};
743
744		uart1: serial@1c28400 {
745			compatible = "snps,dw-apb-uart";
746			reg = <0x01c28400 0x400>;
747			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
748			reg-shift = <2>;
749			reg-io-width = <4>;
750			clocks = <&ccu CLK_BUS_UART1>;
751			resets = <&ccu RST_BUS_UART1>;
752			status = "disabled";
753		};
754
755		uart2: serial@1c28800 {
756			compatible = "snps,dw-apb-uart";
757			reg = <0x01c28800 0x400>;
758			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
759			reg-shift = <2>;
760			reg-io-width = <4>;
761			clocks = <&ccu CLK_BUS_UART2>;
762			resets = <&ccu RST_BUS_UART2>;
763			status = "disabled";
764		};
765
766		uart3: serial@1c28c00 {
767			compatible = "snps,dw-apb-uart";
768			reg = <0x01c28c00 0x400>;
769			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
770			reg-shift = <2>;
771			reg-io-width = <4>;
772			clocks = <&ccu CLK_BUS_UART3>;
773			resets = <&ccu RST_BUS_UART3>;
774			status = "disabled";
775		};
776
777		uart4: serial@1c29000 {
778			compatible = "snps,dw-apb-uart";
779			reg = <0x01c29000 0x400>;
780			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
781			reg-shift = <2>;
782			reg-io-width = <4>;
783			clocks = <&ccu CLK_BUS_UART4>;
784			resets = <&ccu RST_BUS_UART4>;
785			status = "disabled";
786		};
787
788		i2c0: i2c@1c2ac00 {
789			compatible = "allwinner,sun6i-a31-i2c";
790			reg = <0x01c2ac00 0x400>;
791			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
792			clocks = <&ccu CLK_BUS_I2C0>;
793			resets = <&ccu RST_BUS_I2C0>;
794			status = "disabled";
795			#address-cells = <1>;
796			#size-cells = <0>;
797		};
798
799		i2c1: i2c@1c2b000 {
800			compatible = "allwinner,sun6i-a31-i2c";
801			reg = <0x01c2b000 0x400>;
802			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
803			clocks = <&ccu CLK_BUS_I2C1>;
804			resets = <&ccu RST_BUS_I2C1>;
805			status = "disabled";
806			#address-cells = <1>;
807			#size-cells = <0>;
808		};
809
810		i2c2: i2c@1c2b400 {
811			compatible = "allwinner,sun6i-a31-i2c";
812			reg = <0x01c2b400 0x400>;
813			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
814			clocks = <&ccu CLK_BUS_I2C2>;
815			resets = <&ccu RST_BUS_I2C2>;
816			status = "disabled";
817			#address-cells = <1>;
818			#size-cells = <0>;
819		};
820
821
822		spi0: spi@1c68000 {
823			compatible = "allwinner,sun8i-h3-spi";
824			reg = <0x01c68000 0x1000>;
825			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
826			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
827			clock-names = "ahb", "mod";
828			dmas = <&dma 23>, <&dma 23>;
829			dma-names = "rx", "tx";
830			pinctrl-names = "default";
831			pinctrl-0 = <&spi0_pins>;
832			resets = <&ccu RST_BUS_SPI0>;
833			status = "disabled";
834			num-cs = <1>;
835			#address-cells = <1>;
836			#size-cells = <0>;
837		};
838
839		spi1: spi@1c69000 {
840			compatible = "allwinner,sun8i-h3-spi";
841			reg = <0x01c69000 0x1000>;
842			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
843			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
844			clock-names = "ahb", "mod";
845			dmas = <&dma 24>, <&dma 24>;
846			dma-names = "rx", "tx";
847			pinctrl-names = "default";
848			pinctrl-0 = <&spi1_pins>;
849			resets = <&ccu RST_BUS_SPI1>;
850			status = "disabled";
851			num-cs = <1>;
852			#address-cells = <1>;
853			#size-cells = <0>;
854		};
855
856		emac: ethernet@1c30000 {
857			compatible = "allwinner,sun50i-a64-emac";
858			syscon = <&syscon>;
859			reg = <0x01c30000 0x10000>;
860			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
861			interrupt-names = "macirq";
862			resets = <&ccu RST_BUS_EMAC>;
863			reset-names = "stmmaceth";
864			clocks = <&ccu CLK_BUS_EMAC>;
865			clock-names = "stmmaceth";
866			status = "disabled";
867
868			mdio: mdio {
869				compatible = "snps,dwmac-mdio";
870				#address-cells = <1>;
871				#size-cells = <0>;
872			};
873		};
874
875		mali: gpu@1c40000 {
876			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
877			reg = <0x01c40000 0x10000>;
878			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
879				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
880				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
881				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
882				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
883				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
884				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
885			interrupt-names = "gp",
886					  "gpmmu",
887					  "pp0",
888					  "ppmmu0",
889					  "pp1",
890					  "ppmmu1",
891					  "pmu";
892			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
893			clock-names = "bus", "core";
894			resets = <&ccu RST_BUS_GPU>;
895		};
896
897		gic: interrupt-controller@1c81000 {
898			compatible = "arm,gic-400";
899			reg = <0x01c81000 0x1000>,
900			      <0x01c82000 0x2000>,
901			      <0x01c84000 0x2000>,
902			      <0x01c86000 0x2000>;
903			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
904			interrupt-controller;
905			#interrupt-cells = <3>;
906		};
907
908		pwm: pwm@1c21400 {
909			compatible = "allwinner,sun50i-a64-pwm",
910				     "allwinner,sun5i-a13-pwm";
911			reg = <0x01c21400 0x400>;
912			clocks = <&osc24M>;
913			pinctrl-names = "default";
914			pinctrl-0 = <&pwm_pin>;
915			#pwm-cells = <3>;
916			status = "disabled";
917		};
918
919		hdmi: hdmi@1ee0000 {
920			compatible = "allwinner,sun50i-a64-dw-hdmi",
921				     "allwinner,sun8i-a83t-dw-hdmi";
922			reg = <0x01ee0000 0x10000>;
923			reg-io-width = <1>;
924			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
925			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
926				 <&ccu CLK_HDMI>;
927			clock-names = "iahb", "isfr", "tmds";
928			resets = <&ccu RST_BUS_HDMI1>;
929			reset-names = "ctrl";
930			phys = <&hdmi_phy>;
931			phy-names = "hdmi-phy";
932			status = "disabled";
933
934			ports {
935				#address-cells = <1>;
936				#size-cells = <0>;
937
938				hdmi_in: port@0 {
939					reg = <0>;
940
941					hdmi_in_tcon1: endpoint {
942						remote-endpoint = <&tcon1_out_hdmi>;
943					};
944				};
945
946				hdmi_out: port@1 {
947					reg = <1>;
948				};
949			};
950		};
951
952		hdmi_phy: hdmi-phy@1ef0000 {
953			compatible = "allwinner,sun50i-a64-hdmi-phy";
954			reg = <0x01ef0000 0x10000>;
955			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
956				 <&ccu 7>;
957			clock-names = "bus", "mod", "pll-0";
958			resets = <&ccu RST_BUS_HDMI0>;
959			reset-names = "phy";
960			#phy-cells = <0>;
961		};
962
963		rtc: rtc@1f00000 {
964			compatible = "allwinner,sun50i-a64-rtc",
965				     "allwinner,sun8i-h3-rtc";
966			reg = <0x01f00000 0x400>;
967			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
969			clock-output-names = "osc32k", "osc32k-out", "iosc";
970			clocks = <&osc32k>;
971			#clock-cells = <1>;
972		};
973
974		r_intc: interrupt-controller@1f00c00 {
975			compatible = "allwinner,sun50i-a64-r-intc",
976				     "allwinner,sun6i-a31-r-intc";
977			interrupt-controller;
978			#interrupt-cells = <2>;
979			reg = <0x01f00c00 0x400>;
980			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
981		};
982
983		r_ccu: clock@1f01400 {
984			compatible = "allwinner,sun50i-a64-r-ccu";
985			reg = <0x01f01400 0x100>;
986			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>;
987			clock-names = "hosc", "losc", "iosc", "pll-periph";
988			#clock-cells = <1>;
989			#reset-cells = <1>;
990		};
991
992		codec_analog: codec-analog@1f015c0 {
993			compatible = "allwinner,sun50i-a64-codec-analog";
994			reg = <0x01f015c0 0x4>;
995			status = "disabled";
996		};
997
998		r_i2c: i2c@1f02400 {
999			compatible = "allwinner,sun50i-a64-i2c",
1000				     "allwinner,sun6i-a31-i2c";
1001			reg = <0x01f02400 0x400>;
1002			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1003			clocks = <&r_ccu CLK_APB0_I2C>;
1004			resets = <&r_ccu RST_APB0_I2C>;
1005			status = "disabled";
1006			#address-cells = <1>;
1007			#size-cells = <0>;
1008		};
1009
1010		r_pwm: pwm@1f03800 {
1011			compatible = "allwinner,sun50i-a64-pwm",
1012				     "allwinner,sun5i-a13-pwm";
1013			reg = <0x01f03800 0x400>;
1014			clocks = <&osc24M>;
1015			pinctrl-names = "default";
1016			pinctrl-0 = <&r_pwm_pin>;
1017			#pwm-cells = <3>;
1018			status = "disabled";
1019		};
1020
1021		r_pio: pinctrl@1f02c00 {
1022			compatible = "allwinner,sun50i-a64-r-pinctrl";
1023			reg = <0x01f02c00 0x400>;
1024			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1025			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1026			clock-names = "apb", "hosc", "losc";
1027			gpio-controller;
1028			#gpio-cells = <3>;
1029			interrupt-controller;
1030			#interrupt-cells = <3>;
1031
1032			r_i2c_pl89_pins: r-i2c-pl89-pins {
1033				pins = "PL8", "PL9";
1034				function = "s_i2c";
1035			};
1036
1037			r_pwm_pin: pwm {
1038				pins = "PL10";
1039				function = "s_pwm";
1040			};
1041
1042			r_rsb_pins: rsb {
1043				pins = "PL0", "PL1";
1044				function = "s_rsb";
1045			};
1046		};
1047
1048		r_rsb: rsb@1f03400 {
1049			compatible = "allwinner,sun8i-a23-rsb";
1050			reg = <0x01f03400 0x400>;
1051			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1052			clocks = <&r_ccu 6>;
1053			clock-frequency = <3000000>;
1054			resets = <&r_ccu 2>;
1055			pinctrl-names = "default";
1056			pinctrl-0 = <&r_rsb_pins>;
1057			status = "disabled";
1058			#address-cells = <1>;
1059			#size-cells = <0>;
1060		};
1061
1062		wdt0: watchdog@1c20ca0 {
1063			compatible = "allwinner,sun50i-a64-wdt",
1064				     "allwinner,sun6i-a31-wdt";
1065			reg = <0x01c20ca0 0x20>;
1066			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1067		};
1068	};
1069};
1070