1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2016 ARM Ltd.
3// based on the Allwinner H3 dtsi:
4//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6#include <dt-bindings/clock/sun50i-a64-ccu.h>
7#include <dt-bindings/clock/sun8i-de2.h>
8#include <dt-bindings/clock/sun8i-r-ccu.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/sun50i-a64-ccu.h>
11#include <dt-bindings/reset/sun8i-de2.h>
12#include <dt-bindings/reset/sun8i-r-ccu.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	chosen {
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges;
24
25		simplefb_lcd: framebuffer-lcd {
26			compatible = "allwinner,simple-framebuffer",
27				     "simple-framebuffer";
28			allwinner,pipeline = "mixer0-lcd0";
29			clocks = <&ccu CLK_TCON0>,
30				 <&display_clocks CLK_MIXER0>;
31			status = "disabled";
32		};
33
34		simplefb_hdmi: framebuffer-hdmi {
35			compatible = "allwinner,simple-framebuffer",
36				     "simple-framebuffer";
37			allwinner,pipeline = "mixer1-lcd1-hdmi";
38			clocks = <&display_clocks CLK_MIXER1>,
39				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40			status = "disabled";
41		};
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		cpu0: cpu@0 {
49			compatible = "arm,cortex-a53";
50			device_type = "cpu";
51			reg = <0>;
52			enable-method = "psci";
53			next-level-cache = <&L2>;
54			clocks = <&ccu 21>;
55			clock-names = "cpu";
56			#cooling-cells = <2>;
57		};
58
59		cpu1: cpu@1 {
60			compatible = "arm,cortex-a53";
61			device_type = "cpu";
62			reg = <1>;
63			enable-method = "psci";
64			next-level-cache = <&L2>;
65			clocks = <&ccu 21>;
66			clock-names = "cpu";
67			#cooling-cells = <2>;
68		};
69
70		cpu2: cpu@2 {
71			compatible = "arm,cortex-a53";
72			device_type = "cpu";
73			reg = <2>;
74			enable-method = "psci";
75			next-level-cache = <&L2>;
76			clocks = <&ccu 21>;
77			clock-names = "cpu";
78			#cooling-cells = <2>;
79		};
80
81		cpu3: cpu@3 {
82			compatible = "arm,cortex-a53";
83			device_type = "cpu";
84			reg = <3>;
85			enable-method = "psci";
86			next-level-cache = <&L2>;
87			clocks = <&ccu 21>;
88			clock-names = "cpu";
89			#cooling-cells = <2>;
90		};
91
92		L2: l2-cache {
93			compatible = "cache";
94			cache-level = <2>;
95		};
96	};
97
98	de: display-engine {
99		compatible = "allwinner,sun50i-a64-display-engine";
100		allwinner,pipelines = <&mixer0>,
101				      <&mixer1>;
102		status = "disabled";
103	};
104
105	osc24M: osc24M_clk {
106		#clock-cells = <0>;
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "osc24M";
110	};
111
112	osc32k: osc32k_clk {
113		#clock-cells = <0>;
114		compatible = "fixed-clock";
115		clock-frequency = <32768>;
116		clock-output-names = "ext-osc32k";
117	};
118
119	pmu {
120		compatible = "arm,cortex-a53-pmu";
121		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126	};
127
128	psci {
129		compatible = "arm,psci-0.2";
130		method = "smc";
131	};
132
133	sound: sound {
134		compatible = "simple-audio-card";
135		simple-audio-card,name = "sun50i-a64-audio";
136		simple-audio-card,format = "i2s";
137		simple-audio-card,frame-master = <&cpudai>;
138		simple-audio-card,bitclock-master = <&cpudai>;
139		simple-audio-card,mclk-fs = <128>;
140		simple-audio-card,aux-devs = <&codec_analog>;
141		simple-audio-card,routing =
142				"Left DAC", "AIF1 Slot 0 Left",
143				"Right DAC", "AIF1 Slot 0 Right",
144				"AIF1 Slot 0 Left ADC", "Left ADC",
145				"AIF1 Slot 0 Right ADC", "Right ADC";
146		status = "disabled";
147
148		cpudai: simple-audio-card,cpu {
149			sound-dai = <&dai>;
150		};
151
152		link_codec: simple-audio-card,codec {
153			sound-dai = <&codec>;
154		};
155	};
156
157	sound_spdif {
158		compatible = "simple-audio-card";
159		simple-audio-card,name = "On-board SPDIF";
160
161		simple-audio-card,cpu {
162			sound-dai = <&spdif>;
163		};
164
165		simple-audio-card,codec {
166			sound-dai = <&spdif_out>;
167		};
168	};
169
170	spdif_out: spdif-out {
171		#sound-dai-cells = <0>;
172		compatible = "linux,spdif-dit";
173	};
174
175	timer {
176		compatible = "arm,armv8-timer";
177		allwinner,erratum-unknown1;
178		interrupts = <GIC_PPI 13
179			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
180			     <GIC_PPI 14
181			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
182			     <GIC_PPI 11
183			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
184			     <GIC_PPI 10
185			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
186	};
187
188	thermal-zones {
189		cpu_thermal: cpu0-thermal {
190			/* milliseconds */
191			polling-delay-passive = <0>;
192			polling-delay = <0>;
193			thermal-sensors = <&ths 0>;
194
195			cooling-maps {
196				map0 {
197					trip = <&cpu_alert0>;
198					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
199							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202				};
203				map1 {
204					trip = <&cpu_alert1>;
205					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
209				};
210			};
211
212			trips {
213				cpu_alert0: cpu_alert0 {
214					/* milliCelsius */
215					temperature = <75000>;
216					hysteresis = <2000>;
217					type = "passive";
218				};
219
220				cpu_alert1: cpu_alert1 {
221					/* milliCelsius */
222					temperature = <90000>;
223					hysteresis = <2000>;
224					type = "hot";
225				};
226
227				cpu_crit: cpu_crit {
228					/* milliCelsius */
229					temperature = <110000>;
230					hysteresis = <2000>;
231					type = "critical";
232				};
233			};
234		};
235
236		gpu0_thermal: gpu0-thermal {
237			/* milliseconds */
238			polling-delay-passive = <0>;
239			polling-delay = <0>;
240			thermal-sensors = <&ths 1>;
241		};
242
243		gpu1_thermal: gpu1-thermal {
244			/* milliseconds */
245			polling-delay-passive = <0>;
246			polling-delay = <0>;
247			thermal-sensors = <&ths 2>;
248		};
249	};
250
251	soc {
252		compatible = "simple-bus";
253		#address-cells = <1>;
254		#size-cells = <1>;
255		ranges;
256
257		bus@1000000 {
258			compatible = "allwinner,sun50i-a64-de2";
259			reg = <0x1000000 0x400000>;
260			allwinner,sram = <&de2_sram 1>;
261			#address-cells = <1>;
262			#size-cells = <1>;
263			ranges = <0 0x1000000 0x400000>;
264
265			display_clocks: clock@0 {
266				compatible = "allwinner,sun50i-a64-de2-clk";
267				reg = <0x0 0x10000>;
268				clocks = <&ccu CLK_BUS_DE>,
269					 <&ccu CLK_DE>;
270				clock-names = "bus",
271					      "mod";
272				resets = <&ccu RST_BUS_DE>;
273				#clock-cells = <1>;
274				#reset-cells = <1>;
275			};
276
277			mixer0: mixer@100000 {
278				compatible = "allwinner,sun50i-a64-de2-mixer-0";
279				reg = <0x100000 0x100000>;
280				clocks = <&display_clocks CLK_BUS_MIXER0>,
281					 <&display_clocks CLK_MIXER0>;
282				clock-names = "bus",
283					      "mod";
284				resets = <&display_clocks RST_MIXER0>;
285
286				ports {
287					#address-cells = <1>;
288					#size-cells = <0>;
289
290					mixer0_out: port@1 {
291						#address-cells = <1>;
292						#size-cells = <0>;
293						reg = <1>;
294
295						mixer0_out_tcon0: endpoint@0 {
296							reg = <0>;
297							remote-endpoint = <&tcon0_in_mixer0>;
298						};
299
300						mixer0_out_tcon1: endpoint@1 {
301							reg = <1>;
302							remote-endpoint = <&tcon1_in_mixer0>;
303						};
304					};
305				};
306			};
307
308			mixer1: mixer@200000 {
309				compatible = "allwinner,sun50i-a64-de2-mixer-1";
310				reg = <0x200000 0x100000>;
311				clocks = <&display_clocks CLK_BUS_MIXER1>,
312					 <&display_clocks CLK_MIXER1>;
313				clock-names = "bus",
314					      "mod";
315				resets = <&display_clocks RST_MIXER1>;
316
317				ports {
318					#address-cells = <1>;
319					#size-cells = <0>;
320
321					mixer1_out: port@1 {
322						#address-cells = <1>;
323						#size-cells = <0>;
324						reg = <1>;
325
326						mixer1_out_tcon0: endpoint@0 {
327							reg = <0>;
328							remote-endpoint = <&tcon0_in_mixer1>;
329						};
330
331						mixer1_out_tcon1: endpoint@1 {
332							reg = <1>;
333							remote-endpoint = <&tcon1_in_mixer1>;
334						};
335					};
336				};
337			};
338		};
339
340		syscon: syscon@1c00000 {
341			compatible = "allwinner,sun50i-a64-system-control";
342			reg = <0x01c00000 0x1000>;
343			#address-cells = <1>;
344			#size-cells = <1>;
345			ranges;
346
347			sram_c: sram@18000 {
348				compatible = "mmio-sram";
349				reg = <0x00018000 0x28000>;
350				#address-cells = <1>;
351				#size-cells = <1>;
352				ranges = <0 0x00018000 0x28000>;
353
354				de2_sram: sram-section@0 {
355					compatible = "allwinner,sun50i-a64-sram-c";
356					reg = <0x0000 0x28000>;
357				};
358			};
359
360			sram_c1: sram@1d00000 {
361				compatible = "mmio-sram";
362				reg = <0x01d00000 0x40000>;
363				#address-cells = <1>;
364				#size-cells = <1>;
365				ranges = <0 0x01d00000 0x40000>;
366
367				ve_sram: sram-section@0 {
368					compatible = "allwinner,sun50i-a64-sram-c1",
369						     "allwinner,sun4i-a10-sram-c1";
370					reg = <0x000000 0x40000>;
371				};
372			};
373		};
374
375		dma: dma-controller@1c02000 {
376			compatible = "allwinner,sun50i-a64-dma";
377			reg = <0x01c02000 0x1000>;
378			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
379			clocks = <&ccu CLK_BUS_DMA>;
380			dma-channels = <8>;
381			dma-requests = <27>;
382			resets = <&ccu RST_BUS_DMA>;
383			#dma-cells = <1>;
384		};
385
386		tcon0: lcd-controller@1c0c000 {
387			compatible = "allwinner,sun50i-a64-tcon-lcd",
388				     "allwinner,sun8i-a83t-tcon-lcd";
389			reg = <0x01c0c000 0x1000>;
390			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
391			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
392			clock-names = "ahb", "tcon-ch0";
393			clock-output-names = "tcon-pixel-clock";
394			#clock-cells = <0>;
395			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
396			reset-names = "lcd", "lvds";
397
398			ports {
399				#address-cells = <1>;
400				#size-cells = <0>;
401
402				tcon0_in: port@0 {
403					#address-cells = <1>;
404					#size-cells = <0>;
405					reg = <0>;
406
407					tcon0_in_mixer0: endpoint@0 {
408						reg = <0>;
409						remote-endpoint = <&mixer0_out_tcon0>;
410					};
411
412					tcon0_in_mixer1: endpoint@1 {
413						reg = <1>;
414						remote-endpoint = <&mixer1_out_tcon0>;
415					};
416				};
417
418				tcon0_out: port@1 {
419					#address-cells = <1>;
420					#size-cells = <0>;
421					reg = <1>;
422
423					tcon0_out_dsi: endpoint@1 {
424						reg = <1>;
425						remote-endpoint = <&dsi_in_tcon0>;
426						allwinner,tcon-channel = <1>;
427					};
428				};
429			};
430		};
431
432		tcon1: lcd-controller@1c0d000 {
433			compatible = "allwinner,sun50i-a64-tcon-tv",
434				     "allwinner,sun8i-a83t-tcon-tv";
435			reg = <0x01c0d000 0x1000>;
436			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
437			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
438			clock-names = "ahb", "tcon-ch1";
439			resets = <&ccu RST_BUS_TCON1>;
440			reset-names = "lcd";
441
442			ports {
443				#address-cells = <1>;
444				#size-cells = <0>;
445
446				tcon1_in: port@0 {
447					#address-cells = <1>;
448					#size-cells = <0>;
449					reg = <0>;
450
451					tcon1_in_mixer0: endpoint@0 {
452						reg = <0>;
453						remote-endpoint = <&mixer0_out_tcon1>;
454					};
455
456					tcon1_in_mixer1: endpoint@1 {
457						reg = <1>;
458						remote-endpoint = <&mixer1_out_tcon1>;
459					};
460				};
461
462				tcon1_out: port@1 {
463					#address-cells = <1>;
464					#size-cells = <0>;
465					reg = <1>;
466
467					tcon1_out_hdmi: endpoint@1 {
468						reg = <1>;
469						remote-endpoint = <&hdmi_in_tcon1>;
470					};
471				};
472			};
473		};
474
475		video-codec@1c0e000 {
476			compatible = "allwinner,sun50i-a64-video-engine";
477			reg = <0x01c0e000 0x1000>;
478			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
479				 <&ccu CLK_DRAM_VE>;
480			clock-names = "ahb", "mod", "ram";
481			resets = <&ccu RST_BUS_VE>;
482			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
483			allwinner,sram = <&ve_sram 1>;
484		};
485
486		mmc0: mmc@1c0f000 {
487			compatible = "allwinner,sun50i-a64-mmc";
488			reg = <0x01c0f000 0x1000>;
489			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
490			clock-names = "ahb", "mmc";
491			resets = <&ccu RST_BUS_MMC0>;
492			reset-names = "ahb";
493			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
494			max-frequency = <150000000>;
495			status = "disabled";
496			#address-cells = <1>;
497			#size-cells = <0>;
498		};
499
500		mmc1: mmc@1c10000 {
501			compatible = "allwinner,sun50i-a64-mmc";
502			reg = <0x01c10000 0x1000>;
503			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
504			clock-names = "ahb", "mmc";
505			resets = <&ccu RST_BUS_MMC1>;
506			reset-names = "ahb";
507			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
508			max-frequency = <150000000>;
509			status = "disabled";
510			#address-cells = <1>;
511			#size-cells = <0>;
512		};
513
514		mmc2: mmc@1c11000 {
515			compatible = "allwinner,sun50i-a64-emmc";
516			reg = <0x01c11000 0x1000>;
517			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
518			clock-names = "ahb", "mmc";
519			resets = <&ccu RST_BUS_MMC2>;
520			reset-names = "ahb";
521			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
522			max-frequency = <200000000>;
523			status = "disabled";
524			#address-cells = <1>;
525			#size-cells = <0>;
526		};
527
528		sid: eeprom@1c14000 {
529			compatible = "allwinner,sun50i-a64-sid";
530			reg = <0x1c14000 0x400>;
531			#address-cells = <1>;
532			#size-cells = <1>;
533
534			ths_calibration: thermal-sensor-calibration@34 {
535				reg = <0x34 0x8>;
536			};
537		};
538
539		crypto: crypto@1c15000 {
540			compatible = "allwinner,sun50i-a64-crypto";
541			reg = <0x01c15000 0x1000>;
542			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
543			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
544			clock-names = "bus", "mod";
545			resets = <&ccu RST_BUS_CE>;
546		};
547
548		usb_otg: usb@1c19000 {
549			compatible = "allwinner,sun8i-a33-musb";
550			reg = <0x01c19000 0x0400>;
551			clocks = <&ccu CLK_BUS_OTG>;
552			resets = <&ccu RST_BUS_OTG>;
553			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
554			interrupt-names = "mc";
555			phys = <&usbphy 0>;
556			phy-names = "usb";
557			extcon = <&usbphy 0>;
558			dr_mode = "otg";
559			status = "disabled";
560		};
561
562		usbphy: phy@1c19400 {
563			compatible = "allwinner,sun50i-a64-usb-phy";
564			reg = <0x01c19400 0x14>,
565			      <0x01c1a800 0x4>,
566			      <0x01c1b800 0x4>;
567			reg-names = "phy_ctrl",
568				    "pmu0",
569				    "pmu1";
570			clocks = <&ccu CLK_USB_PHY0>,
571				 <&ccu CLK_USB_PHY1>;
572			clock-names = "usb0_phy",
573				      "usb1_phy";
574			resets = <&ccu RST_USB_PHY0>,
575				 <&ccu RST_USB_PHY1>;
576			reset-names = "usb0_reset",
577				      "usb1_reset";
578			status = "disabled";
579			#phy-cells = <1>;
580		};
581
582		ehci0: usb@1c1a000 {
583			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
584			reg = <0x01c1a000 0x100>;
585			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
586			clocks = <&ccu CLK_BUS_OHCI0>,
587				 <&ccu CLK_BUS_EHCI0>,
588				 <&ccu CLK_USB_OHCI0>;
589			resets = <&ccu RST_BUS_OHCI0>,
590				 <&ccu RST_BUS_EHCI0>;
591			status = "disabled";
592		};
593
594		ohci0: usb@1c1a400 {
595			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
596			reg = <0x01c1a400 0x100>;
597			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
598			clocks = <&ccu CLK_BUS_OHCI0>,
599				 <&ccu CLK_USB_OHCI0>;
600			resets = <&ccu RST_BUS_OHCI0>;
601			status = "disabled";
602		};
603
604		ehci1: usb@1c1b000 {
605			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
606			reg = <0x01c1b000 0x100>;
607			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
608			clocks = <&ccu CLK_BUS_OHCI1>,
609				 <&ccu CLK_BUS_EHCI1>,
610				 <&ccu CLK_USB_OHCI1>;
611			resets = <&ccu RST_BUS_OHCI1>,
612				 <&ccu RST_BUS_EHCI1>;
613			phys = <&usbphy 1>;
614			phy-names = "usb";
615			status = "disabled";
616		};
617
618		ohci1: usb@1c1b400 {
619			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
620			reg = <0x01c1b400 0x100>;
621			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
622			clocks = <&ccu CLK_BUS_OHCI1>,
623				 <&ccu CLK_USB_OHCI1>;
624			resets = <&ccu RST_BUS_OHCI1>;
625			phys = <&usbphy 1>;
626			phy-names = "usb";
627			status = "disabled";
628		};
629
630		ccu: clock@1c20000 {
631			compatible = "allwinner,sun50i-a64-ccu";
632			reg = <0x01c20000 0x400>;
633			clocks = <&osc24M>, <&rtc 0>;
634			clock-names = "hosc", "losc";
635			#clock-cells = <1>;
636			#reset-cells = <1>;
637		};
638
639		pio: pinctrl@1c20800 {
640			compatible = "allwinner,sun50i-a64-pinctrl";
641			reg = <0x01c20800 0x400>;
642			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
643				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
644				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
645			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
646			clock-names = "apb", "hosc", "losc";
647			gpio-controller;
648			#gpio-cells = <3>;
649			interrupt-controller;
650			#interrupt-cells = <3>;
651
652			csi_pins: csi-pins {
653				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
654				       "PE7", "PE8", "PE9", "PE10", "PE11";
655				function = "csi";
656			};
657
658			/omit-if-no-ref/
659			csi_mclk_pin: csi-mclk-pin {
660				pins = "PE1";
661				function = "csi";
662			};
663
664			i2c0_pins: i2c0-pins {
665				pins = "PH0", "PH1";
666				function = "i2c0";
667			};
668
669			i2c1_pins: i2c1-pins {
670				pins = "PH2", "PH3";
671				function = "i2c1";
672			};
673
674			i2c2_pins: i2c2-pins {
675				pins = "PE14", "PE15";
676				function = "i2c2";
677			};
678
679			/omit-if-no-ref/
680			lcd_rgb666_pins: lcd-rgb666-pins {
681				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
682				       "PD5", "PD6", "PD7", "PD8", "PD9",
683				       "PD10", "PD11", "PD12", "PD13",
684				       "PD14", "PD15", "PD16", "PD17",
685				       "PD18", "PD19", "PD20", "PD21";
686				function = "lcd0";
687			};
688
689			mmc0_pins: mmc0-pins {
690				pins = "PF0", "PF1", "PF2", "PF3",
691				       "PF4", "PF5";
692				function = "mmc0";
693				drive-strength = <30>;
694				bias-pull-up;
695			};
696
697			mmc1_pins: mmc1-pins {
698				pins = "PG0", "PG1", "PG2", "PG3",
699				       "PG4", "PG5";
700				function = "mmc1";
701				drive-strength = <30>;
702				bias-pull-up;
703			};
704
705			mmc2_pins: mmc2-pins {
706				pins = "PC5", "PC6", "PC8", "PC9",
707				       "PC10","PC11", "PC12", "PC13",
708				       "PC14", "PC15", "PC16";
709				function = "mmc2";
710				drive-strength = <30>;
711				bias-pull-up;
712			};
713
714			mmc2_ds_pin: mmc2-ds-pin {
715				pins = "PC1";
716				function = "mmc2";
717				drive-strength = <30>;
718				bias-pull-up;
719			};
720
721			pwm_pin: pwm-pin {
722				pins = "PD22";
723				function = "pwm";
724			};
725
726			rmii_pins: rmii-pins {
727				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
728				       "PD18", "PD19", "PD20", "PD22", "PD23";
729				function = "emac";
730				drive-strength = <40>;
731			};
732
733			rgmii_pins: rgmii-pins {
734				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
735				       "PD13", "PD15", "PD16", "PD17", "PD18",
736				       "PD19", "PD20", "PD21", "PD22", "PD23";
737				function = "emac";
738				drive-strength = <40>;
739			};
740
741			spdif_tx_pin: spdif-tx-pin {
742				pins = "PH8";
743				function = "spdif";
744			};
745
746			spi0_pins: spi0-pins {
747				pins = "PC0", "PC1", "PC2", "PC3";
748				function = "spi0";
749			};
750
751			spi1_pins: spi1-pins {
752				pins = "PD0", "PD1", "PD2", "PD3";
753				function = "spi1";
754			};
755
756			uart0_pb_pins: uart0-pb-pins {
757				pins = "PB8", "PB9";
758				function = "uart0";
759			};
760
761			uart1_pins: uart1-pins {
762				pins = "PG6", "PG7";
763				function = "uart1";
764			};
765
766			uart1_rts_cts_pins: uart1-rts-cts-pins {
767				pins = "PG8", "PG9";
768				function = "uart1";
769			};
770
771			uart2_pins: uart2-pins {
772				pins = "PB0", "PB1";
773				function = "uart2";
774			};
775
776			uart3_pins: uart3-pins {
777				pins = "PD0", "PD1";
778				function = "uart3";
779			};
780
781			uart4_pins: uart4-pins {
782				pins = "PD2", "PD3";
783				function = "uart4";
784			};
785
786			uart4_rts_cts_pins: uart4-rts-cts-pins {
787				pins = "PD4", "PD5";
788				function = "uart4";
789			};
790		};
791
792		spdif: spdif@1c21000 {
793			#sound-dai-cells = <0>;
794			compatible = "allwinner,sun50i-a64-spdif",
795				     "allwinner,sun8i-h3-spdif";
796			reg = <0x01c21000 0x400>;
797			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
798			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
799			resets = <&ccu RST_BUS_SPDIF>;
800			clock-names = "apb", "spdif";
801			dmas = <&dma 2>;
802			dma-names = "tx";
803			pinctrl-names = "default";
804			pinctrl-0 = <&spdif_tx_pin>;
805			status = "disabled";
806		};
807
808		lradc: lradc@1c21800 {
809			compatible = "allwinner,sun50i-a64-lradc",
810				     "allwinner,sun8i-a83t-r-lradc";
811			reg = <0x01c21800 0x400>;
812			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
813			status = "disabled";
814		};
815
816		i2s0: i2s@1c22000 {
817			#sound-dai-cells = <0>;
818			compatible = "allwinner,sun50i-a64-i2s",
819				     "allwinner,sun8i-h3-i2s";
820			reg = <0x01c22000 0x400>;
821			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
822			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
823			clock-names = "apb", "mod";
824			resets = <&ccu RST_BUS_I2S0>;
825			dma-names = "rx", "tx";
826			dmas = <&dma 3>, <&dma 3>;
827			status = "disabled";
828		};
829
830		i2s1: i2s@1c22400 {
831			#sound-dai-cells = <0>;
832			compatible = "allwinner,sun50i-a64-i2s",
833				     "allwinner,sun8i-h3-i2s";
834			reg = <0x01c22400 0x400>;
835			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
836			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
837			clock-names = "apb", "mod";
838			resets = <&ccu RST_BUS_I2S1>;
839			dma-names = "rx", "tx";
840			dmas = <&dma 4>, <&dma 4>;
841			status = "disabled";
842		};
843
844		dai: dai@1c22c00 {
845			#sound-dai-cells = <0>;
846			compatible = "allwinner,sun50i-a64-codec-i2s";
847			reg = <0x01c22c00 0x200>;
848			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
849			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
850			clock-names = "apb", "mod";
851			resets = <&ccu RST_BUS_CODEC>;
852			dmas = <&dma 15>, <&dma 15>;
853			dma-names = "rx", "tx";
854			status = "disabled";
855		};
856
857		codec: codec@1c22e00 {
858			#sound-dai-cells = <0>;
859			compatible = "allwinner,sun8i-a33-codec";
860			reg = <0x01c22e00 0x600>;
861			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
862			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
863			clock-names = "bus", "mod";
864			status = "disabled";
865		};
866
867		ths: thermal-sensor@1c25000 {
868			compatible = "allwinner,sun50i-a64-ths";
869			reg = <0x01c25000 0x100>;
870			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
871			clock-names = "bus", "mod";
872			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
873			resets = <&ccu RST_BUS_THS>;
874			nvmem-cells = <&ths_calibration>;
875			nvmem-cell-names = "calibration";
876			#thermal-sensor-cells = <1>;
877		};
878
879		uart0: serial@1c28000 {
880			compatible = "snps,dw-apb-uart";
881			reg = <0x01c28000 0x400>;
882			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
883			reg-shift = <2>;
884			reg-io-width = <4>;
885			clocks = <&ccu CLK_BUS_UART0>;
886			resets = <&ccu RST_BUS_UART0>;
887			status = "disabled";
888		};
889
890		uart1: serial@1c28400 {
891			compatible = "snps,dw-apb-uart";
892			reg = <0x01c28400 0x400>;
893			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
894			reg-shift = <2>;
895			reg-io-width = <4>;
896			clocks = <&ccu CLK_BUS_UART1>;
897			resets = <&ccu RST_BUS_UART1>;
898			status = "disabled";
899		};
900
901		uart2: serial@1c28800 {
902			compatible = "snps,dw-apb-uart";
903			reg = <0x01c28800 0x400>;
904			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
905			reg-shift = <2>;
906			reg-io-width = <4>;
907			clocks = <&ccu CLK_BUS_UART2>;
908			resets = <&ccu RST_BUS_UART2>;
909			status = "disabled";
910		};
911
912		uart3: serial@1c28c00 {
913			compatible = "snps,dw-apb-uart";
914			reg = <0x01c28c00 0x400>;
915			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
916			reg-shift = <2>;
917			reg-io-width = <4>;
918			clocks = <&ccu CLK_BUS_UART3>;
919			resets = <&ccu RST_BUS_UART3>;
920			status = "disabled";
921		};
922
923		uart4: serial@1c29000 {
924			compatible = "snps,dw-apb-uart";
925			reg = <0x01c29000 0x400>;
926			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
927			reg-shift = <2>;
928			reg-io-width = <4>;
929			clocks = <&ccu CLK_BUS_UART4>;
930			resets = <&ccu RST_BUS_UART4>;
931			status = "disabled";
932		};
933
934		i2c0: i2c@1c2ac00 {
935			compatible = "allwinner,sun6i-a31-i2c";
936			reg = <0x01c2ac00 0x400>;
937			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
938			clocks = <&ccu CLK_BUS_I2C0>;
939			resets = <&ccu RST_BUS_I2C0>;
940			pinctrl-names = "default";
941			pinctrl-0 = <&i2c0_pins>;
942			status = "disabled";
943			#address-cells = <1>;
944			#size-cells = <0>;
945		};
946
947		i2c1: i2c@1c2b000 {
948			compatible = "allwinner,sun6i-a31-i2c";
949			reg = <0x01c2b000 0x400>;
950			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
951			clocks = <&ccu CLK_BUS_I2C1>;
952			resets = <&ccu RST_BUS_I2C1>;
953			pinctrl-names = "default";
954			pinctrl-0 = <&i2c1_pins>;
955			status = "disabled";
956			#address-cells = <1>;
957			#size-cells = <0>;
958		};
959
960		i2c2: i2c@1c2b400 {
961			compatible = "allwinner,sun6i-a31-i2c";
962			reg = <0x01c2b400 0x400>;
963			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
964			clocks = <&ccu CLK_BUS_I2C2>;
965			resets = <&ccu RST_BUS_I2C2>;
966			pinctrl-names = "default";
967			pinctrl-0 = <&i2c2_pins>;
968			status = "disabled";
969			#address-cells = <1>;
970			#size-cells = <0>;
971		};
972
973		spi0: spi@1c68000 {
974			compatible = "allwinner,sun8i-h3-spi";
975			reg = <0x01c68000 0x1000>;
976			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
977			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
978			clock-names = "ahb", "mod";
979			dmas = <&dma 23>, <&dma 23>;
980			dma-names = "rx", "tx";
981			pinctrl-names = "default";
982			pinctrl-0 = <&spi0_pins>;
983			resets = <&ccu RST_BUS_SPI0>;
984			status = "disabled";
985			num-cs = <1>;
986			#address-cells = <1>;
987			#size-cells = <0>;
988		};
989
990		spi1: spi@1c69000 {
991			compatible = "allwinner,sun8i-h3-spi";
992			reg = <0x01c69000 0x1000>;
993			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
994			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
995			clock-names = "ahb", "mod";
996			dmas = <&dma 24>, <&dma 24>;
997			dma-names = "rx", "tx";
998			pinctrl-names = "default";
999			pinctrl-0 = <&spi1_pins>;
1000			resets = <&ccu RST_BUS_SPI1>;
1001			status = "disabled";
1002			num-cs = <1>;
1003			#address-cells = <1>;
1004			#size-cells = <0>;
1005		};
1006
1007		emac: ethernet@1c30000 {
1008			compatible = "allwinner,sun50i-a64-emac";
1009			syscon = <&syscon>;
1010			reg = <0x01c30000 0x10000>;
1011			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1012			interrupt-names = "macirq";
1013			resets = <&ccu RST_BUS_EMAC>;
1014			reset-names = "stmmaceth";
1015			clocks = <&ccu CLK_BUS_EMAC>;
1016			clock-names = "stmmaceth";
1017			status = "disabled";
1018
1019			mdio: mdio {
1020				compatible = "snps,dwmac-mdio";
1021				#address-cells = <1>;
1022				#size-cells = <0>;
1023			};
1024		};
1025
1026		mali: gpu@1c40000 {
1027			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1028			reg = <0x01c40000 0x10000>;
1029			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1030				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1031				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1032				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1033				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1034				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1035				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1036			interrupt-names = "gp",
1037					  "gpmmu",
1038					  "pp0",
1039					  "ppmmu0",
1040					  "pp1",
1041					  "ppmmu1",
1042					  "pmu";
1043			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1044			clock-names = "bus", "core";
1045			resets = <&ccu RST_BUS_GPU>;
1046		};
1047
1048		gic: interrupt-controller@1c81000 {
1049			compatible = "arm,gic-400";
1050			reg = <0x01c81000 0x1000>,
1051			      <0x01c82000 0x2000>,
1052			      <0x01c84000 0x2000>,
1053			      <0x01c86000 0x2000>;
1054			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1055			interrupt-controller;
1056			#interrupt-cells = <3>;
1057		};
1058
1059		pwm: pwm@1c21400 {
1060			compatible = "allwinner,sun50i-a64-pwm",
1061				     "allwinner,sun5i-a13-pwm";
1062			reg = <0x01c21400 0x400>;
1063			clocks = <&osc24M>;
1064			pinctrl-names = "default";
1065			pinctrl-0 = <&pwm_pin>;
1066			#pwm-cells = <3>;
1067			status = "disabled";
1068		};
1069
1070		mbus: dram-controller@1c62000 {
1071			compatible = "allwinner,sun50i-a64-mbus";
1072			reg = <0x01c62000 0x1000>;
1073			clocks = <&ccu 112>;
1074			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1075			#interconnect-cells = <1>;
1076		};
1077
1078		csi: csi@1cb0000 {
1079			compatible = "allwinner,sun50i-a64-csi";
1080			reg = <0x01cb0000 0x1000>;
1081			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1082			clocks = <&ccu CLK_BUS_CSI>,
1083				 <&ccu CLK_CSI_SCLK>,
1084				 <&ccu CLK_DRAM_CSI>;
1085			clock-names = "bus", "mod", "ram";
1086			resets = <&ccu RST_BUS_CSI>;
1087			pinctrl-names = "default";
1088			pinctrl-0 = <&csi_pins>;
1089			status = "disabled";
1090		};
1091
1092		dsi: dsi@1ca0000 {
1093			compatible = "allwinner,sun50i-a64-mipi-dsi";
1094			reg = <0x01ca0000 0x1000>;
1095			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1096			clocks = <&ccu CLK_BUS_MIPI_DSI>;
1097			resets = <&ccu RST_BUS_MIPI_DSI>;
1098			phys = <&dphy>;
1099			phy-names = "dphy";
1100			status = "disabled";
1101			#address-cells = <1>;
1102			#size-cells = <0>;
1103
1104			port {
1105				dsi_in_tcon0: endpoint {
1106					remote-endpoint = <&tcon0_out_dsi>;
1107				};
1108			};
1109		};
1110
1111		dphy: d-phy@1ca1000 {
1112			compatible = "allwinner,sun50i-a64-mipi-dphy",
1113				     "allwinner,sun6i-a31-mipi-dphy";
1114			reg = <0x01ca1000 0x1000>;
1115			clocks = <&ccu CLK_BUS_MIPI_DSI>,
1116				 <&ccu CLK_DSI_DPHY>;
1117			clock-names = "bus", "mod";
1118			resets = <&ccu RST_BUS_MIPI_DSI>;
1119			status = "disabled";
1120			#phy-cells = <0>;
1121		};
1122
1123		deinterlace: deinterlace@1e00000 {
1124			compatible = "allwinner,sun50i-a64-deinterlace",
1125				     "allwinner,sun8i-h3-deinterlace";
1126			reg = <0x01e00000 0x20000>;
1127			clocks = <&ccu CLK_BUS_DEINTERLACE>,
1128				 <&ccu CLK_DEINTERLACE>,
1129				 <&ccu CLK_DRAM_DEINTERLACE>;
1130			clock-names = "bus", "mod", "ram";
1131			resets = <&ccu RST_BUS_DEINTERLACE>;
1132			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1133			interconnects = <&mbus 9>;
1134			interconnect-names = "dma-mem";
1135		};
1136
1137		hdmi: hdmi@1ee0000 {
1138			compatible = "allwinner,sun50i-a64-dw-hdmi",
1139				     "allwinner,sun8i-a83t-dw-hdmi";
1140			reg = <0x01ee0000 0x10000>;
1141			reg-io-width = <1>;
1142			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1143			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1144				 <&ccu CLK_HDMI>;
1145			clock-names = "iahb", "isfr", "tmds";
1146			resets = <&ccu RST_BUS_HDMI1>;
1147			reset-names = "ctrl";
1148			phys = <&hdmi_phy>;
1149			phy-names = "phy";
1150			status = "disabled";
1151
1152			ports {
1153				#address-cells = <1>;
1154				#size-cells = <0>;
1155
1156				hdmi_in: port@0 {
1157					reg = <0>;
1158
1159					hdmi_in_tcon1: endpoint {
1160						remote-endpoint = <&tcon1_out_hdmi>;
1161					};
1162				};
1163
1164				hdmi_out: port@1 {
1165					reg = <1>;
1166				};
1167			};
1168		};
1169
1170		hdmi_phy: hdmi-phy@1ef0000 {
1171			compatible = "allwinner,sun50i-a64-hdmi-phy";
1172			reg = <0x01ef0000 0x10000>;
1173			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1174				 <&ccu CLK_PLL_VIDEO0>;
1175			clock-names = "bus", "mod", "pll-0";
1176			resets = <&ccu RST_BUS_HDMI0>;
1177			reset-names = "phy";
1178			#phy-cells = <0>;
1179		};
1180
1181		rtc: rtc@1f00000 {
1182			compatible = "allwinner,sun50i-a64-rtc",
1183				     "allwinner,sun8i-h3-rtc";
1184			reg = <0x01f00000 0x400>;
1185			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1186				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1187			clock-output-names = "osc32k", "osc32k-out", "iosc";
1188			clocks = <&osc32k>;
1189			#clock-cells = <1>;
1190		};
1191
1192		r_intc: interrupt-controller@1f00c00 {
1193			compatible = "allwinner,sun50i-a64-r-intc",
1194				     "allwinner,sun6i-a31-r-intc";
1195			interrupt-controller;
1196			#interrupt-cells = <2>;
1197			reg = <0x01f00c00 0x400>;
1198			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1199		};
1200
1201		r_ccu: clock@1f01400 {
1202			compatible = "allwinner,sun50i-a64-r-ccu";
1203			reg = <0x01f01400 0x100>;
1204			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1205				 <&ccu CLK_PLL_PERIPH0>;
1206			clock-names = "hosc", "losc", "iosc", "pll-periph";
1207			#clock-cells = <1>;
1208			#reset-cells = <1>;
1209		};
1210
1211		codec_analog: codec-analog@1f015c0 {
1212			compatible = "allwinner,sun50i-a64-codec-analog";
1213			reg = <0x01f015c0 0x4>;
1214			status = "disabled";
1215		};
1216
1217		r_i2c: i2c@1f02400 {
1218			compatible = "allwinner,sun50i-a64-i2c",
1219				     "allwinner,sun6i-a31-i2c";
1220			reg = <0x01f02400 0x400>;
1221			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1222			clocks = <&r_ccu CLK_APB0_I2C>;
1223			resets = <&r_ccu RST_APB0_I2C>;
1224			status = "disabled";
1225			#address-cells = <1>;
1226			#size-cells = <0>;
1227		};
1228
1229		r_ir: ir@1f02000 {
1230			compatible = "allwinner,sun50i-a64-ir",
1231				     "allwinner,sun6i-a31-ir";
1232			reg = <0x01f02000 0x400>;
1233			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1234			clock-names = "apb", "ir";
1235			resets = <&r_ccu RST_APB0_IR>;
1236			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1237			pinctrl-names = "default";
1238			pinctrl-0 = <&r_ir_rx_pin>;
1239			status = "disabled";
1240		};
1241
1242		r_pwm: pwm@1f03800 {
1243			compatible = "allwinner,sun50i-a64-pwm",
1244				     "allwinner,sun5i-a13-pwm";
1245			reg = <0x01f03800 0x400>;
1246			clocks = <&osc24M>;
1247			pinctrl-names = "default";
1248			pinctrl-0 = <&r_pwm_pin>;
1249			#pwm-cells = <3>;
1250			status = "disabled";
1251		};
1252
1253		r_pio: pinctrl@1f02c00 {
1254			compatible = "allwinner,sun50i-a64-r-pinctrl";
1255			reg = <0x01f02c00 0x400>;
1256			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1257			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1258			clock-names = "apb", "hosc", "losc";
1259			gpio-controller;
1260			#gpio-cells = <3>;
1261			interrupt-controller;
1262			#interrupt-cells = <3>;
1263
1264			r_i2c_pl89_pins: r-i2c-pl89-pins {
1265				pins = "PL8", "PL9";
1266				function = "s_i2c";
1267			};
1268
1269			r_ir_rx_pin: r-ir-rx-pin {
1270				pins = "PL11";
1271				function = "s_cir_rx";
1272			};
1273
1274			r_pwm_pin: r-pwm-pin {
1275				pins = "PL10";
1276				function = "s_pwm";
1277			};
1278
1279			r_rsb_pins: r-rsb-pins {
1280				pins = "PL0", "PL1";
1281				function = "s_rsb";
1282			};
1283		};
1284
1285		r_rsb: rsb@1f03400 {
1286			compatible = "allwinner,sun8i-a23-rsb";
1287			reg = <0x01f03400 0x400>;
1288			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1289			clocks = <&r_ccu 6>;
1290			clock-frequency = <3000000>;
1291			resets = <&r_ccu 2>;
1292			pinctrl-names = "default";
1293			pinctrl-0 = <&r_rsb_pins>;
1294			status = "disabled";
1295			#address-cells = <1>;
1296			#size-cells = <0>;
1297		};
1298
1299		wdt0: watchdog@1c20ca0 {
1300			compatible = "allwinner,sun50i-a64-wdt",
1301				     "allwinner,sun6i-a31-wdt";
1302			reg = <0x01c20ca0 0x20>;
1303			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1304			clocks = <&osc24M>;
1305		};
1306	};
1307};
1308