1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-r-ccu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/sun50i-a64-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/reset/sun8i-r-ccu.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 chosen { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 simplefb_lcd: framebuffer-lcd { 26 compatible = "allwinner,simple-framebuffer", 27 "simple-framebuffer"; 28 allwinner,pipeline = "mixer0-lcd0"; 29 clocks = <&ccu CLK_TCON0>, 30 <&display_clocks CLK_MIXER0>; 31 status = "disabled"; 32 }; 33 34 simplefb_hdmi: framebuffer-hdmi { 35 compatible = "allwinner,simple-framebuffer", 36 "simple-framebuffer"; 37 allwinner,pipeline = "mixer1-lcd1-hdmi"; 38 clocks = <&display_clocks CLK_MIXER1>, 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40 status = "disabled"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 reg = <0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2>; 54 clocks = <&ccu 21>; 55 clock-names = "cpu"; 56 #cooling-cells = <2>; 57 }; 58 59 cpu1: cpu@1 { 60 compatible = "arm,cortex-a53"; 61 device_type = "cpu"; 62 reg = <1>; 63 enable-method = "psci"; 64 next-level-cache = <&L2>; 65 clocks = <&ccu 21>; 66 clock-names = "cpu"; 67 #cooling-cells = <2>; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53"; 72 device_type = "cpu"; 73 reg = <2>; 74 enable-method = "psci"; 75 next-level-cache = <&L2>; 76 clocks = <&ccu 21>; 77 clock-names = "cpu"; 78 #cooling-cells = <2>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 reg = <3>; 85 enable-method = "psci"; 86 next-level-cache = <&L2>; 87 clocks = <&ccu 21>; 88 clock-names = "cpu"; 89 #cooling-cells = <2>; 90 }; 91 92 L2: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 }; 96 }; 97 98 de: display-engine { 99 compatible = "allwinner,sun50i-a64-display-engine"; 100 allwinner,pipelines = <&mixer0>, 101 <&mixer1>; 102 status = "disabled"; 103 }; 104 105 osc24M: osc24M_clk { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <24000000>; 109 clock-output-names = "osc24M"; 110 }; 111 112 osc32k: osc32k_clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <32768>; 116 clock-output-names = "ext-osc32k"; 117 }; 118 119 pmu { 120 compatible = "arm,cortex-a53-pmu"; 121 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 125 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 126 }; 127 128 psci { 129 compatible = "arm,psci-0.2"; 130 method = "smc"; 131 }; 132 133 sound: sound { 134 compatible = "simple-audio-card"; 135 simple-audio-card,name = "sun50i-a64-audio"; 136 simple-audio-card,format = "i2s"; 137 simple-audio-card,frame-master = <&cpudai>; 138 simple-audio-card,bitclock-master = <&cpudai>; 139 simple-audio-card,mclk-fs = <128>; 140 simple-audio-card,aux-devs = <&codec_analog>; 141 simple-audio-card,routing = 142 "Left DAC", "AIF1 Slot 0 Left", 143 "Right DAC", "AIF1 Slot 0 Right", 144 "AIF1 Slot 0 Left ADC", "Left ADC", 145 "AIF1 Slot 0 Right ADC", "Right ADC"; 146 status = "disabled"; 147 148 cpudai: simple-audio-card,cpu { 149 sound-dai = <&dai>; 150 }; 151 152 link_codec: simple-audio-card,codec { 153 sound-dai = <&codec>; 154 }; 155 }; 156 157 sound_spdif { 158 compatible = "simple-audio-card"; 159 simple-audio-card,name = "On-board SPDIF"; 160 161 simple-audio-card,cpu { 162 sound-dai = <&spdif>; 163 }; 164 165 simple-audio-card,codec { 166 sound-dai = <&spdif_out>; 167 }; 168 }; 169 170 spdif_out: spdif-out { 171 #sound-dai-cells = <0>; 172 compatible = "linux,spdif-dit"; 173 }; 174 175 timer { 176 compatible = "arm,armv8-timer"; 177 allwinner,erratum-unknown1; 178 interrupts = <GIC_PPI 13 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 180 <GIC_PPI 14 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 182 <GIC_PPI 11 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 10 185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 thermal-zones { 189 cpu_thermal: cpu0-thermal { 190 /* milliseconds */ 191 polling-delay-passive = <0>; 192 polling-delay = <0>; 193 thermal-sensors = <&ths 0>; 194 195 cooling-maps { 196 map0 { 197 trip = <&cpu_alert0>; 198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 202 }; 203 map1 { 204 trip = <&cpu_alert1>; 205 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 212 trips { 213 cpu_alert0: cpu_alert0 { 214 /* milliCelsius */ 215 temperature = <75000>; 216 hysteresis = <2000>; 217 type = "passive"; 218 }; 219 220 cpu_alert1: cpu_alert1 { 221 /* milliCelsius */ 222 temperature = <90000>; 223 hysteresis = <2000>; 224 type = "hot"; 225 }; 226 227 cpu_crit: cpu_crit { 228 /* milliCelsius */ 229 temperature = <110000>; 230 hysteresis = <2000>; 231 type = "critical"; 232 }; 233 }; 234 }; 235 236 gpu0_thermal: gpu0-thermal { 237 /* milliseconds */ 238 polling-delay-passive = <0>; 239 polling-delay = <0>; 240 thermal-sensors = <&ths 1>; 241 }; 242 243 gpu1_thermal: gpu1-thermal { 244 /* milliseconds */ 245 polling-delay-passive = <0>; 246 polling-delay = <0>; 247 thermal-sensors = <&ths 2>; 248 }; 249 }; 250 251 soc { 252 compatible = "simple-bus"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges; 256 257 bus@1000000 { 258 compatible = "allwinner,sun50i-a64-de2"; 259 reg = <0x1000000 0x400000>; 260 allwinner,sram = <&de2_sram 1>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0 0x1000000 0x400000>; 264 265 display_clocks: clock@0 { 266 compatible = "allwinner,sun50i-a64-de2-clk"; 267 reg = <0x0 0x10000>; 268 clocks = <&ccu CLK_BUS_DE>, 269 <&ccu CLK_DE>; 270 clock-names = "bus", 271 "mod"; 272 resets = <&ccu RST_BUS_DE>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 }; 276 277 rotate: rotate@20000 { 278 compatible = "allwinner,sun50i-a64-de2-rotate", 279 "allwinner,sun8i-a83t-de2-rotate"; 280 reg = <0x20000 0x10000>; 281 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&display_clocks CLK_BUS_ROT>, 283 <&display_clocks CLK_ROT>; 284 clock-names = "bus", 285 "mod"; 286 resets = <&display_clocks RST_ROT>; 287 }; 288 289 mixer0: mixer@100000 { 290 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 291 reg = <0x100000 0x100000>; 292 clocks = <&display_clocks CLK_BUS_MIXER0>, 293 <&display_clocks CLK_MIXER0>; 294 clock-names = "bus", 295 "mod"; 296 resets = <&display_clocks RST_MIXER0>; 297 298 ports { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 302 mixer0_out: port@1 { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 reg = <1>; 306 307 mixer0_out_tcon0: endpoint@0 { 308 reg = <0>; 309 remote-endpoint = <&tcon0_in_mixer0>; 310 }; 311 312 mixer0_out_tcon1: endpoint@1 { 313 reg = <1>; 314 remote-endpoint = <&tcon1_in_mixer0>; 315 }; 316 }; 317 }; 318 }; 319 320 mixer1: mixer@200000 { 321 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 322 reg = <0x200000 0x100000>; 323 clocks = <&display_clocks CLK_BUS_MIXER1>, 324 <&display_clocks CLK_MIXER1>; 325 clock-names = "bus", 326 "mod"; 327 resets = <&display_clocks RST_MIXER1>; 328 329 ports { 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 mixer1_out: port@1 { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <1>; 337 338 mixer1_out_tcon0: endpoint@0 { 339 reg = <0>; 340 remote-endpoint = <&tcon0_in_mixer1>; 341 }; 342 343 mixer1_out_tcon1: endpoint@1 { 344 reg = <1>; 345 remote-endpoint = <&tcon1_in_mixer1>; 346 }; 347 }; 348 }; 349 }; 350 }; 351 352 syscon: syscon@1c00000 { 353 compatible = "allwinner,sun50i-a64-system-control"; 354 reg = <0x01c00000 0x1000>; 355 #address-cells = <1>; 356 #size-cells = <1>; 357 ranges; 358 359 sram_c: sram@18000 { 360 compatible = "mmio-sram"; 361 reg = <0x00018000 0x28000>; 362 #address-cells = <1>; 363 #size-cells = <1>; 364 ranges = <0 0x00018000 0x28000>; 365 366 de2_sram: sram-section@0 { 367 compatible = "allwinner,sun50i-a64-sram-c"; 368 reg = <0x0000 0x28000>; 369 }; 370 }; 371 372 sram_c1: sram@1d00000 { 373 compatible = "mmio-sram"; 374 reg = <0x01d00000 0x40000>; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges = <0 0x01d00000 0x40000>; 378 379 ve_sram: sram-section@0 { 380 compatible = "allwinner,sun50i-a64-sram-c1", 381 "allwinner,sun4i-a10-sram-c1"; 382 reg = <0x000000 0x40000>; 383 }; 384 }; 385 }; 386 387 dma: dma-controller@1c02000 { 388 compatible = "allwinner,sun50i-a64-dma"; 389 reg = <0x01c02000 0x1000>; 390 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&ccu CLK_BUS_DMA>; 392 dma-channels = <8>; 393 dma-requests = <27>; 394 resets = <&ccu RST_BUS_DMA>; 395 #dma-cells = <1>; 396 }; 397 398 tcon0: lcd-controller@1c0c000 { 399 compatible = "allwinner,sun50i-a64-tcon-lcd", 400 "allwinner,sun8i-a83t-tcon-lcd"; 401 reg = <0x01c0c000 0x1000>; 402 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 404 clock-names = "ahb", "tcon-ch0"; 405 clock-output-names = "tcon-pixel-clock"; 406 #clock-cells = <0>; 407 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 408 reset-names = "lcd", "lvds"; 409 410 ports { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 414 tcon0_in: port@0 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 reg = <0>; 418 419 tcon0_in_mixer0: endpoint@0 { 420 reg = <0>; 421 remote-endpoint = <&mixer0_out_tcon0>; 422 }; 423 424 tcon0_in_mixer1: endpoint@1 { 425 reg = <1>; 426 remote-endpoint = <&mixer1_out_tcon0>; 427 }; 428 }; 429 430 tcon0_out: port@1 { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 reg = <1>; 434 435 tcon0_out_dsi: endpoint@1 { 436 reg = <1>; 437 remote-endpoint = <&dsi_in_tcon0>; 438 allwinner,tcon-channel = <1>; 439 }; 440 }; 441 }; 442 }; 443 444 tcon1: lcd-controller@1c0d000 { 445 compatible = "allwinner,sun50i-a64-tcon-tv", 446 "allwinner,sun8i-a83t-tcon-tv"; 447 reg = <0x01c0d000 0x1000>; 448 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 450 clock-names = "ahb", "tcon-ch1"; 451 resets = <&ccu RST_BUS_TCON1>; 452 reset-names = "lcd"; 453 454 ports { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 458 tcon1_in: port@0 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0>; 462 463 tcon1_in_mixer0: endpoint@0 { 464 reg = <0>; 465 remote-endpoint = <&mixer0_out_tcon1>; 466 }; 467 468 tcon1_in_mixer1: endpoint@1 { 469 reg = <1>; 470 remote-endpoint = <&mixer1_out_tcon1>; 471 }; 472 }; 473 474 tcon1_out: port@1 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <1>; 478 479 tcon1_out_hdmi: endpoint@1 { 480 reg = <1>; 481 remote-endpoint = <&hdmi_in_tcon1>; 482 }; 483 }; 484 }; 485 }; 486 487 video-codec@1c0e000 { 488 compatible = "allwinner,sun50i-a64-video-engine"; 489 reg = <0x01c0e000 0x1000>; 490 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 491 <&ccu CLK_DRAM_VE>; 492 clock-names = "ahb", "mod", "ram"; 493 resets = <&ccu RST_BUS_VE>; 494 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 495 allwinner,sram = <&ve_sram 1>; 496 }; 497 498 mmc0: mmc@1c0f000 { 499 compatible = "allwinner,sun50i-a64-mmc"; 500 reg = <0x01c0f000 0x1000>; 501 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 502 clock-names = "ahb", "mmc"; 503 resets = <&ccu RST_BUS_MMC0>; 504 reset-names = "ahb"; 505 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 506 max-frequency = <150000000>; 507 status = "disabled"; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 }; 511 512 mmc1: mmc@1c10000 { 513 compatible = "allwinner,sun50i-a64-mmc"; 514 reg = <0x01c10000 0x1000>; 515 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 516 clock-names = "ahb", "mmc"; 517 resets = <&ccu RST_BUS_MMC1>; 518 reset-names = "ahb"; 519 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 520 max-frequency = <150000000>; 521 status = "disabled"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 }; 525 526 mmc2: mmc@1c11000 { 527 compatible = "allwinner,sun50i-a64-emmc"; 528 reg = <0x01c11000 0x1000>; 529 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 530 clock-names = "ahb", "mmc"; 531 resets = <&ccu RST_BUS_MMC2>; 532 reset-names = "ahb"; 533 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 534 max-frequency = <200000000>; 535 status = "disabled"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 }; 539 540 sid: eeprom@1c14000 { 541 compatible = "allwinner,sun50i-a64-sid"; 542 reg = <0x1c14000 0x400>; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 546 ths_calibration: thermal-sensor-calibration@34 { 547 reg = <0x34 0x8>; 548 }; 549 }; 550 551 crypto: crypto@1c15000 { 552 compatible = "allwinner,sun50i-a64-crypto"; 553 reg = <0x01c15000 0x1000>; 554 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 556 clock-names = "bus", "mod"; 557 resets = <&ccu RST_BUS_CE>; 558 }; 559 560 msgbox: mailbox@1c17000 { 561 compatible = "allwinner,sun50i-a64-msgbox", 562 "allwinner,sun6i-a31-msgbox"; 563 reg = <0x01c17000 0x1000>; 564 clocks = <&ccu CLK_BUS_MSGBOX>; 565 resets = <&ccu RST_BUS_MSGBOX>; 566 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 567 #mbox-cells = <1>; 568 }; 569 570 usb_otg: usb@1c19000 { 571 compatible = "allwinner,sun8i-a33-musb"; 572 reg = <0x01c19000 0x0400>; 573 clocks = <&ccu CLK_BUS_OTG>; 574 resets = <&ccu RST_BUS_OTG>; 575 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 576 interrupt-names = "mc"; 577 phys = <&usbphy 0>; 578 phy-names = "usb"; 579 extcon = <&usbphy 0>; 580 dr_mode = "otg"; 581 status = "disabled"; 582 }; 583 584 usbphy: phy@1c19400 { 585 compatible = "allwinner,sun50i-a64-usb-phy"; 586 reg = <0x01c19400 0x14>, 587 <0x01c1a800 0x4>, 588 <0x01c1b800 0x4>; 589 reg-names = "phy_ctrl", 590 "pmu0", 591 "pmu1"; 592 clocks = <&ccu CLK_USB_PHY0>, 593 <&ccu CLK_USB_PHY1>; 594 clock-names = "usb0_phy", 595 "usb1_phy"; 596 resets = <&ccu RST_USB_PHY0>, 597 <&ccu RST_USB_PHY1>; 598 reset-names = "usb0_reset", 599 "usb1_reset"; 600 status = "disabled"; 601 #phy-cells = <1>; 602 }; 603 604 ehci0: usb@1c1a000 { 605 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 606 reg = <0x01c1a000 0x100>; 607 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&ccu CLK_BUS_OHCI0>, 609 <&ccu CLK_BUS_EHCI0>, 610 <&ccu CLK_USB_OHCI0>; 611 resets = <&ccu RST_BUS_OHCI0>, 612 <&ccu RST_BUS_EHCI0>; 613 status = "disabled"; 614 }; 615 616 ohci0: usb@1c1a400 { 617 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 618 reg = <0x01c1a400 0x100>; 619 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&ccu CLK_BUS_OHCI0>, 621 <&ccu CLK_USB_OHCI0>; 622 resets = <&ccu RST_BUS_OHCI0>; 623 status = "disabled"; 624 }; 625 626 ehci1: usb@1c1b000 { 627 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 628 reg = <0x01c1b000 0x100>; 629 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&ccu CLK_BUS_OHCI1>, 631 <&ccu CLK_BUS_EHCI1>, 632 <&ccu CLK_USB_OHCI1>; 633 resets = <&ccu RST_BUS_OHCI1>, 634 <&ccu RST_BUS_EHCI1>; 635 phys = <&usbphy 1>; 636 phy-names = "usb"; 637 status = "disabled"; 638 }; 639 640 ohci1: usb@1c1b400 { 641 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 642 reg = <0x01c1b400 0x100>; 643 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&ccu CLK_BUS_OHCI1>, 645 <&ccu CLK_USB_OHCI1>; 646 resets = <&ccu RST_BUS_OHCI1>; 647 phys = <&usbphy 1>; 648 phy-names = "usb"; 649 status = "disabled"; 650 }; 651 652 ccu: clock@1c20000 { 653 compatible = "allwinner,sun50i-a64-ccu"; 654 reg = <0x01c20000 0x400>; 655 clocks = <&osc24M>, <&rtc 0>; 656 clock-names = "hosc", "losc"; 657 #clock-cells = <1>; 658 #reset-cells = <1>; 659 }; 660 661 pio: pinctrl@1c20800 { 662 compatible = "allwinner,sun50i-a64-pinctrl"; 663 reg = <0x01c20800 0x400>; 664 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 668 clock-names = "apb", "hosc", "losc"; 669 gpio-controller; 670 #gpio-cells = <3>; 671 interrupt-controller; 672 #interrupt-cells = <3>; 673 674 csi_pins: csi-pins { 675 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 676 "PE7", "PE8", "PE9", "PE10", "PE11"; 677 function = "csi"; 678 }; 679 680 /omit-if-no-ref/ 681 csi_mclk_pin: csi-mclk-pin { 682 pins = "PE1"; 683 function = "csi"; 684 }; 685 686 i2c0_pins: i2c0-pins { 687 pins = "PH0", "PH1"; 688 function = "i2c0"; 689 }; 690 691 i2c1_pins: i2c1-pins { 692 pins = "PH2", "PH3"; 693 function = "i2c1"; 694 }; 695 696 i2c2_pins: i2c2-pins { 697 pins = "PE14", "PE15"; 698 function = "i2c2"; 699 }; 700 701 /omit-if-no-ref/ 702 lcd_rgb666_pins: lcd-rgb666-pins { 703 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 704 "PD5", "PD6", "PD7", "PD8", "PD9", 705 "PD10", "PD11", "PD12", "PD13", 706 "PD14", "PD15", "PD16", "PD17", 707 "PD18", "PD19", "PD20", "PD21"; 708 function = "lcd0"; 709 }; 710 711 mmc0_pins: mmc0-pins { 712 pins = "PF0", "PF1", "PF2", "PF3", 713 "PF4", "PF5"; 714 function = "mmc0"; 715 drive-strength = <30>; 716 bias-pull-up; 717 }; 718 719 mmc1_pins: mmc1-pins { 720 pins = "PG0", "PG1", "PG2", "PG3", 721 "PG4", "PG5"; 722 function = "mmc1"; 723 drive-strength = <30>; 724 bias-pull-up; 725 }; 726 727 mmc2_pins: mmc2-pins { 728 pins = "PC5", "PC6", "PC8", "PC9", 729 "PC10","PC11", "PC12", "PC13", 730 "PC14", "PC15", "PC16"; 731 function = "mmc2"; 732 drive-strength = <30>; 733 bias-pull-up; 734 }; 735 736 mmc2_ds_pin: mmc2-ds-pin { 737 pins = "PC1"; 738 function = "mmc2"; 739 drive-strength = <30>; 740 bias-pull-up; 741 }; 742 743 pwm_pin: pwm-pin { 744 pins = "PD22"; 745 function = "pwm"; 746 }; 747 748 rmii_pins: rmii-pins { 749 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 750 "PD18", "PD19", "PD20", "PD22", "PD23"; 751 function = "emac"; 752 drive-strength = <40>; 753 }; 754 755 rgmii_pins: rgmii-pins { 756 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 757 "PD13", "PD15", "PD16", "PD17", "PD18", 758 "PD19", "PD20", "PD21", "PD22", "PD23"; 759 function = "emac"; 760 drive-strength = <40>; 761 }; 762 763 spdif_tx_pin: spdif-tx-pin { 764 pins = "PH8"; 765 function = "spdif"; 766 }; 767 768 spi0_pins: spi0-pins { 769 pins = "PC0", "PC1", "PC2", "PC3"; 770 function = "spi0"; 771 }; 772 773 spi1_pins: spi1-pins { 774 pins = "PD0", "PD1", "PD2", "PD3"; 775 function = "spi1"; 776 }; 777 778 uart0_pb_pins: uart0-pb-pins { 779 pins = "PB8", "PB9"; 780 function = "uart0"; 781 }; 782 783 uart1_pins: uart1-pins { 784 pins = "PG6", "PG7"; 785 function = "uart1"; 786 }; 787 788 uart1_rts_cts_pins: uart1-rts-cts-pins { 789 pins = "PG8", "PG9"; 790 function = "uart1"; 791 }; 792 793 uart2_pins: uart2-pins { 794 pins = "PB0", "PB1"; 795 function = "uart2"; 796 }; 797 798 uart3_pins: uart3-pins { 799 pins = "PD0", "PD1"; 800 function = "uart3"; 801 }; 802 803 uart4_pins: uart4-pins { 804 pins = "PD2", "PD3"; 805 function = "uart4"; 806 }; 807 808 uart4_rts_cts_pins: uart4-rts-cts-pins { 809 pins = "PD4", "PD5"; 810 function = "uart4"; 811 }; 812 }; 813 814 spdif: spdif@1c21000 { 815 #sound-dai-cells = <0>; 816 compatible = "allwinner,sun50i-a64-spdif", 817 "allwinner,sun8i-h3-spdif"; 818 reg = <0x01c21000 0x400>; 819 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 821 resets = <&ccu RST_BUS_SPDIF>; 822 clock-names = "apb", "spdif"; 823 dmas = <&dma 2>; 824 dma-names = "tx"; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&spdif_tx_pin>; 827 status = "disabled"; 828 }; 829 830 lradc: lradc@1c21800 { 831 compatible = "allwinner,sun50i-a64-lradc", 832 "allwinner,sun8i-a83t-r-lradc"; 833 reg = <0x01c21800 0x400>; 834 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 835 status = "disabled"; 836 }; 837 838 i2s0: i2s@1c22000 { 839 #sound-dai-cells = <0>; 840 compatible = "allwinner,sun50i-a64-i2s", 841 "allwinner,sun8i-h3-i2s"; 842 reg = <0x01c22000 0x400>; 843 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 845 clock-names = "apb", "mod"; 846 resets = <&ccu RST_BUS_I2S0>; 847 dma-names = "rx", "tx"; 848 dmas = <&dma 3>, <&dma 3>; 849 status = "disabled"; 850 }; 851 852 i2s1: i2s@1c22400 { 853 #sound-dai-cells = <0>; 854 compatible = "allwinner,sun50i-a64-i2s", 855 "allwinner,sun8i-h3-i2s"; 856 reg = <0x01c22400 0x400>; 857 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 859 clock-names = "apb", "mod"; 860 resets = <&ccu RST_BUS_I2S1>; 861 dma-names = "rx", "tx"; 862 dmas = <&dma 4>, <&dma 4>; 863 status = "disabled"; 864 }; 865 866 dai: dai@1c22c00 { 867 #sound-dai-cells = <0>; 868 compatible = "allwinner,sun50i-a64-codec-i2s"; 869 reg = <0x01c22c00 0x200>; 870 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 872 clock-names = "apb", "mod"; 873 resets = <&ccu RST_BUS_CODEC>; 874 dmas = <&dma 15>, <&dma 15>; 875 dma-names = "rx", "tx"; 876 status = "disabled"; 877 }; 878 879 codec: codec@1c22e00 { 880 #sound-dai-cells = <0>; 881 compatible = "allwinner,sun8i-a33-codec"; 882 reg = <0x01c22e00 0x600>; 883 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 885 clock-names = "bus", "mod"; 886 status = "disabled"; 887 }; 888 889 ths: thermal-sensor@1c25000 { 890 compatible = "allwinner,sun50i-a64-ths"; 891 reg = <0x01c25000 0x100>; 892 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 893 clock-names = "bus", "mod"; 894 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 895 resets = <&ccu RST_BUS_THS>; 896 nvmem-cells = <&ths_calibration>; 897 nvmem-cell-names = "calibration"; 898 #thermal-sensor-cells = <1>; 899 }; 900 901 uart0: serial@1c28000 { 902 compatible = "snps,dw-apb-uart"; 903 reg = <0x01c28000 0x400>; 904 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 905 reg-shift = <2>; 906 reg-io-width = <4>; 907 clocks = <&ccu CLK_BUS_UART0>; 908 resets = <&ccu RST_BUS_UART0>; 909 status = "disabled"; 910 }; 911 912 uart1: serial@1c28400 { 913 compatible = "snps,dw-apb-uart"; 914 reg = <0x01c28400 0x400>; 915 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 916 reg-shift = <2>; 917 reg-io-width = <4>; 918 clocks = <&ccu CLK_BUS_UART1>; 919 resets = <&ccu RST_BUS_UART1>; 920 status = "disabled"; 921 }; 922 923 uart2: serial@1c28800 { 924 compatible = "snps,dw-apb-uart"; 925 reg = <0x01c28800 0x400>; 926 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 927 reg-shift = <2>; 928 reg-io-width = <4>; 929 clocks = <&ccu CLK_BUS_UART2>; 930 resets = <&ccu RST_BUS_UART2>; 931 status = "disabled"; 932 }; 933 934 uart3: serial@1c28c00 { 935 compatible = "snps,dw-apb-uart"; 936 reg = <0x01c28c00 0x400>; 937 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 938 reg-shift = <2>; 939 reg-io-width = <4>; 940 clocks = <&ccu CLK_BUS_UART3>; 941 resets = <&ccu RST_BUS_UART3>; 942 status = "disabled"; 943 }; 944 945 uart4: serial@1c29000 { 946 compatible = "snps,dw-apb-uart"; 947 reg = <0x01c29000 0x400>; 948 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 949 reg-shift = <2>; 950 reg-io-width = <4>; 951 clocks = <&ccu CLK_BUS_UART4>; 952 resets = <&ccu RST_BUS_UART4>; 953 status = "disabled"; 954 }; 955 956 i2c0: i2c@1c2ac00 { 957 compatible = "allwinner,sun6i-a31-i2c"; 958 reg = <0x01c2ac00 0x400>; 959 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&ccu CLK_BUS_I2C0>; 961 resets = <&ccu RST_BUS_I2C0>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&i2c0_pins>; 964 status = "disabled"; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 }; 968 969 i2c1: i2c@1c2b000 { 970 compatible = "allwinner,sun6i-a31-i2c"; 971 reg = <0x01c2b000 0x400>; 972 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&ccu CLK_BUS_I2C1>; 974 resets = <&ccu RST_BUS_I2C1>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&i2c1_pins>; 977 status = "disabled"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 }; 981 982 i2c2: i2c@1c2b400 { 983 compatible = "allwinner,sun6i-a31-i2c"; 984 reg = <0x01c2b400 0x400>; 985 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&ccu CLK_BUS_I2C2>; 987 resets = <&ccu RST_BUS_I2C2>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&i2c2_pins>; 990 status = "disabled"; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 }; 994 995 spi0: spi@1c68000 { 996 compatible = "allwinner,sun8i-h3-spi"; 997 reg = <0x01c68000 0x1000>; 998 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1000 clock-names = "ahb", "mod"; 1001 dmas = <&dma 23>, <&dma 23>; 1002 dma-names = "rx", "tx"; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&spi0_pins>; 1005 resets = <&ccu RST_BUS_SPI0>; 1006 status = "disabled"; 1007 num-cs = <1>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 }; 1011 1012 spi1: spi@1c69000 { 1013 compatible = "allwinner,sun8i-h3-spi"; 1014 reg = <0x01c69000 0x1000>; 1015 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1017 clock-names = "ahb", "mod"; 1018 dmas = <&dma 24>, <&dma 24>; 1019 dma-names = "rx", "tx"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&spi1_pins>; 1022 resets = <&ccu RST_BUS_SPI1>; 1023 status = "disabled"; 1024 num-cs = <1>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 }; 1028 1029 emac: ethernet@1c30000 { 1030 compatible = "allwinner,sun50i-a64-emac"; 1031 syscon = <&syscon>; 1032 reg = <0x01c30000 0x10000>; 1033 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1034 interrupt-names = "macirq"; 1035 resets = <&ccu RST_BUS_EMAC>; 1036 reset-names = "stmmaceth"; 1037 clocks = <&ccu CLK_BUS_EMAC>; 1038 clock-names = "stmmaceth"; 1039 status = "disabled"; 1040 1041 mdio: mdio { 1042 compatible = "snps,dwmac-mdio"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 }; 1046 }; 1047 1048 mali: gpu@1c40000 { 1049 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 1050 reg = <0x01c40000 0x10000>; 1051 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupt-names = "gp", 1059 "gpmmu", 1060 "pp0", 1061 "ppmmu0", 1062 "pp1", 1063 "ppmmu1", 1064 "pmu"; 1065 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1066 clock-names = "bus", "core"; 1067 resets = <&ccu RST_BUS_GPU>; 1068 }; 1069 1070 gic: interrupt-controller@1c81000 { 1071 compatible = "arm,gic-400"; 1072 reg = <0x01c81000 0x1000>, 1073 <0x01c82000 0x2000>, 1074 <0x01c84000 0x2000>, 1075 <0x01c86000 0x2000>; 1076 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1077 interrupt-controller; 1078 #interrupt-cells = <3>; 1079 }; 1080 1081 pwm: pwm@1c21400 { 1082 compatible = "allwinner,sun50i-a64-pwm", 1083 "allwinner,sun5i-a13-pwm"; 1084 reg = <0x01c21400 0x400>; 1085 clocks = <&osc24M>; 1086 pinctrl-names = "default"; 1087 pinctrl-0 = <&pwm_pin>; 1088 #pwm-cells = <3>; 1089 status = "disabled"; 1090 }; 1091 1092 mbus: dram-controller@1c62000 { 1093 compatible = "allwinner,sun50i-a64-mbus"; 1094 reg = <0x01c62000 0x1000>; 1095 clocks = <&ccu 112>; 1096 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1097 #interconnect-cells = <1>; 1098 }; 1099 1100 csi: csi@1cb0000 { 1101 compatible = "allwinner,sun50i-a64-csi"; 1102 reg = <0x01cb0000 0x1000>; 1103 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&ccu CLK_BUS_CSI>, 1105 <&ccu CLK_CSI_SCLK>, 1106 <&ccu CLK_DRAM_CSI>; 1107 clock-names = "bus", "mod", "ram"; 1108 resets = <&ccu RST_BUS_CSI>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&csi_pins>; 1111 status = "disabled"; 1112 }; 1113 1114 dsi: dsi@1ca0000 { 1115 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1116 reg = <0x01ca0000 0x1000>; 1117 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1119 resets = <&ccu RST_BUS_MIPI_DSI>; 1120 phys = <&dphy>; 1121 phy-names = "dphy"; 1122 status = "disabled"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 1126 port { 1127 dsi_in_tcon0: endpoint { 1128 remote-endpoint = <&tcon0_out_dsi>; 1129 }; 1130 }; 1131 }; 1132 1133 dphy: d-phy@1ca1000 { 1134 compatible = "allwinner,sun50i-a64-mipi-dphy", 1135 "allwinner,sun6i-a31-mipi-dphy"; 1136 reg = <0x01ca1000 0x1000>; 1137 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1138 <&ccu CLK_DSI_DPHY>; 1139 clock-names = "bus", "mod"; 1140 resets = <&ccu RST_BUS_MIPI_DSI>; 1141 status = "disabled"; 1142 #phy-cells = <0>; 1143 }; 1144 1145 deinterlace: deinterlace@1e00000 { 1146 compatible = "allwinner,sun50i-a64-deinterlace", 1147 "allwinner,sun8i-h3-deinterlace"; 1148 reg = <0x01e00000 0x20000>; 1149 clocks = <&ccu CLK_BUS_DEINTERLACE>, 1150 <&ccu CLK_DEINTERLACE>, 1151 <&ccu CLK_DRAM_DEINTERLACE>; 1152 clock-names = "bus", "mod", "ram"; 1153 resets = <&ccu RST_BUS_DEINTERLACE>; 1154 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1155 interconnects = <&mbus 9>; 1156 interconnect-names = "dma-mem"; 1157 }; 1158 1159 hdmi: hdmi@1ee0000 { 1160 compatible = "allwinner,sun50i-a64-dw-hdmi", 1161 "allwinner,sun8i-a83t-dw-hdmi"; 1162 reg = <0x01ee0000 0x10000>; 1163 reg-io-width = <1>; 1164 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1166 <&ccu CLK_HDMI>; 1167 clock-names = "iahb", "isfr", "tmds"; 1168 resets = <&ccu RST_BUS_HDMI1>; 1169 reset-names = "ctrl"; 1170 phys = <&hdmi_phy>; 1171 phy-names = "phy"; 1172 status = "disabled"; 1173 1174 ports { 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 hdmi_in: port@0 { 1179 reg = <0>; 1180 1181 hdmi_in_tcon1: endpoint { 1182 remote-endpoint = <&tcon1_out_hdmi>; 1183 }; 1184 }; 1185 1186 hdmi_out: port@1 { 1187 reg = <1>; 1188 }; 1189 }; 1190 }; 1191 1192 hdmi_phy: hdmi-phy@1ef0000 { 1193 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1194 reg = <0x01ef0000 0x10000>; 1195 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1196 <&ccu CLK_PLL_VIDEO0>; 1197 clock-names = "bus", "mod", "pll-0"; 1198 resets = <&ccu RST_BUS_HDMI0>; 1199 reset-names = "phy"; 1200 #phy-cells = <0>; 1201 }; 1202 1203 rtc: rtc@1f00000 { 1204 compatible = "allwinner,sun50i-a64-rtc", 1205 "allwinner,sun8i-h3-rtc"; 1206 reg = <0x01f00000 0x400>; 1207 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1209 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1210 clocks = <&osc32k>; 1211 #clock-cells = <1>; 1212 }; 1213 1214 r_intc: interrupt-controller@1f00c00 { 1215 compatible = "allwinner,sun50i-a64-r-intc", 1216 "allwinner,sun6i-a31-r-intc"; 1217 interrupt-controller; 1218 #interrupt-cells = <2>; 1219 reg = <0x01f00c00 0x400>; 1220 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1221 }; 1222 1223 r_ccu: clock@1f01400 { 1224 compatible = "allwinner,sun50i-a64-r-ccu"; 1225 reg = <0x01f01400 0x100>; 1226 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1227 <&ccu CLK_PLL_PERIPH0>; 1228 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1229 #clock-cells = <1>; 1230 #reset-cells = <1>; 1231 }; 1232 1233 codec_analog: codec-analog@1f015c0 { 1234 compatible = "allwinner,sun50i-a64-codec-analog"; 1235 reg = <0x01f015c0 0x4>; 1236 status = "disabled"; 1237 }; 1238 1239 r_i2c: i2c@1f02400 { 1240 compatible = "allwinner,sun50i-a64-i2c", 1241 "allwinner,sun6i-a31-i2c"; 1242 reg = <0x01f02400 0x400>; 1243 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&r_ccu CLK_APB0_I2C>; 1245 resets = <&r_ccu RST_APB0_I2C>; 1246 status = "disabled"; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 }; 1250 1251 r_ir: ir@1f02000 { 1252 compatible = "allwinner,sun50i-a64-ir", 1253 "allwinner,sun6i-a31-ir"; 1254 reg = <0x01f02000 0x400>; 1255 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1256 clock-names = "apb", "ir"; 1257 resets = <&r_ccu RST_APB0_IR>; 1258 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&r_ir_rx_pin>; 1261 status = "disabled"; 1262 }; 1263 1264 r_pwm: pwm@1f03800 { 1265 compatible = "allwinner,sun50i-a64-pwm", 1266 "allwinner,sun5i-a13-pwm"; 1267 reg = <0x01f03800 0x400>; 1268 clocks = <&osc24M>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&r_pwm_pin>; 1271 #pwm-cells = <3>; 1272 status = "disabled"; 1273 }; 1274 1275 r_pio: pinctrl@1f02c00 { 1276 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1277 reg = <0x01f02c00 0x400>; 1278 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1280 clock-names = "apb", "hosc", "losc"; 1281 gpio-controller; 1282 #gpio-cells = <3>; 1283 interrupt-controller; 1284 #interrupt-cells = <3>; 1285 1286 r_i2c_pl89_pins: r-i2c-pl89-pins { 1287 pins = "PL8", "PL9"; 1288 function = "s_i2c"; 1289 }; 1290 1291 r_ir_rx_pin: r-ir-rx-pin { 1292 pins = "PL11"; 1293 function = "s_cir_rx"; 1294 }; 1295 1296 r_pwm_pin: r-pwm-pin { 1297 pins = "PL10"; 1298 function = "s_pwm"; 1299 }; 1300 1301 r_rsb_pins: r-rsb-pins { 1302 pins = "PL0", "PL1"; 1303 function = "s_rsb"; 1304 }; 1305 }; 1306 1307 r_rsb: rsb@1f03400 { 1308 compatible = "allwinner,sun8i-a23-rsb"; 1309 reg = <0x01f03400 0x400>; 1310 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&r_ccu 6>; 1312 clock-frequency = <3000000>; 1313 resets = <&r_ccu 2>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&r_rsb_pins>; 1316 status = "disabled"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 }; 1320 1321 wdt0: watchdog@1c20ca0 { 1322 compatible = "allwinner,sun50i-a64-wdt", 1323 "allwinner,sun6i-a31-wdt"; 1324 reg = <0x01c20ca0 0x20>; 1325 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&osc24M>; 1327 }; 1328 }; 1329}; 1330