1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 osc24M: osc24M_clk { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 clock-frequency = <24000000>; 128 clock-output-names = "osc24M"; 129 }; 130 131 osc32k: osc32k_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <32768>; 135 clock-output-names = "osc32k"; 136 }; 137 138 iosc: internal-osc-clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <16000000>; 142 clock-accuracy = <300000000>; 143 clock-output-names = "iosc"; 144 }; 145 146 psci { 147 compatible = "arm,psci-0.2"; 148 method = "smc"; 149 }; 150 151 sound_spdif { 152 compatible = "simple-audio-card"; 153 simple-audio-card,name = "On-board SPDIF"; 154 155 simple-audio-card,cpu { 156 sound-dai = <&spdif>; 157 }; 158 159 simple-audio-card,codec { 160 sound-dai = <&spdif_out>; 161 }; 162 }; 163 164 spdif_out: spdif-out { 165 #sound-dai-cells = <0>; 166 compatible = "linux,spdif-dit"; 167 }; 168 169 timer { 170 compatible = "arm,armv8-timer"; 171 interrupts = <GIC_PPI 13 172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 173 <GIC_PPI 14 174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 11 176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 178 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 179 }; 180 181 soc { 182 compatible = "simple-bus"; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 ranges; 186 187 de2@1000000 { 188 compatible = "allwinner,sun50i-a64-de2"; 189 reg = <0x1000000 0x400000>; 190 allwinner,sram = <&de2_sram 1>; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0 0x1000000 0x400000>; 194 195 display_clocks: clock@0 { 196 compatible = "allwinner,sun50i-a64-de2-clk"; 197 reg = <0x0 0x100000>; 198 clocks = <&ccu CLK_DE>, 199 <&ccu CLK_BUS_DE>; 200 clock-names = "mod", 201 "bus"; 202 resets = <&ccu RST_BUS_DE>; 203 #clock-cells = <1>; 204 #reset-cells = <1>; 205 }; 206 }; 207 208 syscon: syscon@1c00000 { 209 compatible = "allwinner,sun50i-a64-system-control"; 210 reg = <0x01c00000 0x1000>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges; 214 215 sram_c: sram@18000 { 216 compatible = "mmio-sram"; 217 reg = <0x00018000 0x28000>; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 ranges = <0 0x00018000 0x28000>; 221 222 de2_sram: sram-section@0 { 223 compatible = "allwinner,sun50i-a64-sram-c"; 224 reg = <0x0000 0x28000>; 225 }; 226 }; 227 }; 228 229 dma: dma-controller@1c02000 { 230 compatible = "allwinner,sun50i-a64-dma"; 231 reg = <0x01c02000 0x1000>; 232 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&ccu CLK_BUS_DMA>; 234 dma-channels = <8>; 235 dma-requests = <27>; 236 resets = <&ccu RST_BUS_DMA>; 237 #dma-cells = <1>; 238 }; 239 240 mmc0: mmc@1c0f000 { 241 compatible = "allwinner,sun50i-a64-mmc"; 242 reg = <0x01c0f000 0x1000>; 243 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 244 clock-names = "ahb", "mmc"; 245 resets = <&ccu RST_BUS_MMC0>; 246 reset-names = "ahb"; 247 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 248 max-frequency = <150000000>; 249 status = "disabled"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 }; 253 254 mmc1: mmc@1c10000 { 255 compatible = "allwinner,sun50i-a64-mmc"; 256 reg = <0x01c10000 0x1000>; 257 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 258 clock-names = "ahb", "mmc"; 259 resets = <&ccu RST_BUS_MMC1>; 260 reset-names = "ahb"; 261 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 262 max-frequency = <150000000>; 263 status = "disabled"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 }; 267 268 mmc2: mmc@1c11000 { 269 compatible = "allwinner,sun50i-a64-emmc"; 270 reg = <0x01c11000 0x1000>; 271 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 272 clock-names = "ahb", "mmc"; 273 resets = <&ccu RST_BUS_MMC2>; 274 reset-names = "ahb"; 275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 276 max-frequency = <200000000>; 277 status = "disabled"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 }; 281 282 sid: eeprom@1c14000 { 283 compatible = "allwinner,sun50i-a64-sid"; 284 reg = <0x1c14000 0x400>; 285 }; 286 287 usb_otg: usb@1c19000 { 288 compatible = "allwinner,sun8i-a33-musb"; 289 reg = <0x01c19000 0x0400>; 290 clocks = <&ccu CLK_BUS_OTG>; 291 resets = <&ccu RST_BUS_OTG>; 292 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "mc"; 294 phys = <&usbphy 0>; 295 phy-names = "usb"; 296 extcon = <&usbphy 0>; 297 status = "disabled"; 298 }; 299 300 usbphy: phy@1c19400 { 301 compatible = "allwinner,sun50i-a64-usb-phy"; 302 reg = <0x01c19400 0x14>, 303 <0x01c1a800 0x4>, 304 <0x01c1b800 0x4>; 305 reg-names = "phy_ctrl", 306 "pmu0", 307 "pmu1"; 308 clocks = <&ccu CLK_USB_PHY0>, 309 <&ccu CLK_USB_PHY1>; 310 clock-names = "usb0_phy", 311 "usb1_phy"; 312 resets = <&ccu RST_USB_PHY0>, 313 <&ccu RST_USB_PHY1>; 314 reset-names = "usb0_reset", 315 "usb1_reset"; 316 status = "disabled"; 317 #phy-cells = <1>; 318 }; 319 320 ehci0: usb@1c1a000 { 321 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 322 reg = <0x01c1a000 0x100>; 323 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&ccu CLK_BUS_OHCI0>, 325 <&ccu CLK_BUS_EHCI0>, 326 <&ccu CLK_USB_OHCI0>; 327 resets = <&ccu RST_BUS_OHCI0>, 328 <&ccu RST_BUS_EHCI0>; 329 status = "disabled"; 330 }; 331 332 ohci0: usb@1c1a400 { 333 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 334 reg = <0x01c1a400 0x100>; 335 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&ccu CLK_BUS_OHCI0>, 337 <&ccu CLK_USB_OHCI0>; 338 resets = <&ccu RST_BUS_OHCI0>; 339 status = "disabled"; 340 }; 341 342 ehci1: usb@1c1b000 { 343 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 344 reg = <0x01c1b000 0x100>; 345 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&ccu CLK_BUS_OHCI1>, 347 <&ccu CLK_BUS_EHCI1>, 348 <&ccu CLK_USB_OHCI1>; 349 resets = <&ccu RST_BUS_OHCI1>, 350 <&ccu RST_BUS_EHCI1>; 351 phys = <&usbphy 1>; 352 phy-names = "usb"; 353 status = "disabled"; 354 }; 355 356 ohci1: usb@1c1b400 { 357 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 358 reg = <0x01c1b400 0x100>; 359 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&ccu CLK_BUS_OHCI1>, 361 <&ccu CLK_USB_OHCI1>; 362 resets = <&ccu RST_BUS_OHCI1>; 363 phys = <&usbphy 1>; 364 phy-names = "usb"; 365 status = "disabled"; 366 }; 367 368 ccu: clock@1c20000 { 369 compatible = "allwinner,sun50i-a64-ccu"; 370 reg = <0x01c20000 0x400>; 371 clocks = <&osc24M>, <&osc32k>; 372 clock-names = "hosc", "losc"; 373 #clock-cells = <1>; 374 #reset-cells = <1>; 375 }; 376 377 pio: pinctrl@1c20800 { 378 compatible = "allwinner,sun50i-a64-pinctrl"; 379 reg = <0x01c20800 0x400>; 380 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&ccu 58>; 384 gpio-controller; 385 #gpio-cells = <3>; 386 interrupt-controller; 387 #interrupt-cells = <3>; 388 389 i2c0_pins: i2c0_pins { 390 pins = "PH0", "PH1"; 391 function = "i2c0"; 392 }; 393 394 i2c1_pins: i2c1_pins { 395 pins = "PH2", "PH3"; 396 function = "i2c1"; 397 }; 398 399 mmc0_pins: mmc0-pins { 400 pins = "PF0", "PF1", "PF2", "PF3", 401 "PF4", "PF5"; 402 function = "mmc0"; 403 drive-strength = <30>; 404 bias-pull-up; 405 }; 406 407 mmc1_pins: mmc1-pins { 408 pins = "PG0", "PG1", "PG2", "PG3", 409 "PG4", "PG5"; 410 function = "mmc1"; 411 drive-strength = <30>; 412 bias-pull-up; 413 }; 414 415 mmc2_pins: mmc2-pins { 416 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 417 "PC10","PC11", "PC12", "PC13", 418 "PC14", "PC15", "PC16"; 419 function = "mmc2"; 420 drive-strength = <30>; 421 bias-pull-up; 422 }; 423 424 pwm_pin: pwm_pin { 425 pins = "PD22"; 426 function = "pwm"; 427 }; 428 429 rmii_pins: rmii_pins { 430 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 431 "PD18", "PD19", "PD20", "PD22", "PD23"; 432 function = "emac"; 433 drive-strength = <40>; 434 }; 435 436 rgmii_pins: rgmii_pins { 437 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 438 "PD13", "PD15", "PD16", "PD17", "PD18", 439 "PD19", "PD20", "PD21", "PD22", "PD23"; 440 function = "emac"; 441 drive-strength = <40>; 442 }; 443 444 spdif_tx_pin: spdif { 445 pins = "PH8"; 446 function = "spdif"; 447 }; 448 449 spi0_pins: spi0 { 450 pins = "PC0", "PC1", "PC2", "PC3"; 451 function = "spi0"; 452 }; 453 454 spi1_pins: spi1 { 455 pins = "PD0", "PD1", "PD2", "PD3"; 456 function = "spi1"; 457 }; 458 459 uart0_pins_a: uart0 { 460 pins = "PB8", "PB9"; 461 function = "uart0"; 462 }; 463 464 uart1_pins: uart1_pins { 465 pins = "PG6", "PG7"; 466 function = "uart1"; 467 }; 468 469 uart1_rts_cts_pins: uart1_rts_cts_pins { 470 pins = "PG8", "PG9"; 471 function = "uart1"; 472 }; 473 474 uart2_pins: uart2-pins { 475 pins = "PB0", "PB1"; 476 function = "uart2"; 477 }; 478 479 uart3_pins: uart3-pins { 480 pins = "PD0", "PD1"; 481 function = "uart3"; 482 }; 483 484 uart4_pins: uart4-pins { 485 pins = "PD2", "PD3"; 486 function = "uart4"; 487 }; 488 489 uart4_rts_cts_pins: uart4-rts-cts-pins { 490 pins = "PD4", "PD5"; 491 function = "uart4"; 492 }; 493 }; 494 495 spdif: spdif@1c21000 { 496 #sound-dai-cells = <0>; 497 compatible = "allwinner,sun50i-a64-spdif", 498 "allwinner,sun8i-h3-spdif"; 499 reg = <0x01c21000 0x400>; 500 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 502 resets = <&ccu RST_BUS_SPDIF>; 503 clock-names = "apb", "spdif"; 504 dmas = <&dma 2>; 505 dma-names = "tx"; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&spdif_tx_pin>; 508 status = "disabled"; 509 }; 510 511 i2s0: i2s@1c22000 { 512 #sound-dai-cells = <0>; 513 compatible = "allwinner,sun50i-a64-i2s", 514 "allwinner,sun8i-h3-i2s"; 515 reg = <0x01c22000 0x400>; 516 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 518 clock-names = "apb", "mod"; 519 resets = <&ccu RST_BUS_I2S0>; 520 dma-names = "rx", "tx"; 521 dmas = <&dma 3>, <&dma 3>; 522 status = "disabled"; 523 }; 524 525 i2s1: i2s@1c22400 { 526 #sound-dai-cells = <0>; 527 compatible = "allwinner,sun50i-a64-i2s", 528 "allwinner,sun8i-h3-i2s"; 529 reg = <0x01c22400 0x400>; 530 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 532 clock-names = "apb", "mod"; 533 resets = <&ccu RST_BUS_I2S1>; 534 dma-names = "rx", "tx"; 535 dmas = <&dma 4>, <&dma 4>; 536 status = "disabled"; 537 }; 538 539 uart0: serial@1c28000 { 540 compatible = "snps,dw-apb-uart"; 541 reg = <0x01c28000 0x400>; 542 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 543 reg-shift = <2>; 544 reg-io-width = <4>; 545 clocks = <&ccu CLK_BUS_UART0>; 546 resets = <&ccu RST_BUS_UART0>; 547 status = "disabled"; 548 }; 549 550 uart1: serial@1c28400 { 551 compatible = "snps,dw-apb-uart"; 552 reg = <0x01c28400 0x400>; 553 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 554 reg-shift = <2>; 555 reg-io-width = <4>; 556 clocks = <&ccu CLK_BUS_UART1>; 557 resets = <&ccu RST_BUS_UART1>; 558 status = "disabled"; 559 }; 560 561 uart2: serial@1c28800 { 562 compatible = "snps,dw-apb-uart"; 563 reg = <0x01c28800 0x400>; 564 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 565 reg-shift = <2>; 566 reg-io-width = <4>; 567 clocks = <&ccu CLK_BUS_UART2>; 568 resets = <&ccu RST_BUS_UART2>; 569 status = "disabled"; 570 }; 571 572 uart3: serial@1c28c00 { 573 compatible = "snps,dw-apb-uart"; 574 reg = <0x01c28c00 0x400>; 575 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 576 reg-shift = <2>; 577 reg-io-width = <4>; 578 clocks = <&ccu CLK_BUS_UART3>; 579 resets = <&ccu RST_BUS_UART3>; 580 status = "disabled"; 581 }; 582 583 uart4: serial@1c29000 { 584 compatible = "snps,dw-apb-uart"; 585 reg = <0x01c29000 0x400>; 586 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 587 reg-shift = <2>; 588 reg-io-width = <4>; 589 clocks = <&ccu CLK_BUS_UART4>; 590 resets = <&ccu RST_BUS_UART4>; 591 status = "disabled"; 592 }; 593 594 i2c0: i2c@1c2ac00 { 595 compatible = "allwinner,sun6i-a31-i2c"; 596 reg = <0x01c2ac00 0x400>; 597 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&ccu CLK_BUS_I2C0>; 599 resets = <&ccu RST_BUS_I2C0>; 600 status = "disabled"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 }; 604 605 i2c1: i2c@1c2b000 { 606 compatible = "allwinner,sun6i-a31-i2c"; 607 reg = <0x01c2b000 0x400>; 608 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&ccu CLK_BUS_I2C1>; 610 resets = <&ccu RST_BUS_I2C1>; 611 status = "disabled"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 }; 615 616 i2c2: i2c@1c2b400 { 617 compatible = "allwinner,sun6i-a31-i2c"; 618 reg = <0x01c2b400 0x400>; 619 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&ccu CLK_BUS_I2C2>; 621 resets = <&ccu RST_BUS_I2C2>; 622 status = "disabled"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 }; 626 627 628 spi0: spi@1c68000 { 629 compatible = "allwinner,sun8i-h3-spi"; 630 reg = <0x01c68000 0x1000>; 631 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 633 clock-names = "ahb", "mod"; 634 dmas = <&dma 23>, <&dma 23>; 635 dma-names = "rx", "tx"; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&spi0_pins>; 638 resets = <&ccu RST_BUS_SPI0>; 639 status = "disabled"; 640 num-cs = <1>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 }; 644 645 spi1: spi@1c69000 { 646 compatible = "allwinner,sun8i-h3-spi"; 647 reg = <0x01c69000 0x1000>; 648 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 650 clock-names = "ahb", "mod"; 651 dmas = <&dma 24>, <&dma 24>; 652 dma-names = "rx", "tx"; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&spi1_pins>; 655 resets = <&ccu RST_BUS_SPI1>; 656 status = "disabled"; 657 num-cs = <1>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 }; 661 662 emac: ethernet@1c30000 { 663 compatible = "allwinner,sun50i-a64-emac"; 664 syscon = <&syscon>; 665 reg = <0x01c30000 0x10000>; 666 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "macirq"; 668 resets = <&ccu RST_BUS_EMAC>; 669 reset-names = "stmmaceth"; 670 clocks = <&ccu CLK_BUS_EMAC>; 671 clock-names = "stmmaceth"; 672 status = "disabled"; 673 674 mdio: mdio { 675 compatible = "snps,dwmac-mdio"; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 }; 679 }; 680 681 gic: interrupt-controller@1c81000 { 682 compatible = "arm,gic-400"; 683 reg = <0x01c81000 0x1000>, 684 <0x01c82000 0x2000>, 685 <0x01c84000 0x2000>, 686 <0x01c86000 0x2000>; 687 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 688 interrupt-controller; 689 #interrupt-cells = <3>; 690 }; 691 692 pwm: pwm@1c21400 { 693 compatible = "allwinner,sun50i-a64-pwm", 694 "allwinner,sun5i-a13-pwm"; 695 reg = <0x01c21400 0x400>; 696 clocks = <&osc24M>; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pwm_pin>; 699 #pwm-cells = <3>; 700 status = "disabled"; 701 }; 702 703 rtc: rtc@1f00000 { 704 compatible = "allwinner,sun6i-a31-rtc"; 705 reg = <0x01f00000 0x54>; 706 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 708 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 709 clocks = <&osc32k>; 710 #clock-cells = <1>; 711 }; 712 713 r_intc: interrupt-controller@1f00c00 { 714 compatible = "allwinner,sun50i-a64-r-intc", 715 "allwinner,sun6i-a31-r-intc"; 716 interrupt-controller; 717 #interrupt-cells = <2>; 718 reg = <0x01f00c00 0x400>; 719 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 720 }; 721 722 r_ccu: clock@1f01400 { 723 compatible = "allwinner,sun50i-a64-r-ccu"; 724 reg = <0x01f01400 0x100>; 725 clocks = <&osc24M>, <&osc32k>, <&iosc>, 726 <&ccu 11>; 727 clock-names = "hosc", "losc", "iosc", "pll-periph"; 728 #clock-cells = <1>; 729 #reset-cells = <1>; 730 }; 731 732 r_i2c: i2c@1f02400 { 733 compatible = "allwinner,sun50i-a64-i2c", 734 "allwinner,sun6i-a31-i2c"; 735 reg = <0x01f02400 0x400>; 736 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&r_ccu CLK_APB0_I2C>; 738 resets = <&r_ccu RST_APB0_I2C>; 739 status = "disabled"; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 }; 743 744 r_pwm: pwm@1f03800 { 745 compatible = "allwinner,sun50i-a64-pwm", 746 "allwinner,sun5i-a13-pwm"; 747 reg = <0x01f03800 0x400>; 748 clocks = <&osc24M>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&r_pwm_pin>; 751 #pwm-cells = <3>; 752 status = "disabled"; 753 }; 754 755 r_pio: pinctrl@1f02c00 { 756 compatible = "allwinner,sun50i-a64-r-pinctrl"; 757 reg = <0x01f02c00 0x400>; 758 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 760 clock-names = "apb", "hosc", "losc"; 761 gpio-controller; 762 #gpio-cells = <3>; 763 interrupt-controller; 764 #interrupt-cells = <3>; 765 766 r_i2c_pins_a: i2c-a { 767 pins = "PL8", "PL9"; 768 function = "s_i2c"; 769 }; 770 771 r_pwm_pin: pwm { 772 pins = "PL10"; 773 function = "s_pwm"; 774 }; 775 776 r_rsb_pins: rsb { 777 pins = "PL0", "PL1"; 778 function = "s_rsb"; 779 }; 780 }; 781 782 r_rsb: rsb@1f03400 { 783 compatible = "allwinner,sun8i-a23-rsb"; 784 reg = <0x01f03400 0x400>; 785 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&r_ccu 6>; 787 clock-frequency = <3000000>; 788 resets = <&r_ccu 2>; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&r_rsb_pins>; 791 status = "disabled"; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 }; 795 796 wdt0: watchdog@1c20ca0 { 797 compatible = "allwinner,sun50i-a64-wdt", 798 "allwinner,sun6i-a31-wdt"; 799 reg = <0x01c20ca0 0x20>; 800 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 801 }; 802 }; 803}; 804