1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 interrupts = <GIC_PPI 13 204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 205 <GIC_PPI 14 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 10 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 211 }; 212 213 soc { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 de2@1000000 { 220 compatible = "allwinner,sun50i-a64-de2"; 221 reg = <0x1000000 0x400000>; 222 allwinner,sram = <&de2_sram 1>; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0 0x1000000 0x400000>; 226 227 display_clocks: clock@0 { 228 compatible = "allwinner,sun50i-a64-de2-clk"; 229 reg = <0x0 0x100000>; 230 clocks = <&ccu CLK_DE>, 231 <&ccu CLK_BUS_DE>; 232 clock-names = "mod", 233 "bus"; 234 resets = <&ccu RST_BUS_DE>; 235 #clock-cells = <1>; 236 #reset-cells = <1>; 237 }; 238 239 mixer0: mixer@100000 { 240 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 241 reg = <0x100000 0x100000>; 242 clocks = <&display_clocks CLK_BUS_MIXER0>, 243 <&display_clocks CLK_MIXER0>; 244 clock-names = "bus", 245 "mod"; 246 resets = <&display_clocks RST_MIXER0>; 247 248 ports { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 252 mixer0_out: port@1 { 253 reg = <1>; 254 255 mixer0_out_tcon0: endpoint { 256 remote-endpoint = <&tcon0_in_mixer0>; 257 }; 258 }; 259 }; 260 }; 261 262 mixer1: mixer@200000 { 263 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 264 reg = <0x200000 0x100000>; 265 clocks = <&display_clocks CLK_BUS_MIXER1>, 266 <&display_clocks CLK_MIXER1>; 267 clock-names = "bus", 268 "mod"; 269 resets = <&display_clocks RST_MIXER1>; 270 271 ports { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 mixer1_out: port@1 { 276 reg = <1>; 277 278 mixer1_out_tcon1: endpoint { 279 remote-endpoint = <&tcon1_in_mixer1>; 280 }; 281 }; 282 }; 283 }; 284 }; 285 286 syscon: syscon@1c00000 { 287 compatible = "allwinner,sun50i-a64-system-control"; 288 reg = <0x01c00000 0x1000>; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges; 292 293 sram_c: sram@18000 { 294 compatible = "mmio-sram"; 295 reg = <0x00018000 0x28000>; 296 #address-cells = <1>; 297 #size-cells = <1>; 298 ranges = <0 0x00018000 0x28000>; 299 300 de2_sram: sram-section@0 { 301 compatible = "allwinner,sun50i-a64-sram-c"; 302 reg = <0x0000 0x28000>; 303 }; 304 }; 305 306 sram_c1: sram@1d00000 { 307 compatible = "mmio-sram"; 308 reg = <0x01d00000 0x40000>; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 ranges = <0 0x01d00000 0x40000>; 312 313 ve_sram: sram-section@0 { 314 compatible = "allwinner,sun50i-a64-sram-c1", 315 "allwinner,sun4i-a10-sram-c1"; 316 reg = <0x000000 0x40000>; 317 }; 318 }; 319 }; 320 321 dma: dma-controller@1c02000 { 322 compatible = "allwinner,sun50i-a64-dma"; 323 reg = <0x01c02000 0x1000>; 324 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&ccu CLK_BUS_DMA>; 326 dma-channels = <8>; 327 dma-requests = <27>; 328 resets = <&ccu RST_BUS_DMA>; 329 #dma-cells = <1>; 330 }; 331 332 tcon0: lcd-controller@1c0c000 { 333 compatible = "allwinner,sun50i-a64-tcon-lcd", 334 "allwinner,sun8i-a83t-tcon-lcd"; 335 reg = <0x01c0c000 0x1000>; 336 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 338 clock-names = "ahb", "tcon-ch0"; 339 clock-output-names = "tcon-pixel-clock"; 340 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 341 reset-names = "lcd", "lvds"; 342 343 ports { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 tcon0_in: port@0 { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 reg = <0>; 351 352 tcon0_in_mixer0: endpoint@0 { 353 reg = <0>; 354 remote-endpoint = <&mixer0_out_tcon0>; 355 }; 356 }; 357 358 tcon0_out: port@1 { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 reg = <1>; 362 }; 363 }; 364 }; 365 366 tcon1: lcd-controller@1c0d000 { 367 compatible = "allwinner,sun50i-a64-tcon-tv", 368 "allwinner,sun8i-a83t-tcon-tv"; 369 reg = <0x01c0d000 0x1000>; 370 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 372 clock-names = "ahb", "tcon-ch1"; 373 resets = <&ccu RST_BUS_TCON1>; 374 reset-names = "lcd"; 375 376 ports { 377 #address-cells = <1>; 378 #size-cells = <0>; 379 380 tcon1_in: port@0 { 381 reg = <0>; 382 383 tcon1_in_mixer1: endpoint { 384 remote-endpoint = <&mixer1_out_tcon1>; 385 }; 386 }; 387 388 tcon1_out: port@1 { 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <1>; 392 393 tcon1_out_hdmi: endpoint@1 { 394 reg = <1>; 395 remote-endpoint = <&hdmi_in_tcon1>; 396 }; 397 }; 398 }; 399 }; 400 401 video-codec@1c0e000 { 402 compatible = "allwinner,sun50i-h5-video-engine"; 403 reg = <0x01c0e000 0x1000>; 404 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 405 <&ccu CLK_DRAM_VE>; 406 clock-names = "ahb", "mod", "ram"; 407 resets = <&ccu RST_BUS_VE>; 408 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 409 allwinner,sram = <&ve_sram 1>; 410 }; 411 412 mmc0: mmc@1c0f000 { 413 compatible = "allwinner,sun50i-a64-mmc"; 414 reg = <0x01c0f000 0x1000>; 415 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 416 clock-names = "ahb", "mmc"; 417 resets = <&ccu RST_BUS_MMC0>; 418 reset-names = "ahb"; 419 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 420 max-frequency = <150000000>; 421 status = "disabled"; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 }; 425 426 mmc1: mmc@1c10000 { 427 compatible = "allwinner,sun50i-a64-mmc"; 428 reg = <0x01c10000 0x1000>; 429 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 430 clock-names = "ahb", "mmc"; 431 resets = <&ccu RST_BUS_MMC1>; 432 reset-names = "ahb"; 433 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 434 max-frequency = <150000000>; 435 status = "disabled"; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 }; 439 440 mmc2: mmc@1c11000 { 441 compatible = "allwinner,sun50i-a64-emmc"; 442 reg = <0x01c11000 0x1000>; 443 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 444 clock-names = "ahb", "mmc"; 445 resets = <&ccu RST_BUS_MMC2>; 446 reset-names = "ahb"; 447 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 448 max-frequency = <200000000>; 449 status = "disabled"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 }; 453 454 sid: eeprom@1c14000 { 455 compatible = "allwinner,sun50i-a64-sid"; 456 reg = <0x1c14000 0x400>; 457 }; 458 459 usb_otg: usb@1c19000 { 460 compatible = "allwinner,sun8i-a33-musb"; 461 reg = <0x01c19000 0x0400>; 462 clocks = <&ccu CLK_BUS_OTG>; 463 resets = <&ccu RST_BUS_OTG>; 464 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "mc"; 466 phys = <&usbphy 0>; 467 phy-names = "usb"; 468 extcon = <&usbphy 0>; 469 status = "disabled"; 470 }; 471 472 usbphy: phy@1c19400 { 473 compatible = "allwinner,sun50i-a64-usb-phy"; 474 reg = <0x01c19400 0x14>, 475 <0x01c1a800 0x4>, 476 <0x01c1b800 0x4>; 477 reg-names = "phy_ctrl", 478 "pmu0", 479 "pmu1"; 480 clocks = <&ccu CLK_USB_PHY0>, 481 <&ccu CLK_USB_PHY1>; 482 clock-names = "usb0_phy", 483 "usb1_phy"; 484 resets = <&ccu RST_USB_PHY0>, 485 <&ccu RST_USB_PHY1>; 486 reset-names = "usb0_reset", 487 "usb1_reset"; 488 status = "disabled"; 489 #phy-cells = <1>; 490 }; 491 492 ehci0: usb@1c1a000 { 493 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 494 reg = <0x01c1a000 0x100>; 495 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&ccu CLK_BUS_OHCI0>, 497 <&ccu CLK_BUS_EHCI0>, 498 <&ccu CLK_USB_OHCI0>; 499 resets = <&ccu RST_BUS_OHCI0>, 500 <&ccu RST_BUS_EHCI0>; 501 status = "disabled"; 502 }; 503 504 ohci0: usb@1c1a400 { 505 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 506 reg = <0x01c1a400 0x100>; 507 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&ccu CLK_BUS_OHCI0>, 509 <&ccu CLK_USB_OHCI0>; 510 resets = <&ccu RST_BUS_OHCI0>; 511 status = "disabled"; 512 }; 513 514 ehci1: usb@1c1b000 { 515 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 516 reg = <0x01c1b000 0x100>; 517 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&ccu CLK_BUS_OHCI1>, 519 <&ccu CLK_BUS_EHCI1>, 520 <&ccu CLK_USB_OHCI1>; 521 resets = <&ccu RST_BUS_OHCI1>, 522 <&ccu RST_BUS_EHCI1>; 523 phys = <&usbphy 1>; 524 phy-names = "usb"; 525 status = "disabled"; 526 }; 527 528 ohci1: usb@1c1b400 { 529 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 530 reg = <0x01c1b400 0x100>; 531 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&ccu CLK_BUS_OHCI1>, 533 <&ccu CLK_USB_OHCI1>; 534 resets = <&ccu RST_BUS_OHCI1>; 535 phys = <&usbphy 1>; 536 phy-names = "usb"; 537 status = "disabled"; 538 }; 539 540 ccu: clock@1c20000 { 541 compatible = "allwinner,sun50i-a64-ccu"; 542 reg = <0x01c20000 0x400>; 543 clocks = <&osc24M>, <&rtc 0>; 544 clock-names = "hosc", "losc"; 545 #clock-cells = <1>; 546 #reset-cells = <1>; 547 }; 548 549 pio: pinctrl@1c20800 { 550 compatible = "allwinner,sun50i-a64-pinctrl"; 551 reg = <0x01c20800 0x400>; 552 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&ccu 58>; 556 gpio-controller; 557 #gpio-cells = <3>; 558 interrupt-controller; 559 #interrupt-cells = <3>; 560 561 i2c0_pins: i2c0_pins { 562 pins = "PH0", "PH1"; 563 function = "i2c0"; 564 }; 565 566 i2c1_pins: i2c1_pins { 567 pins = "PH2", "PH3"; 568 function = "i2c1"; 569 }; 570 571 mmc0_pins: mmc0-pins { 572 pins = "PF0", "PF1", "PF2", "PF3", 573 "PF4", "PF5"; 574 function = "mmc0"; 575 drive-strength = <30>; 576 bias-pull-up; 577 }; 578 579 mmc1_pins: mmc1-pins { 580 pins = "PG0", "PG1", "PG2", "PG3", 581 "PG4", "PG5"; 582 function = "mmc1"; 583 drive-strength = <30>; 584 bias-pull-up; 585 }; 586 587 mmc2_pins: mmc2-pins { 588 pins = "PC5", "PC6", "PC8", "PC9", 589 "PC10","PC11", "PC12", "PC13", 590 "PC14", "PC15", "PC16"; 591 function = "mmc2"; 592 drive-strength = <30>; 593 bias-pull-up; 594 }; 595 596 mmc2_ds_pin: mmc2-ds-pin { 597 pins = "PC1"; 598 function = "mmc2"; 599 drive-strength = <30>; 600 bias-pull-up; 601 }; 602 603 pwm_pin: pwm_pin { 604 pins = "PD22"; 605 function = "pwm"; 606 }; 607 608 rmii_pins: rmii_pins { 609 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 610 "PD18", "PD19", "PD20", "PD22", "PD23"; 611 function = "emac"; 612 drive-strength = <40>; 613 }; 614 615 rgmii_pins: rgmii_pins { 616 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 617 "PD13", "PD15", "PD16", "PD17", "PD18", 618 "PD19", "PD20", "PD21", "PD22", "PD23"; 619 function = "emac"; 620 drive-strength = <40>; 621 }; 622 623 spdif_tx_pin: spdif { 624 pins = "PH8"; 625 function = "spdif"; 626 }; 627 628 spi0_pins: spi0 { 629 pins = "PC0", "PC1", "PC2", "PC3"; 630 function = "spi0"; 631 }; 632 633 spi1_pins: spi1 { 634 pins = "PD0", "PD1", "PD2", "PD3"; 635 function = "spi1"; 636 }; 637 638 uart0_pb_pins: uart0-pb-pins { 639 pins = "PB8", "PB9"; 640 function = "uart0"; 641 }; 642 643 uart1_pins: uart1_pins { 644 pins = "PG6", "PG7"; 645 function = "uart1"; 646 }; 647 648 uart1_rts_cts_pins: uart1_rts_cts_pins { 649 pins = "PG8", "PG9"; 650 function = "uart1"; 651 }; 652 653 uart2_pins: uart2-pins { 654 pins = "PB0", "PB1"; 655 function = "uart2"; 656 }; 657 658 uart3_pins: uart3-pins { 659 pins = "PD0", "PD1"; 660 function = "uart3"; 661 }; 662 663 uart4_pins: uart4-pins { 664 pins = "PD2", "PD3"; 665 function = "uart4"; 666 }; 667 668 uart4_rts_cts_pins: uart4-rts-cts-pins { 669 pins = "PD4", "PD5"; 670 function = "uart4"; 671 }; 672 }; 673 674 spdif: spdif@1c21000 { 675 #sound-dai-cells = <0>; 676 compatible = "allwinner,sun50i-a64-spdif", 677 "allwinner,sun8i-h3-spdif"; 678 reg = <0x01c21000 0x400>; 679 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 681 resets = <&ccu RST_BUS_SPDIF>; 682 clock-names = "apb", "spdif"; 683 dmas = <&dma 2>; 684 dma-names = "tx"; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&spdif_tx_pin>; 687 status = "disabled"; 688 }; 689 690 i2s0: i2s@1c22000 { 691 #sound-dai-cells = <0>; 692 compatible = "allwinner,sun50i-a64-i2s", 693 "allwinner,sun8i-h3-i2s"; 694 reg = <0x01c22000 0x400>; 695 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 697 clock-names = "apb", "mod"; 698 resets = <&ccu RST_BUS_I2S0>; 699 dma-names = "rx", "tx"; 700 dmas = <&dma 3>, <&dma 3>; 701 status = "disabled"; 702 }; 703 704 i2s1: i2s@1c22400 { 705 #sound-dai-cells = <0>; 706 compatible = "allwinner,sun50i-a64-i2s", 707 "allwinner,sun8i-h3-i2s"; 708 reg = <0x01c22400 0x400>; 709 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 711 clock-names = "apb", "mod"; 712 resets = <&ccu RST_BUS_I2S1>; 713 dma-names = "rx", "tx"; 714 dmas = <&dma 4>, <&dma 4>; 715 status = "disabled"; 716 }; 717 718 dai: dai@1c22c00 { 719 #sound-dai-cells = <0>; 720 compatible = "allwinner,sun50i-a64-codec-i2s"; 721 reg = <0x01c22c00 0x200>; 722 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 724 clock-names = "apb", "mod"; 725 resets = <&ccu RST_BUS_CODEC>; 726 reset-names = "rst"; 727 dmas = <&dma 15>, <&dma 15>; 728 dma-names = "rx", "tx"; 729 status = "disabled"; 730 }; 731 732 codec: codec@1c22e00 { 733 #sound-dai-cells = <0>; 734 compatible = "allwinner,sun8i-a33-codec"; 735 reg = <0x01c22e00 0x600>; 736 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 738 clock-names = "bus", "mod"; 739 status = "disabled"; 740 }; 741 742 uart0: serial@1c28000 { 743 compatible = "snps,dw-apb-uart"; 744 reg = <0x01c28000 0x400>; 745 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 746 reg-shift = <2>; 747 reg-io-width = <4>; 748 clocks = <&ccu CLK_BUS_UART0>; 749 resets = <&ccu RST_BUS_UART0>; 750 status = "disabled"; 751 }; 752 753 uart1: serial@1c28400 { 754 compatible = "snps,dw-apb-uart"; 755 reg = <0x01c28400 0x400>; 756 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 757 reg-shift = <2>; 758 reg-io-width = <4>; 759 clocks = <&ccu CLK_BUS_UART1>; 760 resets = <&ccu RST_BUS_UART1>; 761 status = "disabled"; 762 }; 763 764 uart2: serial@1c28800 { 765 compatible = "snps,dw-apb-uart"; 766 reg = <0x01c28800 0x400>; 767 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 768 reg-shift = <2>; 769 reg-io-width = <4>; 770 clocks = <&ccu CLK_BUS_UART2>; 771 resets = <&ccu RST_BUS_UART2>; 772 status = "disabled"; 773 }; 774 775 uart3: serial@1c28c00 { 776 compatible = "snps,dw-apb-uart"; 777 reg = <0x01c28c00 0x400>; 778 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 779 reg-shift = <2>; 780 reg-io-width = <4>; 781 clocks = <&ccu CLK_BUS_UART3>; 782 resets = <&ccu RST_BUS_UART3>; 783 status = "disabled"; 784 }; 785 786 uart4: serial@1c29000 { 787 compatible = "snps,dw-apb-uart"; 788 reg = <0x01c29000 0x400>; 789 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 790 reg-shift = <2>; 791 reg-io-width = <4>; 792 clocks = <&ccu CLK_BUS_UART4>; 793 resets = <&ccu RST_BUS_UART4>; 794 status = "disabled"; 795 }; 796 797 i2c0: i2c@1c2ac00 { 798 compatible = "allwinner,sun6i-a31-i2c"; 799 reg = <0x01c2ac00 0x400>; 800 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&ccu CLK_BUS_I2C0>; 802 resets = <&ccu RST_BUS_I2C0>; 803 status = "disabled"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 }; 807 808 i2c1: i2c@1c2b000 { 809 compatible = "allwinner,sun6i-a31-i2c"; 810 reg = <0x01c2b000 0x400>; 811 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&ccu CLK_BUS_I2C1>; 813 resets = <&ccu RST_BUS_I2C1>; 814 status = "disabled"; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 }; 818 819 i2c2: i2c@1c2b400 { 820 compatible = "allwinner,sun6i-a31-i2c"; 821 reg = <0x01c2b400 0x400>; 822 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&ccu CLK_BUS_I2C2>; 824 resets = <&ccu RST_BUS_I2C2>; 825 status = "disabled"; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 }; 829 830 831 spi0: spi@1c68000 { 832 compatible = "allwinner,sun8i-h3-spi"; 833 reg = <0x01c68000 0x1000>; 834 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 836 clock-names = "ahb", "mod"; 837 dmas = <&dma 23>, <&dma 23>; 838 dma-names = "rx", "tx"; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&spi0_pins>; 841 resets = <&ccu RST_BUS_SPI0>; 842 status = "disabled"; 843 num-cs = <1>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 }; 847 848 spi1: spi@1c69000 { 849 compatible = "allwinner,sun8i-h3-spi"; 850 reg = <0x01c69000 0x1000>; 851 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 853 clock-names = "ahb", "mod"; 854 dmas = <&dma 24>, <&dma 24>; 855 dma-names = "rx", "tx"; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&spi1_pins>; 858 resets = <&ccu RST_BUS_SPI1>; 859 status = "disabled"; 860 num-cs = <1>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 }; 864 865 emac: ethernet@1c30000 { 866 compatible = "allwinner,sun50i-a64-emac"; 867 syscon = <&syscon>; 868 reg = <0x01c30000 0x10000>; 869 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "macirq"; 871 resets = <&ccu RST_BUS_EMAC>; 872 reset-names = "stmmaceth"; 873 clocks = <&ccu CLK_BUS_EMAC>; 874 clock-names = "stmmaceth"; 875 status = "disabled"; 876 877 mdio: mdio { 878 compatible = "snps,dwmac-mdio"; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 }; 882 }; 883 884 mali: gpu@1c40000 { 885 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 886 reg = <0x01c40000 0x10000>; 887 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 894 interrupt-names = "gp", 895 "gpmmu", 896 "pp0", 897 "ppmmu0", 898 "pp1", 899 "ppmmu1", 900 "pmu"; 901 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 902 clock-names = "bus", "core"; 903 resets = <&ccu RST_BUS_GPU>; 904 }; 905 906 gic: interrupt-controller@1c81000 { 907 compatible = "arm,gic-400"; 908 reg = <0x01c81000 0x1000>, 909 <0x01c82000 0x2000>, 910 <0x01c84000 0x2000>, 911 <0x01c86000 0x2000>; 912 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 913 interrupt-controller; 914 #interrupt-cells = <3>; 915 }; 916 917 pwm: pwm@1c21400 { 918 compatible = "allwinner,sun50i-a64-pwm", 919 "allwinner,sun5i-a13-pwm"; 920 reg = <0x01c21400 0x400>; 921 clocks = <&osc24M>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&pwm_pin>; 924 #pwm-cells = <3>; 925 status = "disabled"; 926 }; 927 928 hdmi: hdmi@1ee0000 { 929 compatible = "allwinner,sun50i-a64-dw-hdmi", 930 "allwinner,sun8i-a83t-dw-hdmi"; 931 reg = <0x01ee0000 0x10000>; 932 reg-io-width = <1>; 933 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 935 <&ccu CLK_HDMI>; 936 clock-names = "iahb", "isfr", "tmds"; 937 resets = <&ccu RST_BUS_HDMI1>; 938 reset-names = "ctrl"; 939 phys = <&hdmi_phy>; 940 phy-names = "hdmi-phy"; 941 status = "disabled"; 942 943 ports { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 hdmi_in: port@0 { 948 reg = <0>; 949 950 hdmi_in_tcon1: endpoint { 951 remote-endpoint = <&tcon1_out_hdmi>; 952 }; 953 }; 954 955 hdmi_out: port@1 { 956 reg = <1>; 957 }; 958 }; 959 }; 960 961 hdmi_phy: hdmi-phy@1ef0000 { 962 compatible = "allwinner,sun50i-a64-hdmi-phy"; 963 reg = <0x01ef0000 0x10000>; 964 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 965 <&ccu 7>; 966 clock-names = "bus", "mod", "pll-0"; 967 resets = <&ccu RST_BUS_HDMI0>; 968 reset-names = "phy"; 969 #phy-cells = <0>; 970 }; 971 972 rtc: rtc@1f00000 { 973 compatible = "allwinner,sun50i-a64-rtc", 974 "allwinner,sun8i-h3-rtc"; 975 reg = <0x01f00000 0x400>; 976 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 978 clock-output-names = "osc32k", "osc32k-out", "iosc"; 979 clocks = <&osc32k>; 980 #clock-cells = <1>; 981 }; 982 983 r_intc: interrupt-controller@1f00c00 { 984 compatible = "allwinner,sun50i-a64-r-intc", 985 "allwinner,sun6i-a31-r-intc"; 986 interrupt-controller; 987 #interrupt-cells = <2>; 988 reg = <0x01f00c00 0x400>; 989 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 990 }; 991 992 r_ccu: clock@1f01400 { 993 compatible = "allwinner,sun50i-a64-r-ccu"; 994 reg = <0x01f01400 0x100>; 995 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 996 clock-names = "hosc", "losc", "iosc", "pll-periph"; 997 #clock-cells = <1>; 998 #reset-cells = <1>; 999 }; 1000 1001 codec_analog: codec-analog@1f015c0 { 1002 compatible = "allwinner,sun50i-a64-codec-analog"; 1003 reg = <0x01f015c0 0x4>; 1004 status = "disabled"; 1005 }; 1006 1007 r_i2c: i2c@1f02400 { 1008 compatible = "allwinner,sun50i-a64-i2c", 1009 "allwinner,sun6i-a31-i2c"; 1010 reg = <0x01f02400 0x400>; 1011 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&r_ccu CLK_APB0_I2C>; 1013 resets = <&r_ccu RST_APB0_I2C>; 1014 status = "disabled"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 }; 1018 1019 r_pwm: pwm@1f03800 { 1020 compatible = "allwinner,sun50i-a64-pwm", 1021 "allwinner,sun5i-a13-pwm"; 1022 reg = <0x01f03800 0x400>; 1023 clocks = <&osc24M>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&r_pwm_pin>; 1026 #pwm-cells = <3>; 1027 status = "disabled"; 1028 }; 1029 1030 r_pio: pinctrl@1f02c00 { 1031 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1032 reg = <0x01f02c00 0x400>; 1033 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1035 clock-names = "apb", "hosc", "losc"; 1036 gpio-controller; 1037 #gpio-cells = <3>; 1038 interrupt-controller; 1039 #interrupt-cells = <3>; 1040 1041 r_i2c_pl89_pins: r-i2c-pl89-pins { 1042 pins = "PL8", "PL9"; 1043 function = "s_i2c"; 1044 }; 1045 1046 r_pwm_pin: pwm { 1047 pins = "PL10"; 1048 function = "s_pwm"; 1049 }; 1050 1051 r_rsb_pins: rsb { 1052 pins = "PL0", "PL1"; 1053 function = "s_rsb"; 1054 }; 1055 }; 1056 1057 r_rsb: rsb@1f03400 { 1058 compatible = "allwinner,sun8i-a23-rsb"; 1059 reg = <0x01f03400 0x400>; 1060 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&r_ccu 6>; 1062 clock-frequency = <3000000>; 1063 resets = <&r_ccu 2>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&r_rsb_pins>; 1066 status = "disabled"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 }; 1070 1071 wdt0: watchdog@1c20ca0 { 1072 compatible = "allwinner,sun50i-a64-wdt", 1073 "allwinner,sun6i-a31-wdt"; 1074 reg = <0x01c20ca0 0x20>; 1075 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1076 }; 1077 }; 1078}; 1079