1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu0: cpu@0 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0>; 81 enable-method = "psci"; 82 }; 83 84 cpu1: cpu@1 { 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <1>; 88 enable-method = "psci"; 89 }; 90 91 cpu2: cpu@2 { 92 compatible = "arm,cortex-a53", "arm,armv8"; 93 device_type = "cpu"; 94 reg = <2>; 95 enable-method = "psci"; 96 }; 97 98 cpu3: cpu@3 { 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 device_type = "cpu"; 101 reg = <3>; 102 enable-method = "psci"; 103 }; 104 }; 105 106 osc24M: osc24M_clk { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 clock-frequency = <24000000>; 110 clock-output-names = "osc24M"; 111 }; 112 113 osc32k: osc32k_clk { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-frequency = <32768>; 117 clock-output-names = "osc32k"; 118 }; 119 120 iosc: internal-osc-clk { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 clock-frequency = <16000000>; 124 clock-accuracy = <300000000>; 125 clock-output-names = "iosc"; 126 }; 127 128 psci { 129 compatible = "arm,psci-0.2"; 130 method = "smc"; 131 }; 132 133 sound_spdif { 134 compatible = "simple-audio-card"; 135 simple-audio-card,name = "On-board SPDIF"; 136 137 simple-audio-card,cpu { 138 sound-dai = <&spdif>; 139 }; 140 141 simple-audio-card,codec { 142 sound-dai = <&spdif_out>; 143 }; 144 }; 145 146 spdif_out: spdif-out { 147 #sound-dai-cells = <0>; 148 compatible = "linux,spdif-dit"; 149 }; 150 151 timer { 152 compatible = "arm,armv8-timer"; 153 interrupts = <GIC_PPI 13 154 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 14 156 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 159 <GIC_PPI 10 160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 161 }; 162 163 soc { 164 compatible = "simple-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges; 168 169 de2@1000000 { 170 compatible = "allwinner,sun50i-a64-de2"; 171 reg = <0x1000000 0x400000>; 172 allwinner,sram = <&de2_sram 1>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0 0x1000000 0x400000>; 176 177 display_clocks: clock@0 { 178 compatible = "allwinner,sun50i-a64-de2-clk"; 179 reg = <0x0 0x100000>; 180 clocks = <&ccu CLK_DE>, 181 <&ccu CLK_BUS_DE>; 182 clock-names = "mod", 183 "bus"; 184 resets = <&ccu RST_BUS_DE>; 185 #clock-cells = <1>; 186 #reset-cells = <1>; 187 }; 188 }; 189 190 syscon: syscon@1c00000 { 191 compatible = "allwinner,sun50i-a64-system-control"; 192 reg = <0x01c00000 0x1000>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges; 196 197 sram_c: sram@18000 { 198 compatible = "mmio-sram"; 199 reg = <0x00018000 0x28000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 ranges = <0 0x00018000 0x28000>; 203 204 de2_sram: sram-section@0 { 205 compatible = "allwinner,sun50i-a64-sram-c"; 206 reg = <0x0000 0x28000>; 207 }; 208 }; 209 }; 210 211 dma: dma-controller@1c02000 { 212 compatible = "allwinner,sun50i-a64-dma"; 213 reg = <0x01c02000 0x1000>; 214 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&ccu CLK_BUS_DMA>; 216 dma-channels = <8>; 217 dma-requests = <27>; 218 resets = <&ccu RST_BUS_DMA>; 219 #dma-cells = <1>; 220 }; 221 222 mmc0: mmc@1c0f000 { 223 compatible = "allwinner,sun50i-a64-mmc"; 224 reg = <0x01c0f000 0x1000>; 225 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 226 clock-names = "ahb", "mmc"; 227 resets = <&ccu RST_BUS_MMC0>; 228 reset-names = "ahb"; 229 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 230 max-frequency = <150000000>; 231 status = "disabled"; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 }; 235 236 mmc1: mmc@1c10000 { 237 compatible = "allwinner,sun50i-a64-mmc"; 238 reg = <0x01c10000 0x1000>; 239 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 240 clock-names = "ahb", "mmc"; 241 resets = <&ccu RST_BUS_MMC1>; 242 reset-names = "ahb"; 243 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 244 max-frequency = <150000000>; 245 status = "disabled"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 }; 249 250 mmc2: mmc@1c11000 { 251 compatible = "allwinner,sun50i-a64-emmc"; 252 reg = <0x01c11000 0x1000>; 253 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 254 clock-names = "ahb", "mmc"; 255 resets = <&ccu RST_BUS_MMC2>; 256 reset-names = "ahb"; 257 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 258 max-frequency = <200000000>; 259 status = "disabled"; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 }; 263 264 usb_otg: usb@1c19000 { 265 compatible = "allwinner,sun8i-a33-musb"; 266 reg = <0x01c19000 0x0400>; 267 clocks = <&ccu CLK_BUS_OTG>; 268 resets = <&ccu RST_BUS_OTG>; 269 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-names = "mc"; 271 phys = <&usbphy 0>; 272 phy-names = "usb"; 273 extcon = <&usbphy 0>; 274 status = "disabled"; 275 }; 276 277 usbphy: phy@1c19400 { 278 compatible = "allwinner,sun50i-a64-usb-phy"; 279 reg = <0x01c19400 0x14>, 280 <0x01c1a800 0x4>, 281 <0x01c1b800 0x4>; 282 reg-names = "phy_ctrl", 283 "pmu0", 284 "pmu1"; 285 clocks = <&ccu CLK_USB_PHY0>, 286 <&ccu CLK_USB_PHY1>; 287 clock-names = "usb0_phy", 288 "usb1_phy"; 289 resets = <&ccu RST_USB_PHY0>, 290 <&ccu RST_USB_PHY1>; 291 reset-names = "usb0_reset", 292 "usb1_reset"; 293 status = "disabled"; 294 #phy-cells = <1>; 295 }; 296 297 ehci0: usb@1c1a000 { 298 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 299 reg = <0x01c1a000 0x100>; 300 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&ccu CLK_BUS_OHCI0>, 302 <&ccu CLK_BUS_EHCI0>, 303 <&ccu CLK_USB_OHCI0>; 304 resets = <&ccu RST_BUS_OHCI0>, 305 <&ccu RST_BUS_EHCI0>; 306 status = "disabled"; 307 }; 308 309 ohci0: usb@1c1a400 { 310 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 311 reg = <0x01c1a400 0x100>; 312 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&ccu CLK_BUS_OHCI0>, 314 <&ccu CLK_USB_OHCI0>; 315 resets = <&ccu RST_BUS_OHCI0>; 316 status = "disabled"; 317 }; 318 319 ehci1: usb@1c1b000 { 320 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 321 reg = <0x01c1b000 0x100>; 322 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&ccu CLK_BUS_OHCI1>, 324 <&ccu CLK_BUS_EHCI1>, 325 <&ccu CLK_USB_OHCI1>; 326 resets = <&ccu RST_BUS_OHCI1>, 327 <&ccu RST_BUS_EHCI1>; 328 phys = <&usbphy 1>; 329 phy-names = "usb"; 330 status = "disabled"; 331 }; 332 333 ohci1: usb@1c1b400 { 334 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 335 reg = <0x01c1b400 0x100>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&ccu CLK_BUS_OHCI1>, 338 <&ccu CLK_USB_OHCI1>; 339 resets = <&ccu RST_BUS_OHCI1>; 340 phys = <&usbphy 1>; 341 phy-names = "usb"; 342 status = "disabled"; 343 }; 344 345 ccu: clock@1c20000 { 346 compatible = "allwinner,sun50i-a64-ccu"; 347 reg = <0x01c20000 0x400>; 348 clocks = <&osc24M>, <&osc32k>; 349 clock-names = "hosc", "losc"; 350 #clock-cells = <1>; 351 #reset-cells = <1>; 352 }; 353 354 pio: pinctrl@1c20800 { 355 compatible = "allwinner,sun50i-a64-pinctrl"; 356 reg = <0x01c20800 0x400>; 357 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&ccu 58>; 361 gpio-controller; 362 #gpio-cells = <3>; 363 interrupt-controller; 364 #interrupt-cells = <3>; 365 366 i2c0_pins: i2c0_pins { 367 pins = "PH0", "PH1"; 368 function = "i2c0"; 369 }; 370 371 i2c1_pins: i2c1_pins { 372 pins = "PH2", "PH3"; 373 function = "i2c1"; 374 }; 375 376 mmc0_pins: mmc0-pins { 377 pins = "PF0", "PF1", "PF2", "PF3", 378 "PF4", "PF5"; 379 function = "mmc0"; 380 drive-strength = <30>; 381 bias-pull-up; 382 }; 383 384 mmc1_pins: mmc1-pins { 385 pins = "PG0", "PG1", "PG2", "PG3", 386 "PG4", "PG5"; 387 function = "mmc1"; 388 drive-strength = <30>; 389 bias-pull-up; 390 }; 391 392 mmc2_pins: mmc2-pins { 393 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 394 "PC10","PC11", "PC12", "PC13", 395 "PC14", "PC15", "PC16"; 396 function = "mmc2"; 397 drive-strength = <30>; 398 bias-pull-up; 399 }; 400 401 pwm_pin: pwm_pin { 402 pins = "PD22"; 403 function = "pwm"; 404 }; 405 406 rmii_pins: rmii_pins { 407 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 408 "PD18", "PD19", "PD20", "PD22", "PD23"; 409 function = "emac"; 410 drive-strength = <40>; 411 }; 412 413 rgmii_pins: rgmii_pins { 414 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 415 "PD13", "PD15", "PD16", "PD17", "PD18", 416 "PD19", "PD20", "PD21", "PD22", "PD23"; 417 function = "emac"; 418 drive-strength = <40>; 419 }; 420 421 spdif_tx_pin: spdif { 422 pins = "PH8"; 423 function = "spdif"; 424 }; 425 426 spi0_pins: spi0 { 427 pins = "PC0", "PC1", "PC2", "PC3"; 428 function = "spi0"; 429 }; 430 431 spi1_pins: spi1 { 432 pins = "PD0", "PD1", "PD2", "PD3"; 433 function = "spi1"; 434 }; 435 436 uart0_pins_a: uart0 { 437 pins = "PB8", "PB9"; 438 function = "uart0"; 439 }; 440 441 uart1_pins: uart1_pins { 442 pins = "PG6", "PG7"; 443 function = "uart1"; 444 }; 445 446 uart1_rts_cts_pins: uart1_rts_cts_pins { 447 pins = "PG8", "PG9"; 448 function = "uart1"; 449 }; 450 451 uart2_pins: uart2-pins { 452 pins = "PB0", "PB1"; 453 function = "uart2"; 454 }; 455 456 uart3_pins: uart3-pins { 457 pins = "PD0", "PD1"; 458 function = "uart3"; 459 }; 460 461 uart4_pins: uart4-pins { 462 pins = "PD2", "PD3"; 463 function = "uart4"; 464 }; 465 466 uart4_rts_cts_pins: uart4-rts-cts-pins { 467 pins = "PD4", "PD5"; 468 function = "uart4"; 469 }; 470 }; 471 472 spdif: spdif@1c21000 { 473 #sound-dai-cells = <0>; 474 compatible = "allwinner,sun50i-a64-spdif", 475 "allwinner,sun8i-h3-spdif"; 476 reg = <0x01c21000 0x400>; 477 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 479 resets = <&ccu RST_BUS_SPDIF>; 480 clock-names = "apb", "spdif"; 481 dmas = <&dma 2>; 482 dma-names = "tx"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&spdif_tx_pin>; 485 status = "disabled"; 486 }; 487 488 i2s0: i2s@1c22000 { 489 #sound-dai-cells = <0>; 490 compatible = "allwinner,sun50i-a64-i2s", 491 "allwinner,sun8i-h3-i2s"; 492 reg = <0x01c22000 0x400>; 493 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 495 clock-names = "apb", "mod"; 496 resets = <&ccu RST_BUS_I2S0>; 497 dma-names = "rx", "tx"; 498 dmas = <&dma 3>, <&dma 3>; 499 status = "disabled"; 500 }; 501 502 i2s1: i2s@1c22400 { 503 #sound-dai-cells = <0>; 504 compatible = "allwinner,sun50i-a64-i2s", 505 "allwinner,sun8i-h3-i2s"; 506 reg = <0x01c22400 0x400>; 507 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 509 clock-names = "apb", "mod"; 510 resets = <&ccu RST_BUS_I2S1>; 511 dma-names = "rx", "tx"; 512 dmas = <&dma 4>, <&dma 4>; 513 status = "disabled"; 514 }; 515 516 uart0: serial@1c28000 { 517 compatible = "snps,dw-apb-uart"; 518 reg = <0x01c28000 0x400>; 519 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 520 reg-shift = <2>; 521 reg-io-width = <4>; 522 clocks = <&ccu CLK_BUS_UART0>; 523 resets = <&ccu RST_BUS_UART0>; 524 status = "disabled"; 525 }; 526 527 uart1: serial@1c28400 { 528 compatible = "snps,dw-apb-uart"; 529 reg = <0x01c28400 0x400>; 530 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 531 reg-shift = <2>; 532 reg-io-width = <4>; 533 clocks = <&ccu CLK_BUS_UART1>; 534 resets = <&ccu RST_BUS_UART1>; 535 status = "disabled"; 536 }; 537 538 uart2: serial@1c28800 { 539 compatible = "snps,dw-apb-uart"; 540 reg = <0x01c28800 0x400>; 541 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 542 reg-shift = <2>; 543 reg-io-width = <4>; 544 clocks = <&ccu CLK_BUS_UART2>; 545 resets = <&ccu RST_BUS_UART2>; 546 status = "disabled"; 547 }; 548 549 uart3: serial@1c28c00 { 550 compatible = "snps,dw-apb-uart"; 551 reg = <0x01c28c00 0x400>; 552 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 553 reg-shift = <2>; 554 reg-io-width = <4>; 555 clocks = <&ccu CLK_BUS_UART3>; 556 resets = <&ccu RST_BUS_UART3>; 557 status = "disabled"; 558 }; 559 560 uart4: serial@1c29000 { 561 compatible = "snps,dw-apb-uart"; 562 reg = <0x01c29000 0x400>; 563 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 564 reg-shift = <2>; 565 reg-io-width = <4>; 566 clocks = <&ccu CLK_BUS_UART4>; 567 resets = <&ccu RST_BUS_UART4>; 568 status = "disabled"; 569 }; 570 571 i2c0: i2c@1c2ac00 { 572 compatible = "allwinner,sun6i-a31-i2c"; 573 reg = <0x01c2ac00 0x400>; 574 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&ccu CLK_BUS_I2C0>; 576 resets = <&ccu RST_BUS_I2C0>; 577 status = "disabled"; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 }; 581 582 i2c1: i2c@1c2b000 { 583 compatible = "allwinner,sun6i-a31-i2c"; 584 reg = <0x01c2b000 0x400>; 585 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&ccu CLK_BUS_I2C1>; 587 resets = <&ccu RST_BUS_I2C1>; 588 status = "disabled"; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 }; 592 593 i2c2: i2c@1c2b400 { 594 compatible = "allwinner,sun6i-a31-i2c"; 595 reg = <0x01c2b400 0x400>; 596 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&ccu CLK_BUS_I2C2>; 598 resets = <&ccu RST_BUS_I2C2>; 599 status = "disabled"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 }; 603 604 605 spi0: spi@1c68000 { 606 compatible = "allwinner,sun8i-h3-spi"; 607 reg = <0x01c68000 0x1000>; 608 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 610 clock-names = "ahb", "mod"; 611 dmas = <&dma 23>, <&dma 23>; 612 dma-names = "rx", "tx"; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&spi0_pins>; 615 resets = <&ccu RST_BUS_SPI0>; 616 status = "disabled"; 617 num-cs = <1>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 }; 621 622 spi1: spi@1c69000 { 623 compatible = "allwinner,sun8i-h3-spi"; 624 reg = <0x01c69000 0x1000>; 625 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 627 clock-names = "ahb", "mod"; 628 dmas = <&dma 24>, <&dma 24>; 629 dma-names = "rx", "tx"; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&spi1_pins>; 632 resets = <&ccu RST_BUS_SPI1>; 633 status = "disabled"; 634 num-cs = <1>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 }; 638 639 emac: ethernet@1c30000 { 640 compatible = "allwinner,sun50i-a64-emac"; 641 syscon = <&syscon>; 642 reg = <0x01c30000 0x10000>; 643 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "macirq"; 645 resets = <&ccu RST_BUS_EMAC>; 646 reset-names = "stmmaceth"; 647 clocks = <&ccu CLK_BUS_EMAC>; 648 clock-names = "stmmaceth"; 649 status = "disabled"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 653 mdio: mdio { 654 compatible = "snps,dwmac-mdio"; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 }; 658 }; 659 660 gic: interrupt-controller@1c81000 { 661 compatible = "arm,gic-400"; 662 reg = <0x01c81000 0x1000>, 663 <0x01c82000 0x2000>, 664 <0x01c84000 0x2000>, 665 <0x01c86000 0x2000>; 666 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 667 interrupt-controller; 668 #interrupt-cells = <3>; 669 }; 670 671 pwm: pwm@1c21400 { 672 compatible = "allwinner,sun50i-a64-pwm", 673 "allwinner,sun5i-a13-pwm"; 674 reg = <0x01c21400 0x400>; 675 clocks = <&osc24M>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&pwm_pin>; 678 #pwm-cells = <3>; 679 status = "disabled"; 680 }; 681 682 rtc: rtc@1f00000 { 683 compatible = "allwinner,sun6i-a31-rtc"; 684 reg = <0x01f00000 0x54>; 685 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 687 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 688 clocks = <&osc32k>; 689 #clock-cells = <1>; 690 }; 691 692 r_intc: interrupt-controller@1f00c00 { 693 compatible = "allwinner,sun50i-a64-r-intc", 694 "allwinner,sun6i-a31-r-intc"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 reg = <0x01f00c00 0x400>; 698 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 699 }; 700 701 r_ccu: clock@1f01400 { 702 compatible = "allwinner,sun50i-a64-r-ccu"; 703 reg = <0x01f01400 0x100>; 704 clocks = <&osc24M>, <&osc32k>, <&iosc>, 705 <&ccu 11>; 706 clock-names = "hosc", "losc", "iosc", "pll-periph"; 707 #clock-cells = <1>; 708 #reset-cells = <1>; 709 }; 710 711 r_i2c: i2c@1f02400 { 712 compatible = "allwinner,sun50i-a64-i2c", 713 "allwinner,sun6i-a31-i2c"; 714 reg = <0x01f02400 0x400>; 715 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&r_ccu CLK_APB0_I2C>; 717 resets = <&r_ccu RST_APB0_I2C>; 718 status = "disabled"; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 }; 722 723 r_pwm: pwm@1f03800 { 724 compatible = "allwinner,sun50i-a64-pwm", 725 "allwinner,sun5i-a13-pwm"; 726 reg = <0x01f03800 0x400>; 727 clocks = <&osc24M>; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&r_pwm_pin>; 730 #pwm-cells = <3>; 731 status = "disabled"; 732 }; 733 734 r_pio: pinctrl@1f02c00 { 735 compatible = "allwinner,sun50i-a64-r-pinctrl"; 736 reg = <0x01f02c00 0x400>; 737 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 739 clock-names = "apb", "hosc", "losc"; 740 gpio-controller; 741 #gpio-cells = <3>; 742 interrupt-controller; 743 #interrupt-cells = <3>; 744 745 r_i2c_pins_a: i2c-a { 746 pins = "PL8", "PL9"; 747 function = "s_i2c"; 748 }; 749 750 r_pwm_pin: pwm { 751 pins = "PL10"; 752 function = "s_pwm"; 753 }; 754 755 r_rsb_pins: rsb { 756 pins = "PL0", "PL1"; 757 function = "s_rsb"; 758 }; 759 }; 760 761 r_rsb: rsb@1f03400 { 762 compatible = "allwinner,sun8i-a23-rsb"; 763 reg = <0x01f03400 0x400>; 764 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&r_ccu 6>; 766 clock-frequency = <3000000>; 767 resets = <&r_ccu 2>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&r_rsb_pins>; 770 status = "disabled"; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 }; 774 775 wdt0: watchdog@1c20ca0 { 776 compatible = "allwinner,sun50i-a64-wdt", 777 "allwinner,sun6i-a31-wdt"; 778 reg = <0x01c20ca0 0x20>; 779 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 780 }; 781 }; 782}; 783