1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 de2@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_DE>, 232 <&ccu CLK_BUS_DE>; 233 clock-names = "mod", 234 "bus"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <1>; 257 258 mixer0_out_tcon0: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&tcon0_in_mixer0>; 261 }; 262 263 mixer0_out_tcon1: endpoint@1 { 264 reg = <1>; 265 remote-endpoint = <&tcon1_in_mixer0>; 266 }; 267 }; 268 }; 269 }; 270 271 mixer1: mixer@200000 { 272 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273 reg = <0x200000 0x100000>; 274 clocks = <&display_clocks CLK_BUS_MIXER1>, 275 <&display_clocks CLK_MIXER1>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&display_clocks RST_MIXER1>; 279 280 ports { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 mixer1_out: port@1 { 285 reg = <1>; 286 287 mixer1_out_tcon0: endpoint@0 { 288 reg = <0>; 289 remote-endpoint = <&tcon0_in_mixer1>; 290 }; 291 292 mixer1_out_tcon1: endpoint@1 { 293 reg = <1>; 294 remote-endpoint = <&tcon1_in_mixer1>; 295 }; 296 }; 297 }; 298 }; 299 }; 300 301 syscon: syscon@1c00000 { 302 compatible = "allwinner,sun50i-a64-system-control"; 303 reg = <0x01c00000 0x1000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges; 307 308 sram_c: sram@18000 { 309 compatible = "mmio-sram"; 310 reg = <0x00018000 0x28000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0 0x00018000 0x28000>; 314 315 de2_sram: sram-section@0 { 316 compatible = "allwinner,sun50i-a64-sram-c"; 317 reg = <0x0000 0x28000>; 318 }; 319 }; 320 321 sram_c1: sram@1d00000 { 322 compatible = "mmio-sram"; 323 reg = <0x01d00000 0x40000>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges = <0 0x01d00000 0x40000>; 327 328 ve_sram: sram-section@0 { 329 compatible = "allwinner,sun50i-a64-sram-c1", 330 "allwinner,sun4i-a10-sram-c1"; 331 reg = <0x000000 0x40000>; 332 }; 333 }; 334 }; 335 336 dma: dma-controller@1c02000 { 337 compatible = "allwinner,sun50i-a64-dma"; 338 reg = <0x01c02000 0x1000>; 339 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&ccu CLK_BUS_DMA>; 341 dma-channels = <8>; 342 dma-requests = <27>; 343 resets = <&ccu RST_BUS_DMA>; 344 #dma-cells = <1>; 345 }; 346 347 tcon0: lcd-controller@1c0c000 { 348 compatible = "allwinner,sun50i-a64-tcon-lcd", 349 "allwinner,sun8i-a83t-tcon-lcd"; 350 reg = <0x01c0c000 0x1000>; 351 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 353 clock-names = "ahb", "tcon-ch0"; 354 clock-output-names = "tcon-pixel-clock"; 355 #clock-cells = <0>; 356 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 357 reset-names = "lcd", "lvds"; 358 359 ports { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 tcon0_in: port@0 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 reg = <0>; 367 368 tcon0_in_mixer0: endpoint@0 { 369 reg = <0>; 370 remote-endpoint = <&mixer0_out_tcon0>; 371 }; 372 373 tcon0_in_mixer1: endpoint@1 { 374 reg = <1>; 375 remote-endpoint = <&mixer1_out_tcon1>; 376 }; 377 }; 378 379 tcon0_out: port@1 { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <1>; 383 }; 384 }; 385 }; 386 387 tcon1: lcd-controller@1c0d000 { 388 compatible = "allwinner,sun50i-a64-tcon-tv", 389 "allwinner,sun8i-a83t-tcon-tv"; 390 reg = <0x01c0d000 0x1000>; 391 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 393 clock-names = "ahb", "tcon-ch1"; 394 resets = <&ccu RST_BUS_TCON1>; 395 reset-names = "lcd"; 396 397 ports { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 401 tcon1_in: port@0 { 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0>; 405 406 tcon1_in_mixer0: endpoint@0 { 407 reg = <0>; 408 remote-endpoint = <&mixer0_out_tcon1>; 409 }; 410 411 tcon1_in_mixer1: endpoint@1 { 412 reg = <1>; 413 remote-endpoint = <&mixer1_out_tcon1>; 414 }; 415 }; 416 417 tcon1_out: port@1 { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 reg = <1>; 421 422 tcon1_out_hdmi: endpoint@1 { 423 reg = <1>; 424 remote-endpoint = <&hdmi_in_tcon1>; 425 }; 426 }; 427 }; 428 }; 429 430 video-codec@1c0e000 { 431 compatible = "allwinner,sun50i-a64-video-engine"; 432 reg = <0x01c0e000 0x1000>; 433 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 434 <&ccu CLK_DRAM_VE>; 435 clock-names = "ahb", "mod", "ram"; 436 resets = <&ccu RST_BUS_VE>; 437 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 438 allwinner,sram = <&ve_sram 1>; 439 }; 440 441 mmc0: mmc@1c0f000 { 442 compatible = "allwinner,sun50i-a64-mmc"; 443 reg = <0x01c0f000 0x1000>; 444 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 445 clock-names = "ahb", "mmc"; 446 resets = <&ccu RST_BUS_MMC0>; 447 reset-names = "ahb"; 448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 449 max-frequency = <150000000>; 450 status = "disabled"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 }; 454 455 mmc1: mmc@1c10000 { 456 compatible = "allwinner,sun50i-a64-mmc"; 457 reg = <0x01c10000 0x1000>; 458 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 459 clock-names = "ahb", "mmc"; 460 resets = <&ccu RST_BUS_MMC1>; 461 reset-names = "ahb"; 462 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 463 max-frequency = <150000000>; 464 status = "disabled"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 }; 468 469 mmc2: mmc@1c11000 { 470 compatible = "allwinner,sun50i-a64-emmc"; 471 reg = <0x01c11000 0x1000>; 472 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 473 clock-names = "ahb", "mmc"; 474 resets = <&ccu RST_BUS_MMC2>; 475 reset-names = "ahb"; 476 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 477 max-frequency = <200000000>; 478 status = "disabled"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 }; 482 483 sid: eeprom@1c14000 { 484 compatible = "allwinner,sun50i-a64-sid"; 485 reg = <0x1c14000 0x400>; 486 }; 487 488 usb_otg: usb@1c19000 { 489 compatible = "allwinner,sun8i-a33-musb"; 490 reg = <0x01c19000 0x0400>; 491 clocks = <&ccu CLK_BUS_OTG>; 492 resets = <&ccu RST_BUS_OTG>; 493 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "mc"; 495 phys = <&usbphy 0>; 496 phy-names = "usb"; 497 extcon = <&usbphy 0>; 498 status = "disabled"; 499 }; 500 501 usbphy: phy@1c19400 { 502 compatible = "allwinner,sun50i-a64-usb-phy"; 503 reg = <0x01c19400 0x14>, 504 <0x01c1a800 0x4>, 505 <0x01c1b800 0x4>; 506 reg-names = "phy_ctrl", 507 "pmu0", 508 "pmu1"; 509 clocks = <&ccu CLK_USB_PHY0>, 510 <&ccu CLK_USB_PHY1>; 511 clock-names = "usb0_phy", 512 "usb1_phy"; 513 resets = <&ccu RST_USB_PHY0>, 514 <&ccu RST_USB_PHY1>; 515 reset-names = "usb0_reset", 516 "usb1_reset"; 517 status = "disabled"; 518 #phy-cells = <1>; 519 }; 520 521 ehci0: usb@1c1a000 { 522 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 523 reg = <0x01c1a000 0x100>; 524 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&ccu CLK_BUS_OHCI0>, 526 <&ccu CLK_BUS_EHCI0>, 527 <&ccu CLK_USB_OHCI0>; 528 resets = <&ccu RST_BUS_OHCI0>, 529 <&ccu RST_BUS_EHCI0>; 530 status = "disabled"; 531 }; 532 533 ohci0: usb@1c1a400 { 534 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 535 reg = <0x01c1a400 0x100>; 536 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&ccu CLK_BUS_OHCI0>, 538 <&ccu CLK_USB_OHCI0>; 539 resets = <&ccu RST_BUS_OHCI0>; 540 status = "disabled"; 541 }; 542 543 ehci1: usb@1c1b000 { 544 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 545 reg = <0x01c1b000 0x100>; 546 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&ccu CLK_BUS_OHCI1>, 548 <&ccu CLK_BUS_EHCI1>, 549 <&ccu CLK_USB_OHCI1>; 550 resets = <&ccu RST_BUS_OHCI1>, 551 <&ccu RST_BUS_EHCI1>; 552 phys = <&usbphy 1>; 553 phy-names = "usb"; 554 status = "disabled"; 555 }; 556 557 ohci1: usb@1c1b400 { 558 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 559 reg = <0x01c1b400 0x100>; 560 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&ccu CLK_BUS_OHCI1>, 562 <&ccu CLK_USB_OHCI1>; 563 resets = <&ccu RST_BUS_OHCI1>; 564 phys = <&usbphy 1>; 565 phy-names = "usb"; 566 status = "disabled"; 567 }; 568 569 ccu: clock@1c20000 { 570 compatible = "allwinner,sun50i-a64-ccu"; 571 reg = <0x01c20000 0x400>; 572 clocks = <&osc24M>, <&rtc 0>; 573 clock-names = "hosc", "losc"; 574 #clock-cells = <1>; 575 #reset-cells = <1>; 576 }; 577 578 pio: pinctrl@1c20800 { 579 compatible = "allwinner,sun50i-a64-pinctrl"; 580 reg = <0x01c20800 0x400>; 581 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&ccu 58>; 585 gpio-controller; 586 #gpio-cells = <3>; 587 interrupt-controller; 588 #interrupt-cells = <3>; 589 590 csi_pins: csi-pins { 591 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 592 "PE7", "PE8", "PE9", "PE10", "PE11"; 593 function = "csi"; 594 }; 595 596 i2c0_pins: i2c0_pins { 597 pins = "PH0", "PH1"; 598 function = "i2c0"; 599 }; 600 601 i2c1_pins: i2c1_pins { 602 pins = "PH2", "PH3"; 603 function = "i2c1"; 604 }; 605 606 mmc0_pins: mmc0-pins { 607 pins = "PF0", "PF1", "PF2", "PF3", 608 "PF4", "PF5"; 609 function = "mmc0"; 610 drive-strength = <30>; 611 bias-pull-up; 612 }; 613 614 mmc1_pins: mmc1-pins { 615 pins = "PG0", "PG1", "PG2", "PG3", 616 "PG4", "PG5"; 617 function = "mmc1"; 618 drive-strength = <30>; 619 bias-pull-up; 620 }; 621 622 mmc2_pins: mmc2-pins { 623 pins = "PC5", "PC6", "PC8", "PC9", 624 "PC10","PC11", "PC12", "PC13", 625 "PC14", "PC15", "PC16"; 626 function = "mmc2"; 627 drive-strength = <30>; 628 bias-pull-up; 629 }; 630 631 mmc2_ds_pin: mmc2-ds-pin { 632 pins = "PC1"; 633 function = "mmc2"; 634 drive-strength = <30>; 635 bias-pull-up; 636 }; 637 638 pwm_pin: pwm_pin { 639 pins = "PD22"; 640 function = "pwm"; 641 }; 642 643 rmii_pins: rmii_pins { 644 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 645 "PD18", "PD19", "PD20", "PD22", "PD23"; 646 function = "emac"; 647 drive-strength = <40>; 648 }; 649 650 rgmii_pins: rgmii_pins { 651 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 652 "PD13", "PD15", "PD16", "PD17", "PD18", 653 "PD19", "PD20", "PD21", "PD22", "PD23"; 654 function = "emac"; 655 drive-strength = <40>; 656 }; 657 658 spdif_tx_pin: spdif { 659 pins = "PH8"; 660 function = "spdif"; 661 }; 662 663 spi0_pins: spi0 { 664 pins = "PC0", "PC1", "PC2", "PC3"; 665 function = "spi0"; 666 }; 667 668 spi1_pins: spi1 { 669 pins = "PD0", "PD1", "PD2", "PD3"; 670 function = "spi1"; 671 }; 672 673 uart0_pb_pins: uart0-pb-pins { 674 pins = "PB8", "PB9"; 675 function = "uart0"; 676 }; 677 678 uart1_pins: uart1_pins { 679 pins = "PG6", "PG7"; 680 function = "uart1"; 681 }; 682 683 uart1_rts_cts_pins: uart1_rts_cts_pins { 684 pins = "PG8", "PG9"; 685 function = "uart1"; 686 }; 687 688 uart2_pins: uart2-pins { 689 pins = "PB0", "PB1"; 690 function = "uart2"; 691 }; 692 693 uart3_pins: uart3-pins { 694 pins = "PD0", "PD1"; 695 function = "uart3"; 696 }; 697 698 uart4_pins: uart4-pins { 699 pins = "PD2", "PD3"; 700 function = "uart4"; 701 }; 702 703 uart4_rts_cts_pins: uart4-rts-cts-pins { 704 pins = "PD4", "PD5"; 705 function = "uart4"; 706 }; 707 }; 708 709 spdif: spdif@1c21000 { 710 #sound-dai-cells = <0>; 711 compatible = "allwinner,sun50i-a64-spdif", 712 "allwinner,sun8i-h3-spdif"; 713 reg = <0x01c21000 0x400>; 714 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 716 resets = <&ccu RST_BUS_SPDIF>; 717 clock-names = "apb", "spdif"; 718 dmas = <&dma 2>; 719 dma-names = "tx"; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&spdif_tx_pin>; 722 status = "disabled"; 723 }; 724 725 i2s0: i2s@1c22000 { 726 #sound-dai-cells = <0>; 727 compatible = "allwinner,sun50i-a64-i2s", 728 "allwinner,sun8i-h3-i2s"; 729 reg = <0x01c22000 0x400>; 730 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 732 clock-names = "apb", "mod"; 733 resets = <&ccu RST_BUS_I2S0>; 734 dma-names = "rx", "tx"; 735 dmas = <&dma 3>, <&dma 3>; 736 status = "disabled"; 737 }; 738 739 i2s1: i2s@1c22400 { 740 #sound-dai-cells = <0>; 741 compatible = "allwinner,sun50i-a64-i2s", 742 "allwinner,sun8i-h3-i2s"; 743 reg = <0x01c22400 0x400>; 744 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 746 clock-names = "apb", "mod"; 747 resets = <&ccu RST_BUS_I2S1>; 748 dma-names = "rx", "tx"; 749 dmas = <&dma 4>, <&dma 4>; 750 status = "disabled"; 751 }; 752 753 dai: dai@1c22c00 { 754 #sound-dai-cells = <0>; 755 compatible = "allwinner,sun50i-a64-codec-i2s"; 756 reg = <0x01c22c00 0x200>; 757 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 759 clock-names = "apb", "mod"; 760 resets = <&ccu RST_BUS_CODEC>; 761 reset-names = "rst"; 762 dmas = <&dma 15>, <&dma 15>; 763 dma-names = "rx", "tx"; 764 status = "disabled"; 765 }; 766 767 codec: codec@1c22e00 { 768 #sound-dai-cells = <0>; 769 compatible = "allwinner,sun8i-a33-codec"; 770 reg = <0x01c22e00 0x600>; 771 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 773 clock-names = "bus", "mod"; 774 status = "disabled"; 775 }; 776 777 uart0: serial@1c28000 { 778 compatible = "snps,dw-apb-uart"; 779 reg = <0x01c28000 0x400>; 780 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 781 reg-shift = <2>; 782 reg-io-width = <4>; 783 clocks = <&ccu CLK_BUS_UART0>; 784 resets = <&ccu RST_BUS_UART0>; 785 status = "disabled"; 786 }; 787 788 uart1: serial@1c28400 { 789 compatible = "snps,dw-apb-uart"; 790 reg = <0x01c28400 0x400>; 791 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 792 reg-shift = <2>; 793 reg-io-width = <4>; 794 clocks = <&ccu CLK_BUS_UART1>; 795 resets = <&ccu RST_BUS_UART1>; 796 status = "disabled"; 797 }; 798 799 uart2: serial@1c28800 { 800 compatible = "snps,dw-apb-uart"; 801 reg = <0x01c28800 0x400>; 802 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 803 reg-shift = <2>; 804 reg-io-width = <4>; 805 clocks = <&ccu CLK_BUS_UART2>; 806 resets = <&ccu RST_BUS_UART2>; 807 status = "disabled"; 808 }; 809 810 uart3: serial@1c28c00 { 811 compatible = "snps,dw-apb-uart"; 812 reg = <0x01c28c00 0x400>; 813 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 814 reg-shift = <2>; 815 reg-io-width = <4>; 816 clocks = <&ccu CLK_BUS_UART3>; 817 resets = <&ccu RST_BUS_UART3>; 818 status = "disabled"; 819 }; 820 821 uart4: serial@1c29000 { 822 compatible = "snps,dw-apb-uart"; 823 reg = <0x01c29000 0x400>; 824 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 825 reg-shift = <2>; 826 reg-io-width = <4>; 827 clocks = <&ccu CLK_BUS_UART4>; 828 resets = <&ccu RST_BUS_UART4>; 829 status = "disabled"; 830 }; 831 832 i2c0: i2c@1c2ac00 { 833 compatible = "allwinner,sun6i-a31-i2c"; 834 reg = <0x01c2ac00 0x400>; 835 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&ccu CLK_BUS_I2C0>; 837 resets = <&ccu RST_BUS_I2C0>; 838 status = "disabled"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 }; 842 843 i2c1: i2c@1c2b000 { 844 compatible = "allwinner,sun6i-a31-i2c"; 845 reg = <0x01c2b000 0x400>; 846 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&ccu CLK_BUS_I2C1>; 848 resets = <&ccu RST_BUS_I2C1>; 849 status = "disabled"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 }; 853 854 i2c2: i2c@1c2b400 { 855 compatible = "allwinner,sun6i-a31-i2c"; 856 reg = <0x01c2b400 0x400>; 857 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&ccu CLK_BUS_I2C2>; 859 resets = <&ccu RST_BUS_I2C2>; 860 status = "disabled"; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 }; 864 865 866 spi0: spi@1c68000 { 867 compatible = "allwinner,sun8i-h3-spi"; 868 reg = <0x01c68000 0x1000>; 869 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 871 clock-names = "ahb", "mod"; 872 dmas = <&dma 23>, <&dma 23>; 873 dma-names = "rx", "tx"; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&spi0_pins>; 876 resets = <&ccu RST_BUS_SPI0>; 877 status = "disabled"; 878 num-cs = <1>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 }; 882 883 spi1: spi@1c69000 { 884 compatible = "allwinner,sun8i-h3-spi"; 885 reg = <0x01c69000 0x1000>; 886 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 888 clock-names = "ahb", "mod"; 889 dmas = <&dma 24>, <&dma 24>; 890 dma-names = "rx", "tx"; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&spi1_pins>; 893 resets = <&ccu RST_BUS_SPI1>; 894 status = "disabled"; 895 num-cs = <1>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 }; 899 900 emac: ethernet@1c30000 { 901 compatible = "allwinner,sun50i-a64-emac"; 902 syscon = <&syscon>; 903 reg = <0x01c30000 0x10000>; 904 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-names = "macirq"; 906 resets = <&ccu RST_BUS_EMAC>; 907 reset-names = "stmmaceth"; 908 clocks = <&ccu CLK_BUS_EMAC>; 909 clock-names = "stmmaceth"; 910 status = "disabled"; 911 912 mdio: mdio { 913 compatible = "snps,dwmac-mdio"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 }; 917 }; 918 919 mali: gpu@1c40000 { 920 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 921 reg = <0x01c40000 0x10000>; 922 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 929 interrupt-names = "gp", 930 "gpmmu", 931 "pp0", 932 "ppmmu0", 933 "pp1", 934 "ppmmu1", 935 "pmu"; 936 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 937 clock-names = "bus", "core"; 938 resets = <&ccu RST_BUS_GPU>; 939 }; 940 941 gic: interrupt-controller@1c81000 { 942 compatible = "arm,gic-400"; 943 reg = <0x01c81000 0x1000>, 944 <0x01c82000 0x2000>, 945 <0x01c84000 0x2000>, 946 <0x01c86000 0x2000>; 947 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 948 interrupt-controller; 949 #interrupt-cells = <3>; 950 }; 951 952 pwm: pwm@1c21400 { 953 compatible = "allwinner,sun50i-a64-pwm", 954 "allwinner,sun5i-a13-pwm"; 955 reg = <0x01c21400 0x400>; 956 clocks = <&osc24M>; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&pwm_pin>; 959 #pwm-cells = <3>; 960 status = "disabled"; 961 }; 962 963 csi: csi@1cb0000 { 964 compatible = "allwinner,sun50i-a64-csi"; 965 reg = <0x01cb0000 0x1000>; 966 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&ccu CLK_BUS_CSI>, 968 <&ccu CLK_CSI_SCLK>, 969 <&ccu CLK_DRAM_CSI>; 970 clock-names = "bus", "mod", "ram"; 971 resets = <&ccu RST_BUS_CSI>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&csi_pins>; 974 status = "disabled"; 975 }; 976 977 hdmi: hdmi@1ee0000 { 978 compatible = "allwinner,sun50i-a64-dw-hdmi", 979 "allwinner,sun8i-a83t-dw-hdmi"; 980 reg = <0x01ee0000 0x10000>; 981 reg-io-width = <1>; 982 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 984 <&ccu CLK_HDMI>; 985 clock-names = "iahb", "isfr", "tmds"; 986 resets = <&ccu RST_BUS_HDMI1>; 987 reset-names = "ctrl"; 988 phys = <&hdmi_phy>; 989 phy-names = "hdmi-phy"; 990 status = "disabled"; 991 992 ports { 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 hdmi_in: port@0 { 997 reg = <0>; 998 999 hdmi_in_tcon1: endpoint { 1000 remote-endpoint = <&tcon1_out_hdmi>; 1001 }; 1002 }; 1003 1004 hdmi_out: port@1 { 1005 reg = <1>; 1006 }; 1007 }; 1008 }; 1009 1010 hdmi_phy: hdmi-phy@1ef0000 { 1011 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1012 reg = <0x01ef0000 0x10000>; 1013 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1014 <&ccu 7>; 1015 clock-names = "bus", "mod", "pll-0"; 1016 resets = <&ccu RST_BUS_HDMI0>; 1017 reset-names = "phy"; 1018 #phy-cells = <0>; 1019 }; 1020 1021 rtc: rtc@1f00000 { 1022 compatible = "allwinner,sun50i-a64-rtc", 1023 "allwinner,sun8i-h3-rtc"; 1024 reg = <0x01f00000 0x400>; 1025 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1027 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1028 clocks = <&osc32k>; 1029 #clock-cells = <1>; 1030 }; 1031 1032 r_intc: interrupt-controller@1f00c00 { 1033 compatible = "allwinner,sun50i-a64-r-intc", 1034 "allwinner,sun6i-a31-r-intc"; 1035 interrupt-controller; 1036 #interrupt-cells = <2>; 1037 reg = <0x01f00c00 0x400>; 1038 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1039 }; 1040 1041 r_ccu: clock@1f01400 { 1042 compatible = "allwinner,sun50i-a64-r-ccu"; 1043 reg = <0x01f01400 0x100>; 1044 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1045 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1046 #clock-cells = <1>; 1047 #reset-cells = <1>; 1048 }; 1049 1050 codec_analog: codec-analog@1f015c0 { 1051 compatible = "allwinner,sun50i-a64-codec-analog"; 1052 reg = <0x01f015c0 0x4>; 1053 status = "disabled"; 1054 }; 1055 1056 r_i2c: i2c@1f02400 { 1057 compatible = "allwinner,sun50i-a64-i2c", 1058 "allwinner,sun6i-a31-i2c"; 1059 reg = <0x01f02400 0x400>; 1060 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&r_ccu CLK_APB0_I2C>; 1062 resets = <&r_ccu RST_APB0_I2C>; 1063 status = "disabled"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 }; 1067 1068 r_pwm: pwm@1f03800 { 1069 compatible = "allwinner,sun50i-a64-pwm", 1070 "allwinner,sun5i-a13-pwm"; 1071 reg = <0x01f03800 0x400>; 1072 clocks = <&osc24M>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&r_pwm_pin>; 1075 #pwm-cells = <3>; 1076 status = "disabled"; 1077 }; 1078 1079 r_pio: pinctrl@1f02c00 { 1080 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1081 reg = <0x01f02c00 0x400>; 1082 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1084 clock-names = "apb", "hosc", "losc"; 1085 gpio-controller; 1086 #gpio-cells = <3>; 1087 interrupt-controller; 1088 #interrupt-cells = <3>; 1089 1090 r_i2c_pl89_pins: r-i2c-pl89-pins { 1091 pins = "PL8", "PL9"; 1092 function = "s_i2c"; 1093 }; 1094 1095 r_pwm_pin: pwm { 1096 pins = "PL10"; 1097 function = "s_pwm"; 1098 }; 1099 1100 r_rsb_pins: rsb { 1101 pins = "PL0", "PL1"; 1102 function = "s_rsb"; 1103 }; 1104 }; 1105 1106 r_rsb: rsb@1f03400 { 1107 compatible = "allwinner,sun8i-a23-rsb"; 1108 reg = <0x01f03400 0x400>; 1109 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&r_ccu 6>; 1111 clock-frequency = <3000000>; 1112 resets = <&r_ccu 2>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&r_rsb_pins>; 1115 status = "disabled"; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 }; 1119 1120 wdt0: watchdog@1c20ca0 { 1121 compatible = "allwinner,sun50i-a64-wdt", 1122 "allwinner,sun6i-a31-wdt"; 1123 reg = <0x01c20ca0 0x20>; 1124 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1125 }; 1126 }; 1127}; 1128