1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-de2.h>
47#include <dt-bindings/clock/sun8i-r-ccu.h>
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include <dt-bindings/reset/sun50i-a64-ccu.h>
50#include <dt-bindings/reset/sun8i-de2.h>
51#include <dt-bindings/reset/sun8i-r-ccu.h>
52
53/ {
54	interrupt-parent = <&gic>;
55	#address-cells = <1>;
56	#size-cells = <1>;
57
58	chosen {
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges;
62
63		simplefb_lcd: framebuffer-lcd {
64			compatible = "allwinner,simple-framebuffer",
65				     "simple-framebuffer";
66			allwinner,pipeline = "mixer0-lcd0";
67			clocks = <&ccu CLK_TCON0>,
68				 <&display_clocks CLK_MIXER0>;
69			status = "disabled";
70		};
71
72		simplefb_hdmi: framebuffer-hdmi {
73			compatible = "allwinner,simple-framebuffer",
74				     "simple-framebuffer";
75			allwinner,pipeline = "mixer1-lcd1-hdmi";
76			clocks = <&display_clocks CLK_MIXER1>,
77				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
78			status = "disabled";
79		};
80	};
81
82	cpus {
83		#address-cells = <1>;
84		#size-cells = <0>;
85
86		cpu0: cpu@0 {
87			compatible = "arm,cortex-a53", "arm,armv8";
88			device_type = "cpu";
89			reg = <0>;
90			enable-method = "psci";
91		};
92
93		cpu1: cpu@1 {
94			compatible = "arm,cortex-a53", "arm,armv8";
95			device_type = "cpu";
96			reg = <1>;
97			enable-method = "psci";
98		};
99
100		cpu2: cpu@2 {
101			compatible = "arm,cortex-a53", "arm,armv8";
102			device_type = "cpu";
103			reg = <2>;
104			enable-method = "psci";
105		};
106
107		cpu3: cpu@3 {
108			compatible = "arm,cortex-a53", "arm,armv8";
109			device_type = "cpu";
110			reg = <3>;
111			enable-method = "psci";
112		};
113	};
114
115	osc24M: osc24M_clk {
116		#clock-cells = <0>;
117		compatible = "fixed-clock";
118		clock-frequency = <24000000>;
119		clock-output-names = "osc24M";
120	};
121
122	osc32k: osc32k_clk {
123		#clock-cells = <0>;
124		compatible = "fixed-clock";
125		clock-frequency = <32768>;
126		clock-output-names = "osc32k";
127	};
128
129	iosc: internal-osc-clk {
130		#clock-cells = <0>;
131		compatible = "fixed-clock";
132		clock-frequency = <16000000>;
133		clock-accuracy = <300000000>;
134		clock-output-names = "iosc";
135	};
136
137	psci {
138		compatible = "arm,psci-0.2";
139		method = "smc";
140	};
141
142	sound_spdif {
143		compatible = "simple-audio-card";
144		simple-audio-card,name = "On-board SPDIF";
145
146		simple-audio-card,cpu {
147			sound-dai = <&spdif>;
148		};
149
150		simple-audio-card,codec {
151			sound-dai = <&spdif_out>;
152		};
153	};
154
155	spdif_out: spdif-out {
156		#sound-dai-cells = <0>;
157		compatible = "linux,spdif-dit";
158	};
159
160	timer {
161		compatible = "arm,armv8-timer";
162		interrupts = <GIC_PPI 13
163			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
164			     <GIC_PPI 14
165			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
166			     <GIC_PPI 11
167			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
168			     <GIC_PPI 10
169			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
170	};
171
172	soc {
173		compatible = "simple-bus";
174		#address-cells = <1>;
175		#size-cells = <1>;
176		ranges;
177
178		de2@1000000 {
179			compatible = "allwinner,sun50i-a64-de2";
180			reg = <0x1000000 0x400000>;
181			allwinner,sram = <&de2_sram 1>;
182			#address-cells = <1>;
183			#size-cells = <1>;
184			ranges = <0 0x1000000 0x400000>;
185
186			display_clocks: clock@0 {
187				compatible = "allwinner,sun50i-a64-de2-clk";
188				reg = <0x0 0x100000>;
189				clocks = <&ccu CLK_DE>,
190					 <&ccu CLK_BUS_DE>;
191				clock-names = "mod",
192					      "bus";
193				resets = <&ccu RST_BUS_DE>;
194				#clock-cells = <1>;
195				#reset-cells = <1>;
196			};
197		};
198
199		syscon: syscon@1c00000 {
200			compatible = "allwinner,sun50i-a64-system-control";
201			reg = <0x01c00000 0x1000>;
202			#address-cells = <1>;
203			#size-cells = <1>;
204			ranges;
205
206			sram_c: sram@18000 {
207				compatible = "mmio-sram";
208				reg = <0x00018000 0x28000>;
209				#address-cells = <1>;
210				#size-cells = <1>;
211				ranges = <0 0x00018000 0x28000>;
212
213				de2_sram: sram-section@0 {
214					compatible = "allwinner,sun50i-a64-sram-c";
215					reg = <0x0000 0x28000>;
216				};
217			};
218		};
219
220		dma: dma-controller@1c02000 {
221			compatible = "allwinner,sun50i-a64-dma";
222			reg = <0x01c02000 0x1000>;
223			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
224			clocks = <&ccu CLK_BUS_DMA>;
225			dma-channels = <8>;
226			dma-requests = <27>;
227			resets = <&ccu RST_BUS_DMA>;
228			#dma-cells = <1>;
229		};
230
231		mmc0: mmc@1c0f000 {
232			compatible = "allwinner,sun50i-a64-mmc";
233			reg = <0x01c0f000 0x1000>;
234			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
235			clock-names = "ahb", "mmc";
236			resets = <&ccu RST_BUS_MMC0>;
237			reset-names = "ahb";
238			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
239			max-frequency = <150000000>;
240			status = "disabled";
241			#address-cells = <1>;
242			#size-cells = <0>;
243		};
244
245		mmc1: mmc@1c10000 {
246			compatible = "allwinner,sun50i-a64-mmc";
247			reg = <0x01c10000 0x1000>;
248			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
249			clock-names = "ahb", "mmc";
250			resets = <&ccu RST_BUS_MMC1>;
251			reset-names = "ahb";
252			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
253			max-frequency = <150000000>;
254			status = "disabled";
255			#address-cells = <1>;
256			#size-cells = <0>;
257		};
258
259		mmc2: mmc@1c11000 {
260			compatible = "allwinner,sun50i-a64-emmc";
261			reg = <0x01c11000 0x1000>;
262			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
263			clock-names = "ahb", "mmc";
264			resets = <&ccu RST_BUS_MMC2>;
265			reset-names = "ahb";
266			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
267			max-frequency = <200000000>;
268			status = "disabled";
269			#address-cells = <1>;
270			#size-cells = <0>;
271		};
272
273		usb_otg: usb@1c19000 {
274			compatible = "allwinner,sun8i-a33-musb";
275			reg = <0x01c19000 0x0400>;
276			clocks = <&ccu CLK_BUS_OTG>;
277			resets = <&ccu RST_BUS_OTG>;
278			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
279			interrupt-names = "mc";
280			phys = <&usbphy 0>;
281			phy-names = "usb";
282			extcon = <&usbphy 0>;
283			status = "disabled";
284		};
285
286		usbphy: phy@1c19400 {
287			compatible = "allwinner,sun50i-a64-usb-phy";
288			reg = <0x01c19400 0x14>,
289			      <0x01c1a800 0x4>,
290			      <0x01c1b800 0x4>;
291			reg-names = "phy_ctrl",
292				    "pmu0",
293				    "pmu1";
294			clocks = <&ccu CLK_USB_PHY0>,
295				 <&ccu CLK_USB_PHY1>;
296			clock-names = "usb0_phy",
297				      "usb1_phy";
298			resets = <&ccu RST_USB_PHY0>,
299				 <&ccu RST_USB_PHY1>;
300			reset-names = "usb0_reset",
301				      "usb1_reset";
302			status = "disabled";
303			#phy-cells = <1>;
304		};
305
306		ehci0: usb@1c1a000 {
307			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
308			reg = <0x01c1a000 0x100>;
309			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
310			clocks = <&ccu CLK_BUS_OHCI0>,
311				 <&ccu CLK_BUS_EHCI0>,
312				 <&ccu CLK_USB_OHCI0>;
313			resets = <&ccu RST_BUS_OHCI0>,
314				 <&ccu RST_BUS_EHCI0>;
315			status = "disabled";
316		};
317
318		ohci0: usb@1c1a400 {
319			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
320			reg = <0x01c1a400 0x100>;
321			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
322			clocks = <&ccu CLK_BUS_OHCI0>,
323				 <&ccu CLK_USB_OHCI0>;
324			resets = <&ccu RST_BUS_OHCI0>;
325			status = "disabled";
326		};
327
328		ehci1: usb@1c1b000 {
329			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
330			reg = <0x01c1b000 0x100>;
331			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
332			clocks = <&ccu CLK_BUS_OHCI1>,
333				 <&ccu CLK_BUS_EHCI1>,
334				 <&ccu CLK_USB_OHCI1>;
335			resets = <&ccu RST_BUS_OHCI1>,
336				 <&ccu RST_BUS_EHCI1>;
337			phys = <&usbphy 1>;
338			phy-names = "usb";
339			status = "disabled";
340		};
341
342		ohci1: usb@1c1b400 {
343			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
344			reg = <0x01c1b400 0x100>;
345			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
346			clocks = <&ccu CLK_BUS_OHCI1>,
347				 <&ccu CLK_USB_OHCI1>;
348			resets = <&ccu RST_BUS_OHCI1>;
349			phys = <&usbphy 1>;
350			phy-names = "usb";
351			status = "disabled";
352		};
353
354		ccu: clock@1c20000 {
355			compatible = "allwinner,sun50i-a64-ccu";
356			reg = <0x01c20000 0x400>;
357			clocks = <&osc24M>, <&osc32k>;
358			clock-names = "hosc", "losc";
359			#clock-cells = <1>;
360			#reset-cells = <1>;
361		};
362
363		pio: pinctrl@1c20800 {
364			compatible = "allwinner,sun50i-a64-pinctrl";
365			reg = <0x01c20800 0x400>;
366			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
367				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
368				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
369			clocks = <&ccu 58>;
370			gpio-controller;
371			#gpio-cells = <3>;
372			interrupt-controller;
373			#interrupt-cells = <3>;
374
375			i2c0_pins: i2c0_pins {
376				pins = "PH0", "PH1";
377				function = "i2c0";
378			};
379
380			i2c1_pins: i2c1_pins {
381				pins = "PH2", "PH3";
382				function = "i2c1";
383			};
384
385			mmc0_pins: mmc0-pins {
386				pins = "PF0", "PF1", "PF2", "PF3",
387				       "PF4", "PF5";
388				function = "mmc0";
389				drive-strength = <30>;
390				bias-pull-up;
391			};
392
393			mmc1_pins: mmc1-pins {
394				pins = "PG0", "PG1", "PG2", "PG3",
395				       "PG4", "PG5";
396				function = "mmc1";
397				drive-strength = <30>;
398				bias-pull-up;
399			};
400
401			mmc2_pins: mmc2-pins {
402				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
403				       "PC10","PC11", "PC12", "PC13",
404				       "PC14", "PC15", "PC16";
405				function = "mmc2";
406				drive-strength = <30>;
407				bias-pull-up;
408			};
409
410			pwm_pin: pwm_pin {
411				pins = "PD22";
412				function = "pwm";
413			};
414
415			rmii_pins: rmii_pins {
416				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
417				       "PD18", "PD19", "PD20", "PD22", "PD23";
418				function = "emac";
419				drive-strength = <40>;
420			};
421
422			rgmii_pins: rgmii_pins {
423				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
424				       "PD13", "PD15", "PD16", "PD17", "PD18",
425				       "PD19", "PD20", "PD21", "PD22", "PD23";
426				function = "emac";
427				drive-strength = <40>;
428			};
429
430			spdif_tx_pin: spdif {
431				pins = "PH8";
432				function = "spdif";
433			};
434
435			spi0_pins: spi0 {
436				pins = "PC0", "PC1", "PC2", "PC3";
437				function = "spi0";
438			};
439
440			spi1_pins: spi1 {
441				pins = "PD0", "PD1", "PD2", "PD3";
442				function = "spi1";
443			};
444
445			uart0_pins_a: uart0 {
446				pins = "PB8", "PB9";
447				function = "uart0";
448			};
449
450			uart1_pins: uart1_pins {
451				pins = "PG6", "PG7";
452				function = "uart1";
453			};
454
455			uart1_rts_cts_pins: uart1_rts_cts_pins {
456				pins = "PG8", "PG9";
457				function = "uart1";
458			};
459
460			uart2_pins: uart2-pins {
461				pins = "PB0", "PB1";
462				function = "uart2";
463			};
464
465			uart3_pins: uart3-pins {
466				pins = "PD0", "PD1";
467				function = "uart3";
468			};
469
470			uart4_pins: uart4-pins {
471				pins = "PD2", "PD3";
472				function = "uart4";
473			};
474
475			uart4_rts_cts_pins: uart4-rts-cts-pins {
476				pins = "PD4", "PD5";
477				function = "uart4";
478			};
479		};
480
481		spdif: spdif@1c21000 {
482			#sound-dai-cells = <0>;
483			compatible = "allwinner,sun50i-a64-spdif",
484				     "allwinner,sun8i-h3-spdif";
485			reg = <0x01c21000 0x400>;
486			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
487			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
488			resets = <&ccu RST_BUS_SPDIF>;
489			clock-names = "apb", "spdif";
490			dmas = <&dma 2>;
491			dma-names = "tx";
492			pinctrl-names = "default";
493			pinctrl-0 = <&spdif_tx_pin>;
494			status = "disabled";
495		};
496
497		i2s0: i2s@1c22000 {
498			#sound-dai-cells = <0>;
499			compatible = "allwinner,sun50i-a64-i2s",
500				     "allwinner,sun8i-h3-i2s";
501			reg = <0x01c22000 0x400>;
502			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
503			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
504			clock-names = "apb", "mod";
505			resets = <&ccu RST_BUS_I2S0>;
506			dma-names = "rx", "tx";
507			dmas = <&dma 3>, <&dma 3>;
508			status = "disabled";
509		};
510
511		i2s1: i2s@1c22400 {
512			#sound-dai-cells = <0>;
513			compatible = "allwinner,sun50i-a64-i2s",
514				     "allwinner,sun8i-h3-i2s";
515			reg = <0x01c22400 0x400>;
516			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
517			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
518			clock-names = "apb", "mod";
519			resets = <&ccu RST_BUS_I2S1>;
520			dma-names = "rx", "tx";
521			dmas = <&dma 4>, <&dma 4>;
522			status = "disabled";
523		};
524
525		uart0: serial@1c28000 {
526			compatible = "snps,dw-apb-uart";
527			reg = <0x01c28000 0x400>;
528			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
529			reg-shift = <2>;
530			reg-io-width = <4>;
531			clocks = <&ccu CLK_BUS_UART0>;
532			resets = <&ccu RST_BUS_UART0>;
533			status = "disabled";
534		};
535
536		uart1: serial@1c28400 {
537			compatible = "snps,dw-apb-uart";
538			reg = <0x01c28400 0x400>;
539			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
540			reg-shift = <2>;
541			reg-io-width = <4>;
542			clocks = <&ccu CLK_BUS_UART1>;
543			resets = <&ccu RST_BUS_UART1>;
544			status = "disabled";
545		};
546
547		uart2: serial@1c28800 {
548			compatible = "snps,dw-apb-uart";
549			reg = <0x01c28800 0x400>;
550			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
551			reg-shift = <2>;
552			reg-io-width = <4>;
553			clocks = <&ccu CLK_BUS_UART2>;
554			resets = <&ccu RST_BUS_UART2>;
555			status = "disabled";
556		};
557
558		uart3: serial@1c28c00 {
559			compatible = "snps,dw-apb-uart";
560			reg = <0x01c28c00 0x400>;
561			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
562			reg-shift = <2>;
563			reg-io-width = <4>;
564			clocks = <&ccu CLK_BUS_UART3>;
565			resets = <&ccu RST_BUS_UART3>;
566			status = "disabled";
567		};
568
569		uart4: serial@1c29000 {
570			compatible = "snps,dw-apb-uart";
571			reg = <0x01c29000 0x400>;
572			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
573			reg-shift = <2>;
574			reg-io-width = <4>;
575			clocks = <&ccu CLK_BUS_UART4>;
576			resets = <&ccu RST_BUS_UART4>;
577			status = "disabled";
578		};
579
580		i2c0: i2c@1c2ac00 {
581			compatible = "allwinner,sun6i-a31-i2c";
582			reg = <0x01c2ac00 0x400>;
583			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
584			clocks = <&ccu CLK_BUS_I2C0>;
585			resets = <&ccu RST_BUS_I2C0>;
586			status = "disabled";
587			#address-cells = <1>;
588			#size-cells = <0>;
589		};
590
591		i2c1: i2c@1c2b000 {
592			compatible = "allwinner,sun6i-a31-i2c";
593			reg = <0x01c2b000 0x400>;
594			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
595			clocks = <&ccu CLK_BUS_I2C1>;
596			resets = <&ccu RST_BUS_I2C1>;
597			status = "disabled";
598			#address-cells = <1>;
599			#size-cells = <0>;
600		};
601
602		i2c2: i2c@1c2b400 {
603			compatible = "allwinner,sun6i-a31-i2c";
604			reg = <0x01c2b400 0x400>;
605			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
606			clocks = <&ccu CLK_BUS_I2C2>;
607			resets = <&ccu RST_BUS_I2C2>;
608			status = "disabled";
609			#address-cells = <1>;
610			#size-cells = <0>;
611		};
612
613
614		spi0: spi@1c68000 {
615			compatible = "allwinner,sun8i-h3-spi";
616			reg = <0x01c68000 0x1000>;
617			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
618			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
619			clock-names = "ahb", "mod";
620			dmas = <&dma 23>, <&dma 23>;
621			dma-names = "rx", "tx";
622			pinctrl-names = "default";
623			pinctrl-0 = <&spi0_pins>;
624			resets = <&ccu RST_BUS_SPI0>;
625			status = "disabled";
626			num-cs = <1>;
627			#address-cells = <1>;
628			#size-cells = <0>;
629		};
630
631		spi1: spi@1c69000 {
632			compatible = "allwinner,sun8i-h3-spi";
633			reg = <0x01c69000 0x1000>;
634			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
635			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
636			clock-names = "ahb", "mod";
637			dmas = <&dma 24>, <&dma 24>;
638			dma-names = "rx", "tx";
639			pinctrl-names = "default";
640			pinctrl-0 = <&spi1_pins>;
641			resets = <&ccu RST_BUS_SPI1>;
642			status = "disabled";
643			num-cs = <1>;
644			#address-cells = <1>;
645			#size-cells = <0>;
646		};
647
648		emac: ethernet@1c30000 {
649			compatible = "allwinner,sun50i-a64-emac";
650			syscon = <&syscon>;
651			reg = <0x01c30000 0x10000>;
652			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
653			interrupt-names = "macirq";
654			resets = <&ccu RST_BUS_EMAC>;
655			reset-names = "stmmaceth";
656			clocks = <&ccu CLK_BUS_EMAC>;
657			clock-names = "stmmaceth";
658			status = "disabled";
659
660			mdio: mdio {
661				compatible = "snps,dwmac-mdio";
662				#address-cells = <1>;
663				#size-cells = <0>;
664			};
665		};
666
667		gic: interrupt-controller@1c81000 {
668			compatible = "arm,gic-400";
669			reg = <0x01c81000 0x1000>,
670			      <0x01c82000 0x2000>,
671			      <0x01c84000 0x2000>,
672			      <0x01c86000 0x2000>;
673			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
674			interrupt-controller;
675			#interrupt-cells = <3>;
676		};
677
678		pwm: pwm@1c21400 {
679			compatible = "allwinner,sun50i-a64-pwm",
680				     "allwinner,sun5i-a13-pwm";
681			reg = <0x01c21400 0x400>;
682			clocks = <&osc24M>;
683			pinctrl-names = "default";
684			pinctrl-0 = <&pwm_pin>;
685			#pwm-cells = <3>;
686			status = "disabled";
687		};
688
689		rtc: rtc@1f00000 {
690			compatible = "allwinner,sun6i-a31-rtc";
691			reg = <0x01f00000 0x54>;
692			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
693				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
694			clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
695			clocks = <&osc32k>;
696			#clock-cells = <1>;
697		};
698
699		r_intc: interrupt-controller@1f00c00 {
700			compatible = "allwinner,sun50i-a64-r-intc",
701				     "allwinner,sun6i-a31-r-intc";
702			interrupt-controller;
703			#interrupt-cells = <2>;
704			reg = <0x01f00c00 0x400>;
705			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
706		};
707
708		r_ccu: clock@1f01400 {
709			compatible = "allwinner,sun50i-a64-r-ccu";
710			reg = <0x01f01400 0x100>;
711			clocks = <&osc24M>, <&osc32k>, <&iosc>,
712				 <&ccu 11>;
713			clock-names = "hosc", "losc", "iosc", "pll-periph";
714			#clock-cells = <1>;
715			#reset-cells = <1>;
716		};
717
718		r_i2c: i2c@1f02400 {
719			compatible = "allwinner,sun50i-a64-i2c",
720				     "allwinner,sun6i-a31-i2c";
721			reg = <0x01f02400 0x400>;
722			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
723			clocks = <&r_ccu CLK_APB0_I2C>;
724			resets = <&r_ccu RST_APB0_I2C>;
725			status = "disabled";
726			#address-cells = <1>;
727			#size-cells = <0>;
728		};
729
730		r_pwm: pwm@1f03800 {
731			compatible = "allwinner,sun50i-a64-pwm",
732				     "allwinner,sun5i-a13-pwm";
733			reg = <0x01f03800 0x400>;
734			clocks = <&osc24M>;
735			pinctrl-names = "default";
736			pinctrl-0 = <&r_pwm_pin>;
737			#pwm-cells = <3>;
738			status = "disabled";
739		};
740
741		r_pio: pinctrl@1f02c00 {
742			compatible = "allwinner,sun50i-a64-r-pinctrl";
743			reg = <0x01f02c00 0x400>;
744			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
745			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
746			clock-names = "apb", "hosc", "losc";
747			gpio-controller;
748			#gpio-cells = <3>;
749			interrupt-controller;
750			#interrupt-cells = <3>;
751
752			r_i2c_pins_a: i2c-a {
753				pins = "PL8", "PL9";
754				function = "s_i2c";
755			};
756
757			r_pwm_pin: pwm {
758				pins = "PL10";
759				function = "s_pwm";
760			};
761
762			r_rsb_pins: rsb {
763				pins = "PL0", "PL1";
764				function = "s_rsb";
765			};
766		};
767
768		r_rsb: rsb@1f03400 {
769			compatible = "allwinner,sun8i-a23-rsb";
770			reg = <0x01f03400 0x400>;
771			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
772			clocks = <&r_ccu 6>;
773			clock-frequency = <3000000>;
774			resets = <&r_ccu 2>;
775			pinctrl-names = "default";
776			pinctrl-0 = <&r_rsb_pins>;
777			status = "disabled";
778			#address-cells = <1>;
779			#size-cells = <0>;
780		};
781
782		wdt0: watchdog@1c20ca0 {
783			compatible = "allwinner,sun50i-a64-wdt",
784				     "allwinner,sun6i-a31-wdt";
785			reg = <0x01c20ca0 0x20>;
786			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
787		};
788	};
789};
790