1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-r-ccu.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/reset/sun50i-a64-ccu.h> 49#include <dt-bindings/reset/sun8i-r-ccu.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 chosen { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 61/* 62 * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. 63 * However there is no support for this clock on A64 yet, so we depend 64 * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. 65 */ 66 simplefb_lcd: framebuffer-lcd { 67 compatible = "allwinner,simple-framebuffer", 68 "simple-framebuffer"; 69 allwinner,pipeline = "mixer0-lcd0"; 70 clocks = <&ccu CLK_TCON0>, 71 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; 72 status = "disabled"; 73 }; 74 }; 75 76 cpus { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 cpu0: cpu@0 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <0>; 84 enable-method = "psci"; 85 }; 86 87 cpu1: cpu@1 { 88 compatible = "arm,cortex-a53", "arm,armv8"; 89 device_type = "cpu"; 90 reg = <1>; 91 enable-method = "psci"; 92 }; 93 94 cpu2: cpu@2 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <2>; 98 enable-method = "psci"; 99 }; 100 101 cpu3: cpu@3 { 102 compatible = "arm,cortex-a53", "arm,armv8"; 103 device_type = "cpu"; 104 reg = <3>; 105 enable-method = "psci"; 106 }; 107 }; 108 109 osc24M: osc24M_clk { 110 #clock-cells = <0>; 111 compatible = "fixed-clock"; 112 clock-frequency = <24000000>; 113 clock-output-names = "osc24M"; 114 }; 115 116 osc32k: osc32k_clk { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 clock-frequency = <32768>; 120 clock-output-names = "osc32k"; 121 }; 122 123 iosc: internal-osc-clk { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <16000000>; 127 clock-accuracy = <300000000>; 128 clock-output-names = "iosc"; 129 }; 130 131 psci { 132 compatible = "arm,psci-0.2"; 133 method = "smc"; 134 }; 135 136 sound_spdif { 137 compatible = "simple-audio-card"; 138 simple-audio-card,name = "On-board SPDIF"; 139 140 simple-audio-card,cpu { 141 sound-dai = <&spdif>; 142 }; 143 144 simple-audio-card,codec { 145 sound-dai = <&spdif_out>; 146 }; 147 }; 148 149 spdif_out: spdif-out { 150 #sound-dai-cells = <0>; 151 compatible = "linux,spdif-dit"; 152 }; 153 154 timer { 155 compatible = "arm,armv8-timer"; 156 interrupts = <GIC_PPI 13 157 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 14 159 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 160 <GIC_PPI 11 161 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 162 <GIC_PPI 10 163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 164 }; 165 166 soc { 167 compatible = "simple-bus"; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges; 171 172 syscon: syscon@1c00000 { 173 compatible = "allwinner,sun50i-a64-system-control"; 174 reg = <0x01c00000 0x1000>; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges; 178 179 sram_c: sram@18000 { 180 compatible = "mmio-sram"; 181 reg = <0x00018000 0x28000>; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 ranges = <0 0x00018000 0x28000>; 185 186 de2_sram: sram-section@0 { 187 compatible = "allwinner,sun50i-a64-sram-c"; 188 reg = <0x0000 0x28000>; 189 }; 190 }; 191 }; 192 193 dma: dma-controller@1c02000 { 194 compatible = "allwinner,sun50i-a64-dma"; 195 reg = <0x01c02000 0x1000>; 196 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&ccu CLK_BUS_DMA>; 198 dma-channels = <8>; 199 dma-requests = <27>; 200 resets = <&ccu RST_BUS_DMA>; 201 #dma-cells = <1>; 202 }; 203 204 mmc0: mmc@1c0f000 { 205 compatible = "allwinner,sun50i-a64-mmc"; 206 reg = <0x01c0f000 0x1000>; 207 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 208 clock-names = "ahb", "mmc"; 209 resets = <&ccu RST_BUS_MMC0>; 210 reset-names = "ahb"; 211 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 212 max-frequency = <150000000>; 213 status = "disabled"; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 }; 217 218 mmc1: mmc@1c10000 { 219 compatible = "allwinner,sun50i-a64-mmc"; 220 reg = <0x01c10000 0x1000>; 221 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 222 clock-names = "ahb", "mmc"; 223 resets = <&ccu RST_BUS_MMC1>; 224 reset-names = "ahb"; 225 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 226 max-frequency = <150000000>; 227 status = "disabled"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 mmc2: mmc@1c11000 { 233 compatible = "allwinner,sun50i-a64-emmc"; 234 reg = <0x01c11000 0x1000>; 235 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 236 clock-names = "ahb", "mmc"; 237 resets = <&ccu RST_BUS_MMC2>; 238 reset-names = "ahb"; 239 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 240 max-frequency = <200000000>; 241 status = "disabled"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 }; 245 246 usb_otg: usb@1c19000 { 247 compatible = "allwinner,sun8i-a33-musb"; 248 reg = <0x01c19000 0x0400>; 249 clocks = <&ccu CLK_BUS_OTG>; 250 resets = <&ccu RST_BUS_OTG>; 251 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "mc"; 253 phys = <&usbphy 0>; 254 phy-names = "usb"; 255 extcon = <&usbphy 0>; 256 status = "disabled"; 257 }; 258 259 usbphy: phy@1c19400 { 260 compatible = "allwinner,sun50i-a64-usb-phy"; 261 reg = <0x01c19400 0x14>, 262 <0x01c1a800 0x4>, 263 <0x01c1b800 0x4>; 264 reg-names = "phy_ctrl", 265 "pmu0", 266 "pmu1"; 267 clocks = <&ccu CLK_USB_PHY0>, 268 <&ccu CLK_USB_PHY1>; 269 clock-names = "usb0_phy", 270 "usb1_phy"; 271 resets = <&ccu RST_USB_PHY0>, 272 <&ccu RST_USB_PHY1>; 273 reset-names = "usb0_reset", 274 "usb1_reset"; 275 status = "disabled"; 276 #phy-cells = <1>; 277 }; 278 279 ehci0: usb@1c1a000 { 280 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 281 reg = <0x01c1a000 0x100>; 282 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&ccu CLK_BUS_OHCI0>, 284 <&ccu CLK_BUS_EHCI0>, 285 <&ccu CLK_USB_OHCI0>; 286 resets = <&ccu RST_BUS_OHCI0>, 287 <&ccu RST_BUS_EHCI0>; 288 status = "disabled"; 289 }; 290 291 ohci0: usb@1c1a400 { 292 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 293 reg = <0x01c1a400 0x100>; 294 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&ccu CLK_BUS_OHCI0>, 296 <&ccu CLK_USB_OHCI0>; 297 resets = <&ccu RST_BUS_OHCI0>; 298 status = "disabled"; 299 }; 300 301 ehci1: usb@1c1b000 { 302 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 303 reg = <0x01c1b000 0x100>; 304 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&ccu CLK_BUS_OHCI1>, 306 <&ccu CLK_BUS_EHCI1>, 307 <&ccu CLK_USB_OHCI1>; 308 resets = <&ccu RST_BUS_OHCI1>, 309 <&ccu RST_BUS_EHCI1>; 310 phys = <&usbphy 1>; 311 phy-names = "usb"; 312 status = "disabled"; 313 }; 314 315 ohci1: usb@1c1b400 { 316 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 317 reg = <0x01c1b400 0x100>; 318 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&ccu CLK_BUS_OHCI1>, 320 <&ccu CLK_USB_OHCI1>; 321 resets = <&ccu RST_BUS_OHCI1>; 322 phys = <&usbphy 1>; 323 phy-names = "usb"; 324 status = "disabled"; 325 }; 326 327 ccu: clock@1c20000 { 328 compatible = "allwinner,sun50i-a64-ccu"; 329 reg = <0x01c20000 0x400>; 330 clocks = <&osc24M>, <&osc32k>; 331 clock-names = "hosc", "losc"; 332 #clock-cells = <1>; 333 #reset-cells = <1>; 334 }; 335 336 pio: pinctrl@1c20800 { 337 compatible = "allwinner,sun50i-a64-pinctrl"; 338 reg = <0x01c20800 0x400>; 339 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&ccu 58>; 343 gpio-controller; 344 #gpio-cells = <3>; 345 interrupt-controller; 346 #interrupt-cells = <3>; 347 348 i2c0_pins: i2c0_pins { 349 pins = "PH0", "PH1"; 350 function = "i2c0"; 351 }; 352 353 i2c1_pins: i2c1_pins { 354 pins = "PH2", "PH3"; 355 function = "i2c1"; 356 }; 357 358 mmc0_pins: mmc0-pins { 359 pins = "PF0", "PF1", "PF2", "PF3", 360 "PF4", "PF5"; 361 function = "mmc0"; 362 drive-strength = <30>; 363 bias-pull-up; 364 }; 365 366 mmc1_pins: mmc1-pins { 367 pins = "PG0", "PG1", "PG2", "PG3", 368 "PG4", "PG5"; 369 function = "mmc1"; 370 drive-strength = <30>; 371 bias-pull-up; 372 }; 373 374 mmc2_pins: mmc2-pins { 375 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 376 "PC10","PC11", "PC12", "PC13", 377 "PC14", "PC15", "PC16"; 378 function = "mmc2"; 379 drive-strength = <30>; 380 bias-pull-up; 381 }; 382 383 pwm_pin: pwm_pin { 384 pins = "PD22"; 385 function = "pwm"; 386 }; 387 388 rmii_pins: rmii_pins { 389 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 390 "PD18", "PD19", "PD20", "PD22", "PD23"; 391 function = "emac"; 392 drive-strength = <40>; 393 }; 394 395 rgmii_pins: rgmii_pins { 396 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 397 "PD13", "PD15", "PD16", "PD17", "PD18", 398 "PD19", "PD20", "PD21", "PD22", "PD23"; 399 function = "emac"; 400 drive-strength = <40>; 401 }; 402 403 spdif_tx_pin: spdif { 404 pins = "PH8"; 405 function = "spdif"; 406 }; 407 408 spi0_pins: spi0 { 409 pins = "PC0", "PC1", "PC2", "PC3"; 410 function = "spi0"; 411 }; 412 413 spi1_pins: spi1 { 414 pins = "PD0", "PD1", "PD2", "PD3"; 415 function = "spi1"; 416 }; 417 418 uart0_pins_a: uart0 { 419 pins = "PB8", "PB9"; 420 function = "uart0"; 421 }; 422 423 uart1_pins: uart1_pins { 424 pins = "PG6", "PG7"; 425 function = "uart1"; 426 }; 427 428 uart1_rts_cts_pins: uart1_rts_cts_pins { 429 pins = "PG8", "PG9"; 430 function = "uart1"; 431 }; 432 433 uart2_pins: uart2-pins { 434 pins = "PB0", "PB1"; 435 function = "uart2"; 436 }; 437 438 uart3_pins: uart3-pins { 439 pins = "PD0", "PD1"; 440 function = "uart3"; 441 }; 442 443 uart4_pins: uart4-pins { 444 pins = "PD2", "PD3"; 445 function = "uart4"; 446 }; 447 448 uart4_rts_cts_pins: uart4-rts-cts-pins { 449 pins = "PD4", "PD5"; 450 function = "uart4"; 451 }; 452 }; 453 454 spdif: spdif@1c21000 { 455 #sound-dai-cells = <0>; 456 compatible = "allwinner,sun50i-a64-spdif", 457 "allwinner,sun8i-h3-spdif"; 458 reg = <0x01c21000 0x400>; 459 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 461 resets = <&ccu RST_BUS_SPDIF>; 462 clock-names = "apb", "spdif"; 463 dmas = <&dma 2>; 464 dma-names = "tx"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&spdif_tx_pin>; 467 status = "disabled"; 468 }; 469 470 i2s0: i2s@1c22000 { 471 #sound-dai-cells = <0>; 472 compatible = "allwinner,sun50i-a64-i2s", 473 "allwinner,sun8i-h3-i2s"; 474 reg = <0x01c22000 0x400>; 475 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 477 clock-names = "apb", "mod"; 478 resets = <&ccu RST_BUS_I2S0>; 479 dma-names = "rx", "tx"; 480 dmas = <&dma 3>, <&dma 3>; 481 status = "disabled"; 482 }; 483 484 i2s1: i2s@1c22400 { 485 #sound-dai-cells = <0>; 486 compatible = "allwinner,sun50i-a64-i2s", 487 "allwinner,sun8i-h3-i2s"; 488 reg = <0x01c22400 0x400>; 489 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 491 clock-names = "apb", "mod"; 492 resets = <&ccu RST_BUS_I2S1>; 493 dma-names = "rx", "tx"; 494 dmas = <&dma 4>, <&dma 4>; 495 status = "disabled"; 496 }; 497 498 uart0: serial@1c28000 { 499 compatible = "snps,dw-apb-uart"; 500 reg = <0x01c28000 0x400>; 501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 502 reg-shift = <2>; 503 reg-io-width = <4>; 504 clocks = <&ccu CLK_BUS_UART0>; 505 resets = <&ccu RST_BUS_UART0>; 506 status = "disabled"; 507 }; 508 509 uart1: serial@1c28400 { 510 compatible = "snps,dw-apb-uart"; 511 reg = <0x01c28400 0x400>; 512 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 clocks = <&ccu CLK_BUS_UART1>; 516 resets = <&ccu RST_BUS_UART1>; 517 status = "disabled"; 518 }; 519 520 uart2: serial@1c28800 { 521 compatible = "snps,dw-apb-uart"; 522 reg = <0x01c28800 0x400>; 523 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 524 reg-shift = <2>; 525 reg-io-width = <4>; 526 clocks = <&ccu CLK_BUS_UART2>; 527 resets = <&ccu RST_BUS_UART2>; 528 status = "disabled"; 529 }; 530 531 uart3: serial@1c28c00 { 532 compatible = "snps,dw-apb-uart"; 533 reg = <0x01c28c00 0x400>; 534 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 535 reg-shift = <2>; 536 reg-io-width = <4>; 537 clocks = <&ccu CLK_BUS_UART3>; 538 resets = <&ccu RST_BUS_UART3>; 539 status = "disabled"; 540 }; 541 542 uart4: serial@1c29000 { 543 compatible = "snps,dw-apb-uart"; 544 reg = <0x01c29000 0x400>; 545 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 546 reg-shift = <2>; 547 reg-io-width = <4>; 548 clocks = <&ccu CLK_BUS_UART4>; 549 resets = <&ccu RST_BUS_UART4>; 550 status = "disabled"; 551 }; 552 553 i2c0: i2c@1c2ac00 { 554 compatible = "allwinner,sun6i-a31-i2c"; 555 reg = <0x01c2ac00 0x400>; 556 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&ccu CLK_BUS_I2C0>; 558 resets = <&ccu RST_BUS_I2C0>; 559 status = "disabled"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 }; 563 564 i2c1: i2c@1c2b000 { 565 compatible = "allwinner,sun6i-a31-i2c"; 566 reg = <0x01c2b000 0x400>; 567 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&ccu CLK_BUS_I2C1>; 569 resets = <&ccu RST_BUS_I2C1>; 570 status = "disabled"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 }; 574 575 i2c2: i2c@1c2b400 { 576 compatible = "allwinner,sun6i-a31-i2c"; 577 reg = <0x01c2b400 0x400>; 578 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&ccu CLK_BUS_I2C2>; 580 resets = <&ccu RST_BUS_I2C2>; 581 status = "disabled"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 }; 585 586 587 spi0: spi@1c68000 { 588 compatible = "allwinner,sun8i-h3-spi"; 589 reg = <0x01c68000 0x1000>; 590 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 592 clock-names = "ahb", "mod"; 593 dmas = <&dma 23>, <&dma 23>; 594 dma-names = "rx", "tx"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&spi0_pins>; 597 resets = <&ccu RST_BUS_SPI0>; 598 status = "disabled"; 599 num-cs = <1>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 }; 603 604 spi1: spi@1c69000 { 605 compatible = "allwinner,sun8i-h3-spi"; 606 reg = <0x01c69000 0x1000>; 607 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 609 clock-names = "ahb", "mod"; 610 dmas = <&dma 24>, <&dma 24>; 611 dma-names = "rx", "tx"; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&spi1_pins>; 614 resets = <&ccu RST_BUS_SPI1>; 615 status = "disabled"; 616 num-cs = <1>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 }; 620 621 emac: ethernet@1c30000 { 622 compatible = "allwinner,sun50i-a64-emac"; 623 syscon = <&syscon>; 624 reg = <0x01c30000 0x10000>; 625 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "macirq"; 627 resets = <&ccu RST_BUS_EMAC>; 628 reset-names = "stmmaceth"; 629 clocks = <&ccu CLK_BUS_EMAC>; 630 clock-names = "stmmaceth"; 631 status = "disabled"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 mdio: mdio { 636 compatible = "snps,dwmac-mdio"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 }; 640 }; 641 642 gic: interrupt-controller@1c81000 { 643 compatible = "arm,gic-400"; 644 reg = <0x01c81000 0x1000>, 645 <0x01c82000 0x2000>, 646 <0x01c84000 0x2000>, 647 <0x01c86000 0x2000>; 648 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 649 interrupt-controller; 650 #interrupt-cells = <3>; 651 }; 652 653 pwm: pwm@1c21400 { 654 compatible = "allwinner,sun50i-a64-pwm", 655 "allwinner,sun5i-a13-pwm"; 656 reg = <0x01c21400 0x400>; 657 clocks = <&osc24M>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pwm_pin>; 660 #pwm-cells = <3>; 661 status = "disabled"; 662 }; 663 664 rtc: rtc@1f00000 { 665 compatible = "allwinner,sun6i-a31-rtc"; 666 reg = <0x01f00000 0x54>; 667 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 669 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 670 clocks = <&osc32k>; 671 #clock-cells = <1>; 672 }; 673 674 r_intc: interrupt-controller@1f00c00 { 675 compatible = "allwinner,sun50i-a64-r-intc", 676 "allwinner,sun6i-a31-r-intc"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 reg = <0x01f00c00 0x400>; 680 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 681 }; 682 683 r_ccu: clock@1f01400 { 684 compatible = "allwinner,sun50i-a64-r-ccu"; 685 reg = <0x01f01400 0x100>; 686 clocks = <&osc24M>, <&osc32k>, <&iosc>, 687 <&ccu 11>; 688 clock-names = "hosc", "losc", "iosc", "pll-periph"; 689 #clock-cells = <1>; 690 #reset-cells = <1>; 691 }; 692 693 r_i2c: i2c@1f02400 { 694 compatible = "allwinner,sun50i-a64-i2c", 695 "allwinner,sun6i-a31-i2c"; 696 reg = <0x01f02400 0x400>; 697 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&r_ccu CLK_APB0_I2C>; 699 resets = <&r_ccu RST_APB0_I2C>; 700 status = "disabled"; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 }; 704 705 r_pwm: pwm@1f03800 { 706 compatible = "allwinner,sun50i-a64-pwm", 707 "allwinner,sun5i-a13-pwm"; 708 reg = <0x01f03800 0x400>; 709 clocks = <&osc24M>; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&r_pwm_pin>; 712 #pwm-cells = <3>; 713 status = "disabled"; 714 }; 715 716 r_pio: pinctrl@1f02c00 { 717 compatible = "allwinner,sun50i-a64-r-pinctrl"; 718 reg = <0x01f02c00 0x400>; 719 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 721 clock-names = "apb", "hosc", "losc"; 722 gpio-controller; 723 #gpio-cells = <3>; 724 interrupt-controller; 725 #interrupt-cells = <3>; 726 727 r_i2c_pins_a: i2c-a { 728 pins = "PL8", "PL9"; 729 function = "s_i2c"; 730 }; 731 732 r_pwm_pin: pwm { 733 pins = "PL10"; 734 function = "s_pwm"; 735 }; 736 737 r_rsb_pins: rsb { 738 pins = "PL0", "PL1"; 739 function = "s_rsb"; 740 }; 741 }; 742 743 r_rsb: rsb@1f03400 { 744 compatible = "allwinner,sun8i-a23-rsb"; 745 reg = <0x01f03400 0x400>; 746 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&r_ccu 6>; 748 clock-frequency = <3000000>; 749 resets = <&r_ccu 2>; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&r_rsb_pins>; 752 status = "disabled"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 }; 756 757 wdt0: watchdog@1c20ca0 { 758 compatible = "allwinner,sun50i-a64-wdt", 759 "allwinner,sun6i-a31-wdt"; 760 reg = <0x01c20ca0 0x20>; 761 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 762 }; 763 }; 764}; 765