1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 de2@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_DE>, 232 <&ccu CLK_BUS_DE>; 233 clock-names = "mod", 234 "bus"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 reg = <1>; 255 256 mixer0_out_tcon0: endpoint { 257 remote-endpoint = <&tcon0_in_mixer0>; 258 }; 259 }; 260 }; 261 }; 262 263 mixer1: mixer@200000 { 264 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 265 reg = <0x200000 0x100000>; 266 clocks = <&display_clocks CLK_BUS_MIXER1>, 267 <&display_clocks CLK_MIXER1>; 268 clock-names = "bus", 269 "mod"; 270 resets = <&display_clocks RST_MIXER1>; 271 272 ports { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 mixer1_out: port@1 { 277 reg = <1>; 278 279 mixer1_out_tcon1: endpoint { 280 remote-endpoint = <&tcon1_in_mixer1>; 281 }; 282 }; 283 }; 284 }; 285 }; 286 287 syscon: syscon@1c00000 { 288 compatible = "allwinner,sun50i-a64-system-control"; 289 reg = <0x01c00000 0x1000>; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges; 293 294 sram_c: sram@18000 { 295 compatible = "mmio-sram"; 296 reg = <0x00018000 0x28000>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 ranges = <0 0x00018000 0x28000>; 300 301 de2_sram: sram-section@0 { 302 compatible = "allwinner,sun50i-a64-sram-c"; 303 reg = <0x0000 0x28000>; 304 }; 305 }; 306 307 sram_c1: sram@1d00000 { 308 compatible = "mmio-sram"; 309 reg = <0x01d00000 0x40000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges = <0 0x01d00000 0x40000>; 313 314 ve_sram: sram-section@0 { 315 compatible = "allwinner,sun50i-a64-sram-c1", 316 "allwinner,sun4i-a10-sram-c1"; 317 reg = <0x000000 0x40000>; 318 }; 319 }; 320 }; 321 322 dma: dma-controller@1c02000 { 323 compatible = "allwinner,sun50i-a64-dma"; 324 reg = <0x01c02000 0x1000>; 325 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&ccu CLK_BUS_DMA>; 327 dma-channels = <8>; 328 dma-requests = <27>; 329 resets = <&ccu RST_BUS_DMA>; 330 #dma-cells = <1>; 331 }; 332 333 tcon0: lcd-controller@1c0c000 { 334 compatible = "allwinner,sun50i-a64-tcon-lcd", 335 "allwinner,sun8i-a83t-tcon-lcd"; 336 reg = <0x01c0c000 0x1000>; 337 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 339 clock-names = "ahb", "tcon-ch0"; 340 clock-output-names = "tcon-pixel-clock"; 341 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 342 reset-names = "lcd", "lvds"; 343 344 ports { 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 tcon0_in: port@0 { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0>; 352 353 tcon0_in_mixer0: endpoint@0 { 354 reg = <0>; 355 remote-endpoint = <&mixer0_out_tcon0>; 356 }; 357 }; 358 359 tcon0_out: port@1 { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <1>; 363 }; 364 }; 365 }; 366 367 tcon1: lcd-controller@1c0d000 { 368 compatible = "allwinner,sun50i-a64-tcon-tv", 369 "allwinner,sun8i-a83t-tcon-tv"; 370 reg = <0x01c0d000 0x1000>; 371 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 373 clock-names = "ahb", "tcon-ch1"; 374 resets = <&ccu RST_BUS_TCON1>; 375 reset-names = "lcd"; 376 377 ports { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 381 tcon1_in: port@0 { 382 reg = <0>; 383 384 tcon1_in_mixer1: endpoint { 385 remote-endpoint = <&mixer1_out_tcon1>; 386 }; 387 }; 388 389 tcon1_out: port@1 { 390 #address-cells = <1>; 391 #size-cells = <0>; 392 reg = <1>; 393 394 tcon1_out_hdmi: endpoint@1 { 395 reg = <1>; 396 remote-endpoint = <&hdmi_in_tcon1>; 397 }; 398 }; 399 }; 400 }; 401 402 video-codec@1c0e000 { 403 compatible = "allwinner,sun50i-h5-video-engine"; 404 reg = <0x01c0e000 0x1000>; 405 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 406 <&ccu CLK_DRAM_VE>; 407 clock-names = "ahb", "mod", "ram"; 408 resets = <&ccu RST_BUS_VE>; 409 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 410 allwinner,sram = <&ve_sram 1>; 411 }; 412 413 mmc0: mmc@1c0f000 { 414 compatible = "allwinner,sun50i-a64-mmc"; 415 reg = <0x01c0f000 0x1000>; 416 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 417 clock-names = "ahb", "mmc"; 418 resets = <&ccu RST_BUS_MMC0>; 419 reset-names = "ahb"; 420 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 421 max-frequency = <150000000>; 422 status = "disabled"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 }; 426 427 mmc1: mmc@1c10000 { 428 compatible = "allwinner,sun50i-a64-mmc"; 429 reg = <0x01c10000 0x1000>; 430 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 431 clock-names = "ahb", "mmc"; 432 resets = <&ccu RST_BUS_MMC1>; 433 reset-names = "ahb"; 434 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 435 max-frequency = <150000000>; 436 status = "disabled"; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 }; 440 441 mmc2: mmc@1c11000 { 442 compatible = "allwinner,sun50i-a64-emmc"; 443 reg = <0x01c11000 0x1000>; 444 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 445 clock-names = "ahb", "mmc"; 446 resets = <&ccu RST_BUS_MMC2>; 447 reset-names = "ahb"; 448 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 449 max-frequency = <200000000>; 450 status = "disabled"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 }; 454 455 sid: eeprom@1c14000 { 456 compatible = "allwinner,sun50i-a64-sid"; 457 reg = <0x1c14000 0x400>; 458 }; 459 460 usb_otg: usb@1c19000 { 461 compatible = "allwinner,sun8i-a33-musb"; 462 reg = <0x01c19000 0x0400>; 463 clocks = <&ccu CLK_BUS_OTG>; 464 resets = <&ccu RST_BUS_OTG>; 465 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-names = "mc"; 467 phys = <&usbphy 0>; 468 phy-names = "usb"; 469 extcon = <&usbphy 0>; 470 status = "disabled"; 471 }; 472 473 usbphy: phy@1c19400 { 474 compatible = "allwinner,sun50i-a64-usb-phy"; 475 reg = <0x01c19400 0x14>, 476 <0x01c1a800 0x4>, 477 <0x01c1b800 0x4>; 478 reg-names = "phy_ctrl", 479 "pmu0", 480 "pmu1"; 481 clocks = <&ccu CLK_USB_PHY0>, 482 <&ccu CLK_USB_PHY1>; 483 clock-names = "usb0_phy", 484 "usb1_phy"; 485 resets = <&ccu RST_USB_PHY0>, 486 <&ccu RST_USB_PHY1>; 487 reset-names = "usb0_reset", 488 "usb1_reset"; 489 status = "disabled"; 490 #phy-cells = <1>; 491 }; 492 493 ehci0: usb@1c1a000 { 494 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 495 reg = <0x01c1a000 0x100>; 496 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&ccu CLK_BUS_OHCI0>, 498 <&ccu CLK_BUS_EHCI0>, 499 <&ccu CLK_USB_OHCI0>; 500 resets = <&ccu RST_BUS_OHCI0>, 501 <&ccu RST_BUS_EHCI0>; 502 status = "disabled"; 503 }; 504 505 ohci0: usb@1c1a400 { 506 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 507 reg = <0x01c1a400 0x100>; 508 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&ccu CLK_BUS_OHCI0>, 510 <&ccu CLK_USB_OHCI0>; 511 resets = <&ccu RST_BUS_OHCI0>; 512 status = "disabled"; 513 }; 514 515 ehci1: usb@1c1b000 { 516 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 517 reg = <0x01c1b000 0x100>; 518 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&ccu CLK_BUS_OHCI1>, 520 <&ccu CLK_BUS_EHCI1>, 521 <&ccu CLK_USB_OHCI1>; 522 resets = <&ccu RST_BUS_OHCI1>, 523 <&ccu RST_BUS_EHCI1>; 524 phys = <&usbphy 1>; 525 phy-names = "usb"; 526 status = "disabled"; 527 }; 528 529 ohci1: usb@1c1b400 { 530 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 531 reg = <0x01c1b400 0x100>; 532 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&ccu CLK_BUS_OHCI1>, 534 <&ccu CLK_USB_OHCI1>; 535 resets = <&ccu RST_BUS_OHCI1>; 536 phys = <&usbphy 1>; 537 phy-names = "usb"; 538 status = "disabled"; 539 }; 540 541 ccu: clock@1c20000 { 542 compatible = "allwinner,sun50i-a64-ccu"; 543 reg = <0x01c20000 0x400>; 544 clocks = <&osc24M>, <&rtc 0>; 545 clock-names = "hosc", "losc"; 546 #clock-cells = <1>; 547 #reset-cells = <1>; 548 }; 549 550 pio: pinctrl@1c20800 { 551 compatible = "allwinner,sun50i-a64-pinctrl"; 552 reg = <0x01c20800 0x400>; 553 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&ccu 58>; 557 gpio-controller; 558 #gpio-cells = <3>; 559 interrupt-controller; 560 #interrupt-cells = <3>; 561 562 csi_pins: csi-pins { 563 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 564 "PE7", "PE8", "PE9", "PE10", "PE11"; 565 function = "csi"; 566 }; 567 568 i2c0_pins: i2c0_pins { 569 pins = "PH0", "PH1"; 570 function = "i2c0"; 571 }; 572 573 i2c1_pins: i2c1_pins { 574 pins = "PH2", "PH3"; 575 function = "i2c1"; 576 }; 577 578 mmc0_pins: mmc0-pins { 579 pins = "PF0", "PF1", "PF2", "PF3", 580 "PF4", "PF5"; 581 function = "mmc0"; 582 drive-strength = <30>; 583 bias-pull-up; 584 }; 585 586 mmc1_pins: mmc1-pins { 587 pins = "PG0", "PG1", "PG2", "PG3", 588 "PG4", "PG5"; 589 function = "mmc1"; 590 drive-strength = <30>; 591 bias-pull-up; 592 }; 593 594 mmc2_pins: mmc2-pins { 595 pins = "PC5", "PC6", "PC8", "PC9", 596 "PC10","PC11", "PC12", "PC13", 597 "PC14", "PC15", "PC16"; 598 function = "mmc2"; 599 drive-strength = <30>; 600 bias-pull-up; 601 }; 602 603 mmc2_ds_pin: mmc2-ds-pin { 604 pins = "PC1"; 605 function = "mmc2"; 606 drive-strength = <30>; 607 bias-pull-up; 608 }; 609 610 pwm_pin: pwm_pin { 611 pins = "PD22"; 612 function = "pwm"; 613 }; 614 615 rmii_pins: rmii_pins { 616 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 617 "PD18", "PD19", "PD20", "PD22", "PD23"; 618 function = "emac"; 619 drive-strength = <40>; 620 }; 621 622 rgmii_pins: rgmii_pins { 623 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 624 "PD13", "PD15", "PD16", "PD17", "PD18", 625 "PD19", "PD20", "PD21", "PD22", "PD23"; 626 function = "emac"; 627 drive-strength = <40>; 628 }; 629 630 spdif_tx_pin: spdif { 631 pins = "PH8"; 632 function = "spdif"; 633 }; 634 635 spi0_pins: spi0 { 636 pins = "PC0", "PC1", "PC2", "PC3"; 637 function = "spi0"; 638 }; 639 640 spi1_pins: spi1 { 641 pins = "PD0", "PD1", "PD2", "PD3"; 642 function = "spi1"; 643 }; 644 645 uart0_pb_pins: uart0-pb-pins { 646 pins = "PB8", "PB9"; 647 function = "uart0"; 648 }; 649 650 uart1_pins: uart1_pins { 651 pins = "PG6", "PG7"; 652 function = "uart1"; 653 }; 654 655 uart1_rts_cts_pins: uart1_rts_cts_pins { 656 pins = "PG8", "PG9"; 657 function = "uart1"; 658 }; 659 660 uart2_pins: uart2-pins { 661 pins = "PB0", "PB1"; 662 function = "uart2"; 663 }; 664 665 uart3_pins: uart3-pins { 666 pins = "PD0", "PD1"; 667 function = "uart3"; 668 }; 669 670 uart4_pins: uart4-pins { 671 pins = "PD2", "PD3"; 672 function = "uart4"; 673 }; 674 675 uart4_rts_cts_pins: uart4-rts-cts-pins { 676 pins = "PD4", "PD5"; 677 function = "uart4"; 678 }; 679 }; 680 681 spdif: spdif@1c21000 { 682 #sound-dai-cells = <0>; 683 compatible = "allwinner,sun50i-a64-spdif", 684 "allwinner,sun8i-h3-spdif"; 685 reg = <0x01c21000 0x400>; 686 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 688 resets = <&ccu RST_BUS_SPDIF>; 689 clock-names = "apb", "spdif"; 690 dmas = <&dma 2>; 691 dma-names = "tx"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&spdif_tx_pin>; 694 status = "disabled"; 695 }; 696 697 i2s0: i2s@1c22000 { 698 #sound-dai-cells = <0>; 699 compatible = "allwinner,sun50i-a64-i2s", 700 "allwinner,sun8i-h3-i2s"; 701 reg = <0x01c22000 0x400>; 702 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 704 clock-names = "apb", "mod"; 705 resets = <&ccu RST_BUS_I2S0>; 706 dma-names = "rx", "tx"; 707 dmas = <&dma 3>, <&dma 3>; 708 status = "disabled"; 709 }; 710 711 i2s1: i2s@1c22400 { 712 #sound-dai-cells = <0>; 713 compatible = "allwinner,sun50i-a64-i2s", 714 "allwinner,sun8i-h3-i2s"; 715 reg = <0x01c22400 0x400>; 716 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 718 clock-names = "apb", "mod"; 719 resets = <&ccu RST_BUS_I2S1>; 720 dma-names = "rx", "tx"; 721 dmas = <&dma 4>, <&dma 4>; 722 status = "disabled"; 723 }; 724 725 dai: dai@1c22c00 { 726 #sound-dai-cells = <0>; 727 compatible = "allwinner,sun50i-a64-codec-i2s"; 728 reg = <0x01c22c00 0x200>; 729 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 731 clock-names = "apb", "mod"; 732 resets = <&ccu RST_BUS_CODEC>; 733 reset-names = "rst"; 734 dmas = <&dma 15>, <&dma 15>; 735 dma-names = "rx", "tx"; 736 status = "disabled"; 737 }; 738 739 codec: codec@1c22e00 { 740 #sound-dai-cells = <0>; 741 compatible = "allwinner,sun8i-a33-codec"; 742 reg = <0x01c22e00 0x600>; 743 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 745 clock-names = "bus", "mod"; 746 status = "disabled"; 747 }; 748 749 uart0: serial@1c28000 { 750 compatible = "snps,dw-apb-uart"; 751 reg = <0x01c28000 0x400>; 752 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 753 reg-shift = <2>; 754 reg-io-width = <4>; 755 clocks = <&ccu CLK_BUS_UART0>; 756 resets = <&ccu RST_BUS_UART0>; 757 status = "disabled"; 758 }; 759 760 uart1: serial@1c28400 { 761 compatible = "snps,dw-apb-uart"; 762 reg = <0x01c28400 0x400>; 763 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 764 reg-shift = <2>; 765 reg-io-width = <4>; 766 clocks = <&ccu CLK_BUS_UART1>; 767 resets = <&ccu RST_BUS_UART1>; 768 status = "disabled"; 769 }; 770 771 uart2: serial@1c28800 { 772 compatible = "snps,dw-apb-uart"; 773 reg = <0x01c28800 0x400>; 774 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 775 reg-shift = <2>; 776 reg-io-width = <4>; 777 clocks = <&ccu CLK_BUS_UART2>; 778 resets = <&ccu RST_BUS_UART2>; 779 status = "disabled"; 780 }; 781 782 uart3: serial@1c28c00 { 783 compatible = "snps,dw-apb-uart"; 784 reg = <0x01c28c00 0x400>; 785 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 786 reg-shift = <2>; 787 reg-io-width = <4>; 788 clocks = <&ccu CLK_BUS_UART3>; 789 resets = <&ccu RST_BUS_UART3>; 790 status = "disabled"; 791 }; 792 793 uart4: serial@1c29000 { 794 compatible = "snps,dw-apb-uart"; 795 reg = <0x01c29000 0x400>; 796 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 797 reg-shift = <2>; 798 reg-io-width = <4>; 799 clocks = <&ccu CLK_BUS_UART4>; 800 resets = <&ccu RST_BUS_UART4>; 801 status = "disabled"; 802 }; 803 804 i2c0: i2c@1c2ac00 { 805 compatible = "allwinner,sun6i-a31-i2c"; 806 reg = <0x01c2ac00 0x400>; 807 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&ccu CLK_BUS_I2C0>; 809 resets = <&ccu RST_BUS_I2C0>; 810 status = "disabled"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 }; 814 815 i2c1: i2c@1c2b000 { 816 compatible = "allwinner,sun6i-a31-i2c"; 817 reg = <0x01c2b000 0x400>; 818 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&ccu CLK_BUS_I2C1>; 820 resets = <&ccu RST_BUS_I2C1>; 821 status = "disabled"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 }; 825 826 i2c2: i2c@1c2b400 { 827 compatible = "allwinner,sun6i-a31-i2c"; 828 reg = <0x01c2b400 0x400>; 829 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&ccu CLK_BUS_I2C2>; 831 resets = <&ccu RST_BUS_I2C2>; 832 status = "disabled"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 }; 836 837 838 spi0: spi@1c68000 { 839 compatible = "allwinner,sun8i-h3-spi"; 840 reg = <0x01c68000 0x1000>; 841 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 843 clock-names = "ahb", "mod"; 844 dmas = <&dma 23>, <&dma 23>; 845 dma-names = "rx", "tx"; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&spi0_pins>; 848 resets = <&ccu RST_BUS_SPI0>; 849 status = "disabled"; 850 num-cs = <1>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 }; 854 855 spi1: spi@1c69000 { 856 compatible = "allwinner,sun8i-h3-spi"; 857 reg = <0x01c69000 0x1000>; 858 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 860 clock-names = "ahb", "mod"; 861 dmas = <&dma 24>, <&dma 24>; 862 dma-names = "rx", "tx"; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&spi1_pins>; 865 resets = <&ccu RST_BUS_SPI1>; 866 status = "disabled"; 867 num-cs = <1>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 }; 871 872 emac: ethernet@1c30000 { 873 compatible = "allwinner,sun50i-a64-emac"; 874 syscon = <&syscon>; 875 reg = <0x01c30000 0x10000>; 876 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-names = "macirq"; 878 resets = <&ccu RST_BUS_EMAC>; 879 reset-names = "stmmaceth"; 880 clocks = <&ccu CLK_BUS_EMAC>; 881 clock-names = "stmmaceth"; 882 status = "disabled"; 883 884 mdio: mdio { 885 compatible = "snps,dwmac-mdio"; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 }; 889 }; 890 891 mali: gpu@1c40000 { 892 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 893 reg = <0x01c40000 0x10000>; 894 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 901 interrupt-names = "gp", 902 "gpmmu", 903 "pp0", 904 "ppmmu0", 905 "pp1", 906 "ppmmu1", 907 "pmu"; 908 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 909 clock-names = "bus", "core"; 910 resets = <&ccu RST_BUS_GPU>; 911 }; 912 913 gic: interrupt-controller@1c81000 { 914 compatible = "arm,gic-400"; 915 reg = <0x01c81000 0x1000>, 916 <0x01c82000 0x2000>, 917 <0x01c84000 0x2000>, 918 <0x01c86000 0x2000>; 919 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 920 interrupt-controller; 921 #interrupt-cells = <3>; 922 }; 923 924 pwm: pwm@1c21400 { 925 compatible = "allwinner,sun50i-a64-pwm", 926 "allwinner,sun5i-a13-pwm"; 927 reg = <0x01c21400 0x400>; 928 clocks = <&osc24M>; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&pwm_pin>; 931 #pwm-cells = <3>; 932 status = "disabled"; 933 }; 934 935 csi: csi@1cb0000 { 936 compatible = "allwinner,sun50i-a64-csi"; 937 reg = <0x01cb0000 0x1000>; 938 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&ccu CLK_BUS_CSI>, 940 <&ccu CLK_CSI_SCLK>, 941 <&ccu CLK_DRAM_CSI>; 942 clock-names = "bus", "mod", "ram"; 943 resets = <&ccu RST_BUS_CSI>; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&csi_pins>; 946 status = "disabled"; 947 }; 948 949 hdmi: hdmi@1ee0000 { 950 compatible = "allwinner,sun50i-a64-dw-hdmi", 951 "allwinner,sun8i-a83t-dw-hdmi"; 952 reg = <0x01ee0000 0x10000>; 953 reg-io-width = <1>; 954 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 956 <&ccu CLK_HDMI>; 957 clock-names = "iahb", "isfr", "tmds"; 958 resets = <&ccu RST_BUS_HDMI1>; 959 reset-names = "ctrl"; 960 phys = <&hdmi_phy>; 961 phy-names = "hdmi-phy"; 962 status = "disabled"; 963 964 ports { 965 #address-cells = <1>; 966 #size-cells = <0>; 967 968 hdmi_in: port@0 { 969 reg = <0>; 970 971 hdmi_in_tcon1: endpoint { 972 remote-endpoint = <&tcon1_out_hdmi>; 973 }; 974 }; 975 976 hdmi_out: port@1 { 977 reg = <1>; 978 }; 979 }; 980 }; 981 982 hdmi_phy: hdmi-phy@1ef0000 { 983 compatible = "allwinner,sun50i-a64-hdmi-phy"; 984 reg = <0x01ef0000 0x10000>; 985 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 986 <&ccu 7>; 987 clock-names = "bus", "mod", "pll-0"; 988 resets = <&ccu RST_BUS_HDMI0>; 989 reset-names = "phy"; 990 #phy-cells = <0>; 991 }; 992 993 rtc: rtc@1f00000 { 994 compatible = "allwinner,sun50i-a64-rtc", 995 "allwinner,sun8i-h3-rtc"; 996 reg = <0x01f00000 0x400>; 997 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 999 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1000 clocks = <&osc32k>; 1001 #clock-cells = <1>; 1002 }; 1003 1004 r_intc: interrupt-controller@1f00c00 { 1005 compatible = "allwinner,sun50i-a64-r-intc", 1006 "allwinner,sun6i-a31-r-intc"; 1007 interrupt-controller; 1008 #interrupt-cells = <2>; 1009 reg = <0x01f00c00 0x400>; 1010 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1011 }; 1012 1013 r_ccu: clock@1f01400 { 1014 compatible = "allwinner,sun50i-a64-r-ccu"; 1015 reg = <0x01f01400 0x100>; 1016 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1017 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1018 #clock-cells = <1>; 1019 #reset-cells = <1>; 1020 }; 1021 1022 codec_analog: codec-analog@1f015c0 { 1023 compatible = "allwinner,sun50i-a64-codec-analog"; 1024 reg = <0x01f015c0 0x4>; 1025 status = "disabled"; 1026 }; 1027 1028 r_i2c: i2c@1f02400 { 1029 compatible = "allwinner,sun50i-a64-i2c", 1030 "allwinner,sun6i-a31-i2c"; 1031 reg = <0x01f02400 0x400>; 1032 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&r_ccu CLK_APB0_I2C>; 1034 resets = <&r_ccu RST_APB0_I2C>; 1035 status = "disabled"; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 }; 1039 1040 r_pwm: pwm@1f03800 { 1041 compatible = "allwinner,sun50i-a64-pwm", 1042 "allwinner,sun5i-a13-pwm"; 1043 reg = <0x01f03800 0x400>; 1044 clocks = <&osc24M>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&r_pwm_pin>; 1047 #pwm-cells = <3>; 1048 status = "disabled"; 1049 }; 1050 1051 r_pio: pinctrl@1f02c00 { 1052 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1053 reg = <0x01f02c00 0x400>; 1054 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1056 clock-names = "apb", "hosc", "losc"; 1057 gpio-controller; 1058 #gpio-cells = <3>; 1059 interrupt-controller; 1060 #interrupt-cells = <3>; 1061 1062 r_i2c_pl89_pins: r-i2c-pl89-pins { 1063 pins = "PL8", "PL9"; 1064 function = "s_i2c"; 1065 }; 1066 1067 r_pwm_pin: pwm { 1068 pins = "PL10"; 1069 function = "s_pwm"; 1070 }; 1071 1072 r_rsb_pins: rsb { 1073 pins = "PL0", "PL1"; 1074 function = "s_rsb"; 1075 }; 1076 }; 1077 1078 r_rsb: rsb@1f03400 { 1079 compatible = "allwinner,sun8i-a23-rsb"; 1080 reg = <0x01f03400 0x400>; 1081 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&r_ccu 6>; 1083 clock-frequency = <3000000>; 1084 resets = <&r_ccu 2>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&r_rsb_pins>; 1087 status = "disabled"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 }; 1091 1092 wdt0: watchdog@1c20ca0 { 1093 compatible = "allwinner,sun50i-a64-wdt", 1094 "allwinner,sun6i-a31-wdt"; 1095 reg = <0x01c20ca0 0x20>; 1096 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1097 }; 1098 }; 1099}; 1100