1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-r-ccu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/sun50i-a64-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/reset/sun8i-r-ccu.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 chosen { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 simplefb_lcd: framebuffer-lcd { 26 compatible = "allwinner,simple-framebuffer", 27 "simple-framebuffer"; 28 allwinner,pipeline = "mixer0-lcd0"; 29 clocks = <&ccu CLK_TCON0>, 30 <&display_clocks CLK_MIXER0>; 31 status = "disabled"; 32 }; 33 34 simplefb_hdmi: framebuffer-hdmi { 35 compatible = "allwinner,simple-framebuffer", 36 "simple-framebuffer"; 37 allwinner,pipeline = "mixer1-lcd1-hdmi"; 38 clocks = <&display_clocks CLK_MIXER1>, 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40 status = "disabled"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 reg = <0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2>; 54 }; 55 56 cpu1: cpu@1 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 reg = <1>; 60 enable-method = "psci"; 61 next-level-cache = <&L2>; 62 }; 63 64 cpu2: cpu@2 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 reg = <2>; 68 enable-method = "psci"; 69 next-level-cache = <&L2>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 reg = <3>; 76 enable-method = "psci"; 77 next-level-cache = <&L2>; 78 }; 79 80 L2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 }; 84 }; 85 86 de: display-engine { 87 compatible = "allwinner,sun50i-a64-display-engine"; 88 allwinner,pipelines = <&mixer0>, 89 <&mixer1>; 90 status = "disabled"; 91 }; 92 93 osc24M: osc24M_clk { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <24000000>; 97 clock-output-names = "osc24M"; 98 }; 99 100 osc32k: osc32k_clk { 101 #clock-cells = <0>; 102 compatible = "fixed-clock"; 103 clock-frequency = <32768>; 104 clock-output-names = "ext-osc32k"; 105 }; 106 107 pmu { 108 compatible = "arm,cortex-a53-pmu"; 109 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 113 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 114 }; 115 116 psci { 117 compatible = "arm,psci-0.2"; 118 method = "smc"; 119 }; 120 121 sound: sound { 122 compatible = "simple-audio-card"; 123 simple-audio-card,name = "sun50i-a64-audio"; 124 simple-audio-card,format = "i2s"; 125 simple-audio-card,frame-master = <&cpudai>; 126 simple-audio-card,bitclock-master = <&cpudai>; 127 simple-audio-card,mclk-fs = <128>; 128 simple-audio-card,aux-devs = <&codec_analog>; 129 simple-audio-card,routing = 130 "Left DAC", "AIF1 Slot 0 Left", 131 "Right DAC", "AIF1 Slot 0 Right", 132 "AIF1 Slot 0 Left ADC", "Left ADC", 133 "AIF1 Slot 0 Right ADC", "Right ADC"; 134 status = "disabled"; 135 136 cpudai: simple-audio-card,cpu { 137 sound-dai = <&dai>; 138 }; 139 140 link_codec: simple-audio-card,codec { 141 sound-dai = <&codec>; 142 }; 143 }; 144 145 sound_spdif { 146 compatible = "simple-audio-card"; 147 simple-audio-card,name = "On-board SPDIF"; 148 149 simple-audio-card,cpu { 150 sound-dai = <&spdif>; 151 }; 152 153 simple-audio-card,codec { 154 sound-dai = <&spdif_out>; 155 }; 156 }; 157 158 spdif_out: spdif-out { 159 #sound-dai-cells = <0>; 160 compatible = "linux,spdif-dit"; 161 }; 162 163 timer { 164 compatible = "arm,armv8-timer"; 165 allwinner,erratum-unknown1; 166 interrupts = <GIC_PPI 13 167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 168 <GIC_PPI 14 169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 170 <GIC_PPI 11 171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 172 <GIC_PPI 10 173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 174 }; 175 176 thermal-zones { 177 cpu_thermal: cpu0-thermal { 178 /* milliseconds */ 179 polling-delay-passive = <0>; 180 polling-delay = <0>; 181 thermal-sensors = <&ths 0>; 182 }; 183 184 gpu0_thermal: gpu0-thermal { 185 /* milliseconds */ 186 polling-delay-passive = <0>; 187 polling-delay = <0>; 188 thermal-sensors = <&ths 1>; 189 }; 190 191 gpu1_thermal: gpu1-thermal { 192 /* milliseconds */ 193 polling-delay-passive = <0>; 194 polling-delay = <0>; 195 thermal-sensors = <&ths 2>; 196 }; 197 }; 198 199 soc { 200 compatible = "simple-bus"; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges; 204 205 bus@1000000 { 206 compatible = "allwinner,sun50i-a64-de2"; 207 reg = <0x1000000 0x400000>; 208 allwinner,sram = <&de2_sram 1>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0 0x1000000 0x400000>; 212 213 display_clocks: clock@0 { 214 compatible = "allwinner,sun50i-a64-de2-clk"; 215 reg = <0x0 0x100000>; 216 clocks = <&ccu CLK_BUS_DE>, 217 <&ccu CLK_DE>; 218 clock-names = "bus", 219 "mod"; 220 resets = <&ccu RST_BUS_DE>; 221 #clock-cells = <1>; 222 #reset-cells = <1>; 223 }; 224 225 mixer0: mixer@100000 { 226 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 227 reg = <0x100000 0x100000>; 228 clocks = <&display_clocks CLK_BUS_MIXER0>, 229 <&display_clocks CLK_MIXER0>; 230 clock-names = "bus", 231 "mod"; 232 resets = <&display_clocks RST_MIXER0>; 233 234 ports { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 mixer0_out: port@1 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <1>; 242 243 mixer0_out_tcon0: endpoint@0 { 244 reg = <0>; 245 remote-endpoint = <&tcon0_in_mixer0>; 246 }; 247 248 mixer0_out_tcon1: endpoint@1 { 249 reg = <1>; 250 remote-endpoint = <&tcon1_in_mixer0>; 251 }; 252 }; 253 }; 254 }; 255 256 mixer1: mixer@200000 { 257 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 258 reg = <0x200000 0x100000>; 259 clocks = <&display_clocks CLK_BUS_MIXER1>, 260 <&display_clocks CLK_MIXER1>; 261 clock-names = "bus", 262 "mod"; 263 resets = <&display_clocks RST_MIXER1>; 264 265 ports { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 mixer1_out: port@1 { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 reg = <1>; 273 274 mixer1_out_tcon0: endpoint@0 { 275 reg = <0>; 276 remote-endpoint = <&tcon0_in_mixer1>; 277 }; 278 279 mixer1_out_tcon1: endpoint@1 { 280 reg = <1>; 281 remote-endpoint = <&tcon1_in_mixer1>; 282 }; 283 }; 284 }; 285 }; 286 }; 287 288 syscon: syscon@1c00000 { 289 compatible = "allwinner,sun50i-a64-system-control"; 290 reg = <0x01c00000 0x1000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 ranges; 294 295 sram_c: sram@18000 { 296 compatible = "mmio-sram"; 297 reg = <0x00018000 0x28000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges = <0 0x00018000 0x28000>; 301 302 de2_sram: sram-section@0 { 303 compatible = "allwinner,sun50i-a64-sram-c"; 304 reg = <0x0000 0x28000>; 305 }; 306 }; 307 308 sram_c1: sram@1d00000 { 309 compatible = "mmio-sram"; 310 reg = <0x01d00000 0x40000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0 0x01d00000 0x40000>; 314 315 ve_sram: sram-section@0 { 316 compatible = "allwinner,sun50i-a64-sram-c1", 317 "allwinner,sun4i-a10-sram-c1"; 318 reg = <0x000000 0x40000>; 319 }; 320 }; 321 }; 322 323 dma: dma-controller@1c02000 { 324 compatible = "allwinner,sun50i-a64-dma"; 325 reg = <0x01c02000 0x1000>; 326 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&ccu CLK_BUS_DMA>; 328 dma-channels = <8>; 329 dma-requests = <27>; 330 resets = <&ccu RST_BUS_DMA>; 331 #dma-cells = <1>; 332 }; 333 334 tcon0: lcd-controller@1c0c000 { 335 compatible = "allwinner,sun50i-a64-tcon-lcd", 336 "allwinner,sun8i-a83t-tcon-lcd"; 337 reg = <0x01c0c000 0x1000>; 338 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 340 clock-names = "ahb", "tcon-ch0"; 341 clock-output-names = "tcon-pixel-clock"; 342 #clock-cells = <0>; 343 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 344 reset-names = "lcd", "lvds"; 345 346 ports { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 tcon0_in: port@0 { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <0>; 354 355 tcon0_in_mixer0: endpoint@0 { 356 reg = <0>; 357 remote-endpoint = <&mixer0_out_tcon0>; 358 }; 359 360 tcon0_in_mixer1: endpoint@1 { 361 reg = <1>; 362 remote-endpoint = <&mixer1_out_tcon0>; 363 }; 364 }; 365 366 tcon0_out: port@1 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <1>; 370 371 tcon0_out_dsi: endpoint@1 { 372 reg = <1>; 373 remote-endpoint = <&dsi_in_tcon0>; 374 allwinner,tcon-channel = <1>; 375 }; 376 }; 377 }; 378 }; 379 380 tcon1: lcd-controller@1c0d000 { 381 compatible = "allwinner,sun50i-a64-tcon-tv", 382 "allwinner,sun8i-a83t-tcon-tv"; 383 reg = <0x01c0d000 0x1000>; 384 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 386 clock-names = "ahb", "tcon-ch1"; 387 resets = <&ccu RST_BUS_TCON1>; 388 reset-names = "lcd"; 389 390 ports { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 tcon1_in: port@0 { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 reg = <0>; 398 399 tcon1_in_mixer0: endpoint@0 { 400 reg = <0>; 401 remote-endpoint = <&mixer0_out_tcon1>; 402 }; 403 404 tcon1_in_mixer1: endpoint@1 { 405 reg = <1>; 406 remote-endpoint = <&mixer1_out_tcon1>; 407 }; 408 }; 409 410 tcon1_out: port@1 { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <1>; 414 415 tcon1_out_hdmi: endpoint@1 { 416 reg = <1>; 417 remote-endpoint = <&hdmi_in_tcon1>; 418 }; 419 }; 420 }; 421 }; 422 423 video-codec@1c0e000 { 424 compatible = "allwinner,sun50i-a64-video-engine"; 425 reg = <0x01c0e000 0x1000>; 426 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 427 <&ccu CLK_DRAM_VE>; 428 clock-names = "ahb", "mod", "ram"; 429 resets = <&ccu RST_BUS_VE>; 430 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 431 allwinner,sram = <&ve_sram 1>; 432 }; 433 434 mmc0: mmc@1c0f000 { 435 compatible = "allwinner,sun50i-a64-mmc"; 436 reg = <0x01c0f000 0x1000>; 437 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 438 clock-names = "ahb", "mmc"; 439 resets = <&ccu RST_BUS_MMC0>; 440 reset-names = "ahb"; 441 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 442 max-frequency = <150000000>; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 mmc1: mmc@1c10000 { 449 compatible = "allwinner,sun50i-a64-mmc"; 450 reg = <0x01c10000 0x1000>; 451 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 452 clock-names = "ahb", "mmc"; 453 resets = <&ccu RST_BUS_MMC1>; 454 reset-names = "ahb"; 455 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 456 max-frequency = <150000000>; 457 status = "disabled"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 }; 461 462 mmc2: mmc@1c11000 { 463 compatible = "allwinner,sun50i-a64-emmc"; 464 reg = <0x01c11000 0x1000>; 465 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 466 clock-names = "ahb", "mmc"; 467 resets = <&ccu RST_BUS_MMC2>; 468 reset-names = "ahb"; 469 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 470 max-frequency = <200000000>; 471 status = "disabled"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 }; 475 476 sid: eeprom@1c14000 { 477 compatible = "allwinner,sun50i-a64-sid"; 478 reg = <0x1c14000 0x400>; 479 #address-cells = <1>; 480 #size-cells = <1>; 481 482 ths_calibration: thermal-sensor-calibration@34 { 483 reg = <0x34 0x8>; 484 }; 485 }; 486 487 crypto: crypto@1c15000 { 488 compatible = "allwinner,sun50i-a64-crypto"; 489 reg = <0x01c15000 0x1000>; 490 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 492 clock-names = "bus", "mod"; 493 resets = <&ccu RST_BUS_CE>; 494 }; 495 496 usb_otg: usb@1c19000 { 497 compatible = "allwinner,sun8i-a33-musb"; 498 reg = <0x01c19000 0x0400>; 499 clocks = <&ccu CLK_BUS_OTG>; 500 resets = <&ccu RST_BUS_OTG>; 501 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "mc"; 503 phys = <&usbphy 0>; 504 phy-names = "usb"; 505 extcon = <&usbphy 0>; 506 dr_mode = "otg"; 507 status = "disabled"; 508 }; 509 510 usbphy: phy@1c19400 { 511 compatible = "allwinner,sun50i-a64-usb-phy"; 512 reg = <0x01c19400 0x14>, 513 <0x01c1a800 0x4>, 514 <0x01c1b800 0x4>; 515 reg-names = "phy_ctrl", 516 "pmu0", 517 "pmu1"; 518 clocks = <&ccu CLK_USB_PHY0>, 519 <&ccu CLK_USB_PHY1>; 520 clock-names = "usb0_phy", 521 "usb1_phy"; 522 resets = <&ccu RST_USB_PHY0>, 523 <&ccu RST_USB_PHY1>; 524 reset-names = "usb0_reset", 525 "usb1_reset"; 526 status = "disabled"; 527 #phy-cells = <1>; 528 }; 529 530 ehci0: usb@1c1a000 { 531 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 532 reg = <0x01c1a000 0x100>; 533 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&ccu CLK_BUS_OHCI0>, 535 <&ccu CLK_BUS_EHCI0>, 536 <&ccu CLK_USB_OHCI0>; 537 resets = <&ccu RST_BUS_OHCI0>, 538 <&ccu RST_BUS_EHCI0>; 539 status = "disabled"; 540 }; 541 542 ohci0: usb@1c1a400 { 543 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 544 reg = <0x01c1a400 0x100>; 545 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&ccu CLK_BUS_OHCI0>, 547 <&ccu CLK_USB_OHCI0>; 548 resets = <&ccu RST_BUS_OHCI0>; 549 status = "disabled"; 550 }; 551 552 ehci1: usb@1c1b000 { 553 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 554 reg = <0x01c1b000 0x100>; 555 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&ccu CLK_BUS_OHCI1>, 557 <&ccu CLK_BUS_EHCI1>, 558 <&ccu CLK_USB_OHCI1>; 559 resets = <&ccu RST_BUS_OHCI1>, 560 <&ccu RST_BUS_EHCI1>; 561 phys = <&usbphy 1>; 562 phy-names = "usb"; 563 status = "disabled"; 564 }; 565 566 ohci1: usb@1c1b400 { 567 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 568 reg = <0x01c1b400 0x100>; 569 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&ccu CLK_BUS_OHCI1>, 571 <&ccu CLK_USB_OHCI1>; 572 resets = <&ccu RST_BUS_OHCI1>; 573 phys = <&usbphy 1>; 574 phy-names = "usb"; 575 status = "disabled"; 576 }; 577 578 ccu: clock@1c20000 { 579 compatible = "allwinner,sun50i-a64-ccu"; 580 reg = <0x01c20000 0x400>; 581 clocks = <&osc24M>, <&rtc 0>; 582 clock-names = "hosc", "losc"; 583 #clock-cells = <1>; 584 #reset-cells = <1>; 585 }; 586 587 pio: pinctrl@1c20800 { 588 compatible = "allwinner,sun50i-a64-pinctrl"; 589 reg = <0x01c20800 0x400>; 590 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 594 clock-names = "apb", "hosc", "losc"; 595 gpio-controller; 596 #gpio-cells = <3>; 597 interrupt-controller; 598 #interrupt-cells = <3>; 599 600 csi_pins: csi-pins { 601 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 602 "PE7", "PE8", "PE9", "PE10", "PE11"; 603 function = "csi"; 604 }; 605 606 /omit-if-no-ref/ 607 csi_mclk_pin: csi-mclk-pin { 608 pins = "PE1"; 609 function = "csi"; 610 }; 611 612 i2c0_pins: i2c0-pins { 613 pins = "PH0", "PH1"; 614 function = "i2c0"; 615 }; 616 617 i2c1_pins: i2c1-pins { 618 pins = "PH2", "PH3"; 619 function = "i2c1"; 620 }; 621 622 /omit-if-no-ref/ 623 lcd_rgb666_pins: lcd-rgb666-pins { 624 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 625 "PD5", "PD6", "PD7", "PD8", "PD9", 626 "PD10", "PD11", "PD12", "PD13", 627 "PD14", "PD15", "PD16", "PD17", 628 "PD18", "PD19", "PD20", "PD21"; 629 function = "lcd0"; 630 }; 631 632 mmc0_pins: mmc0-pins { 633 pins = "PF0", "PF1", "PF2", "PF3", 634 "PF4", "PF5"; 635 function = "mmc0"; 636 drive-strength = <30>; 637 bias-pull-up; 638 }; 639 640 mmc1_pins: mmc1-pins { 641 pins = "PG0", "PG1", "PG2", "PG3", 642 "PG4", "PG5"; 643 function = "mmc1"; 644 drive-strength = <30>; 645 bias-pull-up; 646 }; 647 648 mmc2_pins: mmc2-pins { 649 pins = "PC5", "PC6", "PC8", "PC9", 650 "PC10","PC11", "PC12", "PC13", 651 "PC14", "PC15", "PC16"; 652 function = "mmc2"; 653 drive-strength = <30>; 654 bias-pull-up; 655 }; 656 657 mmc2_ds_pin: mmc2-ds-pin { 658 pins = "PC1"; 659 function = "mmc2"; 660 drive-strength = <30>; 661 bias-pull-up; 662 }; 663 664 pwm_pin: pwm-pin { 665 pins = "PD22"; 666 function = "pwm"; 667 }; 668 669 rmii_pins: rmii-pins { 670 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 671 "PD18", "PD19", "PD20", "PD22", "PD23"; 672 function = "emac"; 673 drive-strength = <40>; 674 }; 675 676 rgmii_pins: rgmii-pins { 677 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 678 "PD13", "PD15", "PD16", "PD17", "PD18", 679 "PD19", "PD20", "PD21", "PD22", "PD23"; 680 function = "emac"; 681 drive-strength = <40>; 682 }; 683 684 spdif_tx_pin: spdif-tx-pin { 685 pins = "PH8"; 686 function = "spdif"; 687 }; 688 689 spi0_pins: spi0-pins { 690 pins = "PC0", "PC1", "PC2", "PC3"; 691 function = "spi0"; 692 }; 693 694 spi1_pins: spi1-pins { 695 pins = "PD0", "PD1", "PD2", "PD3"; 696 function = "spi1"; 697 }; 698 699 uart0_pb_pins: uart0-pb-pins { 700 pins = "PB8", "PB9"; 701 function = "uart0"; 702 }; 703 704 uart1_pins: uart1-pins { 705 pins = "PG6", "PG7"; 706 function = "uart1"; 707 }; 708 709 uart1_rts_cts_pins: uart1-rts-cts-pins { 710 pins = "PG8", "PG9"; 711 function = "uart1"; 712 }; 713 714 uart2_pins: uart2-pins { 715 pins = "PB0", "PB1"; 716 function = "uart2"; 717 }; 718 719 uart3_pins: uart3-pins { 720 pins = "PD0", "PD1"; 721 function = "uart3"; 722 }; 723 724 uart4_pins: uart4-pins { 725 pins = "PD2", "PD3"; 726 function = "uart4"; 727 }; 728 729 uart4_rts_cts_pins: uart4-rts-cts-pins { 730 pins = "PD4", "PD5"; 731 function = "uart4"; 732 }; 733 }; 734 735 spdif: spdif@1c21000 { 736 #sound-dai-cells = <0>; 737 compatible = "allwinner,sun50i-a64-spdif", 738 "allwinner,sun8i-h3-spdif"; 739 reg = <0x01c21000 0x400>; 740 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 742 resets = <&ccu RST_BUS_SPDIF>; 743 clock-names = "apb", "spdif"; 744 dmas = <&dma 2>; 745 dma-names = "tx"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&spdif_tx_pin>; 748 status = "disabled"; 749 }; 750 751 lradc: lradc@1c21800 { 752 compatible = "allwinner,sun50i-a64-lradc", 753 "allwinner,sun8i-a83t-r-lradc"; 754 reg = <0x01c21800 0x400>; 755 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 756 status = "disabled"; 757 }; 758 759 i2s0: i2s@1c22000 { 760 #sound-dai-cells = <0>; 761 compatible = "allwinner,sun50i-a64-i2s", 762 "allwinner,sun8i-h3-i2s"; 763 reg = <0x01c22000 0x400>; 764 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 766 clock-names = "apb", "mod"; 767 resets = <&ccu RST_BUS_I2S0>; 768 dma-names = "rx", "tx"; 769 dmas = <&dma 3>, <&dma 3>; 770 status = "disabled"; 771 }; 772 773 i2s1: i2s@1c22400 { 774 #sound-dai-cells = <0>; 775 compatible = "allwinner,sun50i-a64-i2s", 776 "allwinner,sun8i-h3-i2s"; 777 reg = <0x01c22400 0x400>; 778 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 780 clock-names = "apb", "mod"; 781 resets = <&ccu RST_BUS_I2S1>; 782 dma-names = "rx", "tx"; 783 dmas = <&dma 4>, <&dma 4>; 784 status = "disabled"; 785 }; 786 787 dai: dai@1c22c00 { 788 #sound-dai-cells = <0>; 789 compatible = "allwinner,sun50i-a64-codec-i2s"; 790 reg = <0x01c22c00 0x200>; 791 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 793 clock-names = "apb", "mod"; 794 resets = <&ccu RST_BUS_CODEC>; 795 dmas = <&dma 15>, <&dma 15>; 796 dma-names = "rx", "tx"; 797 status = "disabled"; 798 }; 799 800 codec: codec@1c22e00 { 801 #sound-dai-cells = <0>; 802 compatible = "allwinner,sun8i-a33-codec"; 803 reg = <0x01c22e00 0x600>; 804 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 806 clock-names = "bus", "mod"; 807 status = "disabled"; 808 }; 809 810 ths: thermal-sensor@1c25000 { 811 compatible = "allwinner,sun50i-a64-ths"; 812 reg = <0x01c25000 0x100>; 813 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 814 clock-names = "bus", "mod"; 815 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 816 resets = <&ccu RST_BUS_THS>; 817 nvmem-cells = <&ths_calibration>; 818 nvmem-cell-names = "calibration"; 819 #thermal-sensor-cells = <1>; 820 }; 821 822 uart0: serial@1c28000 { 823 compatible = "snps,dw-apb-uart"; 824 reg = <0x01c28000 0x400>; 825 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 826 reg-shift = <2>; 827 reg-io-width = <4>; 828 clocks = <&ccu CLK_BUS_UART0>; 829 resets = <&ccu RST_BUS_UART0>; 830 status = "disabled"; 831 }; 832 833 uart1: serial@1c28400 { 834 compatible = "snps,dw-apb-uart"; 835 reg = <0x01c28400 0x400>; 836 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 837 reg-shift = <2>; 838 reg-io-width = <4>; 839 clocks = <&ccu CLK_BUS_UART1>; 840 resets = <&ccu RST_BUS_UART1>; 841 status = "disabled"; 842 }; 843 844 uart2: serial@1c28800 { 845 compatible = "snps,dw-apb-uart"; 846 reg = <0x01c28800 0x400>; 847 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 848 reg-shift = <2>; 849 reg-io-width = <4>; 850 clocks = <&ccu CLK_BUS_UART2>; 851 resets = <&ccu RST_BUS_UART2>; 852 status = "disabled"; 853 }; 854 855 uart3: serial@1c28c00 { 856 compatible = "snps,dw-apb-uart"; 857 reg = <0x01c28c00 0x400>; 858 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 859 reg-shift = <2>; 860 reg-io-width = <4>; 861 clocks = <&ccu CLK_BUS_UART3>; 862 resets = <&ccu RST_BUS_UART3>; 863 status = "disabled"; 864 }; 865 866 uart4: serial@1c29000 { 867 compatible = "snps,dw-apb-uart"; 868 reg = <0x01c29000 0x400>; 869 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 870 reg-shift = <2>; 871 reg-io-width = <4>; 872 clocks = <&ccu CLK_BUS_UART4>; 873 resets = <&ccu RST_BUS_UART4>; 874 status = "disabled"; 875 }; 876 877 i2c0: i2c@1c2ac00 { 878 compatible = "allwinner,sun6i-a31-i2c"; 879 reg = <0x01c2ac00 0x400>; 880 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&ccu CLK_BUS_I2C0>; 882 resets = <&ccu RST_BUS_I2C0>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&i2c0_pins>; 885 status = "disabled"; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 }; 889 890 i2c1: i2c@1c2b000 { 891 compatible = "allwinner,sun6i-a31-i2c"; 892 reg = <0x01c2b000 0x400>; 893 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&ccu CLK_BUS_I2C1>; 895 resets = <&ccu RST_BUS_I2C1>; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&i2c1_pins>; 898 status = "disabled"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 }; 902 903 i2c2: i2c@1c2b400 { 904 compatible = "allwinner,sun6i-a31-i2c"; 905 reg = <0x01c2b400 0x400>; 906 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&ccu CLK_BUS_I2C2>; 908 resets = <&ccu RST_BUS_I2C2>; 909 status = "disabled"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 }; 913 914 915 spi0: spi@1c68000 { 916 compatible = "allwinner,sun8i-h3-spi"; 917 reg = <0x01c68000 0x1000>; 918 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 920 clock-names = "ahb", "mod"; 921 dmas = <&dma 23>, <&dma 23>; 922 dma-names = "rx", "tx"; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&spi0_pins>; 925 resets = <&ccu RST_BUS_SPI0>; 926 status = "disabled"; 927 num-cs = <1>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 }; 931 932 spi1: spi@1c69000 { 933 compatible = "allwinner,sun8i-h3-spi"; 934 reg = <0x01c69000 0x1000>; 935 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 937 clock-names = "ahb", "mod"; 938 dmas = <&dma 24>, <&dma 24>; 939 dma-names = "rx", "tx"; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&spi1_pins>; 942 resets = <&ccu RST_BUS_SPI1>; 943 status = "disabled"; 944 num-cs = <1>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 }; 948 949 emac: ethernet@1c30000 { 950 compatible = "allwinner,sun50i-a64-emac"; 951 syscon = <&syscon>; 952 reg = <0x01c30000 0x10000>; 953 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 954 interrupt-names = "macirq"; 955 resets = <&ccu RST_BUS_EMAC>; 956 reset-names = "stmmaceth"; 957 clocks = <&ccu CLK_BUS_EMAC>; 958 clock-names = "stmmaceth"; 959 status = "disabled"; 960 961 mdio: mdio { 962 compatible = "snps,dwmac-mdio"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 }; 966 }; 967 968 mali: gpu@1c40000 { 969 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 970 reg = <0x01c40000 0x10000>; 971 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 978 interrupt-names = "gp", 979 "gpmmu", 980 "pp0", 981 "ppmmu0", 982 "pp1", 983 "ppmmu1", 984 "pmu"; 985 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 986 clock-names = "bus", "core"; 987 resets = <&ccu RST_BUS_GPU>; 988 }; 989 990 gic: interrupt-controller@1c81000 { 991 compatible = "arm,gic-400"; 992 reg = <0x01c81000 0x1000>, 993 <0x01c82000 0x2000>, 994 <0x01c84000 0x2000>, 995 <0x01c86000 0x2000>; 996 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 997 interrupt-controller; 998 #interrupt-cells = <3>; 999 }; 1000 1001 pwm: pwm@1c21400 { 1002 compatible = "allwinner,sun50i-a64-pwm", 1003 "allwinner,sun5i-a13-pwm"; 1004 reg = <0x01c21400 0x400>; 1005 clocks = <&osc24M>; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&pwm_pin>; 1008 #pwm-cells = <3>; 1009 status = "disabled"; 1010 }; 1011 1012 csi: csi@1cb0000 { 1013 compatible = "allwinner,sun50i-a64-csi"; 1014 reg = <0x01cb0000 0x1000>; 1015 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&ccu CLK_BUS_CSI>, 1017 <&ccu CLK_CSI_SCLK>, 1018 <&ccu CLK_DRAM_CSI>; 1019 clock-names = "bus", "mod", "ram"; 1020 resets = <&ccu RST_BUS_CSI>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&csi_pins>; 1023 status = "disabled"; 1024 }; 1025 1026 dsi: dsi@1ca0000 { 1027 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1028 reg = <0x01ca0000 0x1000>; 1029 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1031 resets = <&ccu RST_BUS_MIPI_DSI>; 1032 phys = <&dphy>; 1033 phy-names = "dphy"; 1034 status = "disabled"; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 1038 port { 1039 dsi_in_tcon0: endpoint { 1040 remote-endpoint = <&tcon0_out_dsi>; 1041 }; 1042 }; 1043 }; 1044 1045 dphy: d-phy@1ca1000 { 1046 compatible = "allwinner,sun50i-a64-mipi-dphy", 1047 "allwinner,sun6i-a31-mipi-dphy"; 1048 reg = <0x01ca1000 0x1000>; 1049 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1050 <&ccu CLK_DSI_DPHY>; 1051 clock-names = "bus", "mod"; 1052 resets = <&ccu RST_BUS_MIPI_DSI>; 1053 status = "disabled"; 1054 #phy-cells = <0>; 1055 }; 1056 1057 hdmi: hdmi@1ee0000 { 1058 compatible = "allwinner,sun50i-a64-dw-hdmi", 1059 "allwinner,sun8i-a83t-dw-hdmi"; 1060 reg = <0x01ee0000 0x10000>; 1061 reg-io-width = <1>; 1062 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1064 <&ccu CLK_HDMI>; 1065 clock-names = "iahb", "isfr", "tmds"; 1066 resets = <&ccu RST_BUS_HDMI1>; 1067 reset-names = "ctrl"; 1068 phys = <&hdmi_phy>; 1069 phy-names = "phy"; 1070 status = "disabled"; 1071 1072 ports { 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 1076 hdmi_in: port@0 { 1077 reg = <0>; 1078 1079 hdmi_in_tcon1: endpoint { 1080 remote-endpoint = <&tcon1_out_hdmi>; 1081 }; 1082 }; 1083 1084 hdmi_out: port@1 { 1085 reg = <1>; 1086 }; 1087 }; 1088 }; 1089 1090 hdmi_phy: hdmi-phy@1ef0000 { 1091 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1092 reg = <0x01ef0000 0x10000>; 1093 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1094 <&ccu 7>; 1095 clock-names = "bus", "mod", "pll-0"; 1096 resets = <&ccu RST_BUS_HDMI0>; 1097 reset-names = "phy"; 1098 #phy-cells = <0>; 1099 }; 1100 1101 rtc: rtc@1f00000 { 1102 compatible = "allwinner,sun50i-a64-rtc", 1103 "allwinner,sun8i-h3-rtc"; 1104 reg = <0x01f00000 0x400>; 1105 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1107 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1108 clocks = <&osc32k>; 1109 #clock-cells = <1>; 1110 }; 1111 1112 r_intc: interrupt-controller@1f00c00 { 1113 compatible = "allwinner,sun50i-a64-r-intc", 1114 "allwinner,sun6i-a31-r-intc"; 1115 interrupt-controller; 1116 #interrupt-cells = <2>; 1117 reg = <0x01f00c00 0x400>; 1118 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1119 }; 1120 1121 r_ccu: clock@1f01400 { 1122 compatible = "allwinner,sun50i-a64-r-ccu"; 1123 reg = <0x01f01400 0x100>; 1124 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1125 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1126 #clock-cells = <1>; 1127 #reset-cells = <1>; 1128 }; 1129 1130 codec_analog: codec-analog@1f015c0 { 1131 compatible = "allwinner,sun50i-a64-codec-analog"; 1132 reg = <0x01f015c0 0x4>; 1133 status = "disabled"; 1134 }; 1135 1136 r_i2c: i2c@1f02400 { 1137 compatible = "allwinner,sun50i-a64-i2c", 1138 "allwinner,sun6i-a31-i2c"; 1139 reg = <0x01f02400 0x400>; 1140 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&r_ccu CLK_APB0_I2C>; 1142 resets = <&r_ccu RST_APB0_I2C>; 1143 status = "disabled"; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 }; 1147 1148 r_ir: ir@1f02000 { 1149 compatible = "allwinner,sun50i-a64-ir", 1150 "allwinner,sun6i-a31-ir"; 1151 reg = <0x01f02000 0x400>; 1152 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1153 clock-names = "apb", "ir"; 1154 resets = <&r_ccu RST_APB0_IR>; 1155 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&r_ir_rx_pin>; 1158 status = "disabled"; 1159 }; 1160 1161 r_pwm: pwm@1f03800 { 1162 compatible = "allwinner,sun50i-a64-pwm", 1163 "allwinner,sun5i-a13-pwm"; 1164 reg = <0x01f03800 0x400>; 1165 clocks = <&osc24M>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&r_pwm_pin>; 1168 #pwm-cells = <3>; 1169 status = "disabled"; 1170 }; 1171 1172 r_pio: pinctrl@1f02c00 { 1173 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1174 reg = <0x01f02c00 0x400>; 1175 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1177 clock-names = "apb", "hosc", "losc"; 1178 gpio-controller; 1179 #gpio-cells = <3>; 1180 interrupt-controller; 1181 #interrupt-cells = <3>; 1182 1183 r_i2c_pl89_pins: r-i2c-pl89-pins { 1184 pins = "PL8", "PL9"; 1185 function = "s_i2c"; 1186 }; 1187 1188 r_ir_rx_pin: r-ir-rx-pin { 1189 pins = "PL11"; 1190 function = "s_cir_rx"; 1191 }; 1192 1193 r_pwm_pin: r-pwm-pin { 1194 pins = "PL10"; 1195 function = "s_pwm"; 1196 }; 1197 1198 r_rsb_pins: r-rsb-pins { 1199 pins = "PL0", "PL1"; 1200 function = "s_rsb"; 1201 }; 1202 }; 1203 1204 r_rsb: rsb@1f03400 { 1205 compatible = "allwinner,sun8i-a23-rsb"; 1206 reg = <0x01f03400 0x400>; 1207 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&r_ccu 6>; 1209 clock-frequency = <3000000>; 1210 resets = <&r_ccu 2>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&r_rsb_pins>; 1213 status = "disabled"; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 }; 1217 1218 wdt0: watchdog@1c20ca0 { 1219 compatible = "allwinner,sun50i-a64-wdt", 1220 "allwinner,sun6i-a31-wdt"; 1221 reg = <0x01c20ca0 0x20>; 1222 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&osc24M>; 1224 }; 1225 }; 1226}; 1227